\n

PM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCCTRL

PBBSEL

PBCSEL

PPCR

PBDSEL

RCAUSE

WCAUSE

AWEN

OBS

FASTSLEEP

CPUMASK

HSBMASK

PBAMASK

PBBMASK

PBCMASK

PBDMASK

CONFIG

VERSION

CPUSEL

PBADIVMASK

CFDCTRL

UNLOCK

PBASEL

IER

IDR

IMR

ISR

ICR

SR


MCCTRL

Main Clock Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCCTRL MCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCSEL

MCSEL : Main Clock Select
bits : 0 - 2 (3 bit)


PBBSEL

PBB Clock Select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBBSEL PBBSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBSEL PBDIV

PBSEL : PBB Clock Select
bits : 0 - 2 (3 bit)

PBDIV : PBB Division Select
bits : 7 - 7 (1 bit)


PBCSEL

PBC Clock Select
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBCSEL PBCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBSEL PBDIV

PBSEL : PBC Clock Select
bits : 0 - 2 (3 bit)

PBDIV : PBC Division Select
bits : 7 - 7 (1 bit)


PPCR

Peripheral Power Control Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPCR PPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTPUN CATBRCMASK ACIFCRCMASK ASTRCMASK TWIS0RCMASK TWIS1RCMASK PEVCRCMASK ADCIFERCMASK VREGRCMASK FWBGREF FWBOD18

RSTPUN : Reset Pullup
bits : 0 - 0 (1 bit)

CATBRCMASK : CAT Request Clock Mask
bits : 1 - 1 (1 bit)

ACIFCRCMASK : ACIFC Request Clock Mask
bits : 2 - 2 (1 bit)

ASTRCMASK : AST Request Clock Mask
bits : 3 - 3 (1 bit)

TWIS0RCMASK : TWIS0 Request Clock Mask
bits : 4 - 4 (1 bit)

TWIS1RCMASK : TWIS1 Request Clock Mask
bits : 5 - 5 (1 bit)

PEVCRCMASK : PEVC Request Clock Mask
bits : 6 - 6 (1 bit)

ADCIFERCMASK : ADCIFE Request Clock Mask
bits : 7 - 7 (1 bit)

VREGRCMASK : VREG Request Clock Mask
bits : 8 - 8 (1 bit)

FWBGREF : Flash Wait BGREF
bits : 9 - 9 (1 bit)

FWBOD18 : Flash Wait BOD18
bits : 10 - 10 (1 bit)


PBDSEL

PBD Clock Select
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBDSEL PBDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBSEL PBDIV

PBSEL : PBD Clock Select
bits : 0 - 2 (3 bit)

PBDIV : PBD Division Select
bits : 7 - 7 (1 bit)


RCAUSE

Reset Cause Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAUSE RCAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR BOD EXT WDT OCDRST POR33 BOD33

POR : Power-on Reset
bits : 0 - 0 (1 bit)

BOD : Brown-out Reset
bits : 1 - 1 (1 bit)

EXT : External Reset Pin
bits : 2 - 2 (1 bit)

WDT : Watchdog Reset
bits : 3 - 3 (1 bit)

OCDRST : OCD Reset
bits : 8 - 8 (1 bit)

POR33 : Power-on Reset
bits : 10 - 10 (1 bit)

BOD33 : Brown-out 3.3V Reset
bits : 13 - 13 (1 bit)


WCAUSE

Wake Cause Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WCAUSE WCAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWI_SLAVE_0 TWI_SLAVE_1 USBC PSOK BOD18_IRQ BOD33_IRQ PICOUART LCDCA EIC AST

TWI_SLAVE_0 : Two-wire Slave Interface 0
bits : 0 - 0 (1 bit)
access : read-only

TWI_SLAVE_1 : Two-wire Slave Interface 1
bits : 1 - 1 (1 bit)
access : read-only

USBC : USB Device and Embedded Host Interface
bits : 2 - 2 (1 bit)
access : read-only

PSOK : Power Scaling OK
bits : 3 - 3 (1 bit)
access : read-only

BOD18_IRQ : BOD18 Interrupt
bits : 4 - 4 (1 bit)
access : read-only

BOD33_IRQ : BOD33 Interrupt
bits : 5 - 5 (1 bit)
access : read-only

PICOUART : Picopower UART
bits : 6 - 6 (1 bit)
access : read-only

LCDCA : LCD Controller
bits : 7 - 7 (1 bit)
access : read-only

EIC : External Interrupt Controller
bits : 16 - 16 (1 bit)
access : read-only

AST : Asynchronous Timer
bits : 17 - 17 (1 bit)
access : read-only


AWEN

Asynchronous Wake Enable
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWEN AWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWEN

AWEN : Asynchronous Wake Up
bits : 0 - 31 (32 bit)


OBS

Obsvervability
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OBS OBS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FASTSLEEP

Fast Sleep Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FASTSLEEP FASTSLEEP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC PLL FASTRCOSC DFLL

OSC : Oscillator
bits : 0 - 0 (1 bit)

PLL : PLL
bits : 8 - 8 (1 bit)

FASTRCOSC : RC80 or FLO
bits : 16 - 20 (5 bit)

DFLL : DFLL
bits : 24 - 24 (1 bit)


CPUMASK

CPU Mask
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUMASK CPUMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCD_

OCD_ : OCD CPU Clock Mask
bits : 0 - 0 (1 bit)


HSBMASK

HSB Mask
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSBMASK HSBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDCA_ HFLASHC_ HRAMC1_ USBC_ CRCCU_ HTOP0_ HTOP1_ HTOP2_ HTOP3_ AESA_

PDCA_ : PDCA HSB Clock Mask
bits : 0 - 0 (1 bit)

HFLASHC_ : HFLASHC HSB Clock Mask
bits : 1 - 1 (1 bit)

HRAMC1_ : HRAMC1 HSB Clock Mask
bits : 2 - 2 (1 bit)

USBC_ : USBC HSB Clock Mask
bits : 3 - 3 (1 bit)

CRCCU_ : CRCCU HSB Clock Mask
bits : 4 - 4 (1 bit)

HTOP0_ : HTOP0 HSB Clock Mask
bits : 5 - 5 (1 bit)

HTOP1_ : HTOP1 HSB Clock Mask
bits : 6 - 6 (1 bit)

HTOP2_ : HTOP2 HSB Clock Mask
bits : 7 - 7 (1 bit)

HTOP3_ : HTOP3 HSB Clock Mask
bits : 8 - 8 (1 bit)

AESA_ : AESA HSB Clock Mask
bits : 9 - 9 (1 bit)


PBAMASK

PBA Mask
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBAMASK PBAMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IISC_ SPI_ TC0_ TC1_ TWIM0_ TWIS0_ TWIM1_ TWIS1_ USART0_ USART1_ USART2_ USART3_ ADCIFE_ DACC_ ACIFC_ GLOC_ ABDACB_ TRNG_ PARC_ CATB_ TWIM2_ TWIM3_ LCDCA_

IISC_ : IISC APB Clock Enable
bits : 0 - 0 (1 bit)

SPI_ : SPI APB Clock Enable
bits : 1 - 1 (1 bit)

TC0_ : TC0 APB Clock Enable
bits : 2 - 2 (1 bit)

TC1_ : TC1 APB Clock Enable
bits : 3 - 3 (1 bit)

TWIM0_ : TWIM0 APB Clock Enable
bits : 4 - 4 (1 bit)

TWIS0_ : TWIS0 APB Clock Enable
bits : 5 - 5 (1 bit)

TWIM1_ : TWIM1 APB Clock Enable
bits : 6 - 6 (1 bit)

TWIS1_ : TWIS1 APB Clock Enable
bits : 7 - 7 (1 bit)

USART0_ : USART0 APB Clock Enable
bits : 8 - 8 (1 bit)

USART1_ : USART1 APB Clock Enable
bits : 9 - 9 (1 bit)

USART2_ : USART2 APB Clock Enable
bits : 10 - 10 (1 bit)

USART3_ : USART3 APB Clock Enable
bits : 11 - 11 (1 bit)

ADCIFE_ : ADCIFE APB Clock Enable
bits : 12 - 12 (1 bit)

DACC_ : DACC APB Clock Enable
bits : 13 - 13 (1 bit)

ACIFC_ : ACIFC APB Clock Enable
bits : 14 - 14 (1 bit)

GLOC_ : GLOC APB Clock Enable
bits : 15 - 15 (1 bit)

ABDACB_ : ABDACB APB Clock Enable
bits : 16 - 16 (1 bit)

TRNG_ : TRNG APB Clock Enable
bits : 17 - 17 (1 bit)

PARC_ : PARC APB Clock Enable
bits : 18 - 18 (1 bit)

CATB_ : CATB APB Clock Enable
bits : 19 - 19 (1 bit)

TWIM2_ : TWIM2 APB Clock Enable
bits : 21 - 21 (1 bit)

TWIM3_ : TWIM3 APB Clock Enable
bits : 22 - 22 (1 bit)

LCDCA_ : LCDCA APB Clock Enable
bits : 23 - 23 (1 bit)


PBBMASK

PBB Mask
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBBMASK PBBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFLASHC_ HCACHE_ HMATRIX_ PDCA_ CRCCU_ USBC_ PEVC_

HFLASHC_ : HFLASHC APB Clock Enable
bits : 0 - 0 (1 bit)

HCACHE_ : HCACHE APB Clock Enable
bits : 1 - 1 (1 bit)

HMATRIX_ : HMATRIX APB Clock Enable
bits : 2 - 2 (1 bit)

PDCA_ : PDCA APB Clock Enable
bits : 3 - 3 (1 bit)

CRCCU_ : CRCCU APB Clock Enable
bits : 4 - 4 (1 bit)

USBC_ : USBC APB Clock Enable
bits : 5 - 5 (1 bit)

PEVC_ : PEVC APB Clock Enable
bits : 6 - 6 (1 bit)


PBCMASK

PBC Mask
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBCMASK PBCMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM_ CHIPID_ SCIF_ FREQM_ GPIO_

PM_ : PM APB Clock Enable
bits : 0 - 0 (1 bit)

CHIPID_ : CHIPID APB Clock Enable
bits : 1 - 1 (1 bit)

SCIF_ : SCIF APB Clock Enable
bits : 2 - 2 (1 bit)

FREQM_ : FREQM APB Clock Enable
bits : 3 - 3 (1 bit)

GPIO_ : GPIO APB Clock Enable
bits : 4 - 4 (1 bit)


PBDMASK

PBD Mask
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBDMASK PBDMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BPM_ BSCIF_ AST_ WDT_ EIC_ PICOUART_

BPM_ : BPM APB Clock Enable
bits : 0 - 0 (1 bit)

BSCIF_ : BSCIF APB Clock Enable
bits : 1 - 1 (1 bit)

AST_ : AST APB Clock Enable
bits : 2 - 2 (1 bit)

WDT_ : WDT APB Clock Enable
bits : 3 - 3 (1 bit)

EIC_ : EIC APB Clock Enable
bits : 4 - 4 (1 bit)

PICOUART_ : PICOUART APB Clock Enable
bits : 5 - 5 (1 bit)


CONFIG

Configuration Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBA PBB PBC PBD HSBPEVC

PBA : APBA Implemented
bits : 0 - 0 (1 bit)

PBB : APBB Implemented
bits : 1 - 1 (1 bit)

PBC : APBC Implemented
bits : 2 - 2 (1 bit)

PBD : APBD Implemented
bits : 3 - 3 (1 bit)

HSBPEVC : HSB PEVC Clock Implemented
bits : 7 - 7 (1 bit)


VERSION

Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant number
bits : 16 - 19 (4 bit)
access : read-only


CPUSEL

CPU Clock Select
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUSEL CPUSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUSEL CPUDIV

CPUSEL : CPU Clock Select
bits : 0 - 2 (3 bit)

Enumeration: CPUSELSelect

0x0 : 0

fCPU:fmain. CPUDIV:

0x1 : 1

fCPU:fmain / 2^(CPUSEL+1)

End of enumeration elements list.

CPUDIV : CPU Division
bits : 7 - 7 (1 bit)


PBADIVMASK

PBA Divided Clock Mask
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBADIVMASK PBADIVMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFDCTRL

Clock Failure Detector Control
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFDCTRL CFDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFDEN SFV

CFDEN : Clock Failure Detection Enable
bits : 0 - 0 (1 bit)

SFV : Store Final Value
bits : 31 - 31 (1 bit)


UNLOCK

Unlock Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR KEY

ADDR : Unlock Address
bits : 0 - 9 (10 bit)

KEY : Unlock Key
bits : 24 - 31 (8 bit)


PBASEL

PBA Clock Select
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBASEL PBASEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBSEL PBDIV

PBSEL : PBA Clock Select
bits : 0 - 2 (3 bit)

PBDIV : PBA Division Select
bits : 7 - 7 (1 bit)


IER

Interrupt Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD CKRDY WAKE AE

CFD : Clock Failure Detected Interrupt Enable
bits : 0 - 0 (1 bit)

CKRDY : Clock Ready Interrupt Enable
bits : 5 - 5 (1 bit)

WAKE : Wake up Interrupt Enable
bits : 8 - 8 (1 bit)

Enumeration: WAKESelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

AE : Access Error Interrupt Enable
bits : 31 - 31 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD CKRDY WAKE AE

CFD : Clock Failure Detected Interrupt Disable
bits : 0 - 0 (1 bit)

CKRDY : Clock Ready Interrupt Disable
bits : 5 - 5 (1 bit)

WAKE : Wake up Interrupt Disable
bits : 8 - 8 (1 bit)

Enumeration: WAKESelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

AE : Access Error Interrupt Disable
bits : 31 - 31 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD CKRDY WAKE AE

CFD : Clock Failure Detected Interrupt Mask
bits : 0 - 0 (1 bit)

CKRDY : Clock Ready Interrupt Mask
bits : 5 - 5 (1 bit)

WAKE : Wake up Interrupt Mask
bits : 8 - 8 (1 bit)

Enumeration: WAKESelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

AE : Access Error Interrupt Mask
bits : 31 - 31 (1 bit)


ISR

Interrupt Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD CKRDY WAKE AE

CFD : Clock Failure Detected Interrupt Status
bits : 0 - 0 (1 bit)

CKRDY : Clock Ready Interrupt Status
bits : 5 - 5 (1 bit)

WAKE : Wake up Interrupt Status
bits : 8 - 8 (1 bit)

Enumeration: WAKESelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

AE : Access Error Interrupt Status
bits : 31 - 31 (1 bit)


ICR

Interrupt Clear Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD CKRDY WAKE AE

CFD : Clock Failure Detected Interrupt Status Clear
bits : 0 - 0 (1 bit)

CKRDY : Clock Ready Interrupt Status Clear
bits : 5 - 5 (1 bit)

WAKE : Wake up Interrupt Status Clear
bits : 8 - 8 (1 bit)

AE : Access Error Interrupt Status Clear
bits : 31 - 31 (1 bit)


SR

Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFD OCP CKRDY WAKE PERRDY AE

CFD : Clock Failure Detected
bits : 0 - 0 (1 bit)

OCP : Over Clock Detected
bits : 1 - 1 (1 bit)

CKRDY : Clock Ready
bits : 5 - 5 (1 bit)

WAKE : Wake up
bits : 8 - 8 (1 bit)

Enumeration: WAKESelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

PERRDY : Peripheral Ready
bits : 28 - 28 (1 bit)

AE : Access Error
bits : 31 - 31 (1 bit)



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