\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : WDT Enable
bits : 0 - 0 (1 bit)
Enumeration: ENSelect
0x0 : 0
WDT is disabled.
0x1 : 1
WDT is enabled
End of enumeration elements list.
DAR : WDT Disable After Reset
bits : 1 - 1 (1 bit)
MODE : WDT Mode
bits : 2 - 2 (1 bit)
SFV : WDT Store Final Value
bits : 3 - 3 (1 bit)
IM : WDT Interruput Mode
bits : 4 - 4 (1 bit)
FCD : WDT Fuse Calibration Done
bits : 7 - 7 (1 bit)
PSEL : Timeout Prescale Select
bits : 8 - 12 (5 bit)
CSSEL1 : Clock Source Selection1
bits : 14 - 14 (1 bit)
CEN : Clock Enable
bits : 16 - 16 (1 bit)
CSSEL : Clock Source Selection0
bits : 17 - 17 (1 bit)
TBAN : TBAN Prescale Select
bits : 18 - 22 (5 bit)
KEY : Key
bits : 24 - 31 (8 bit)
Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WINT : Watchdog Interrupt
bits : 2 - 2 (1 bit)
Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WINT : Watchdog Interrupt
bits : 2 - 2 (1 bit)
Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WINT : Watchdog Interrupt
bits : 2 - 2 (1 bit)
Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WINT : Watchdog Interrupt
bits : 2 - 2 (1 bit)
Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WDTCLR : Clear WDT counter
bits : 0 - 0 (1 bit)
access : write-only
KEY : Key
bits : 24 - 31 (8 bit)
access : write-only
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WINDOW : WDT in window
bits : 0 - 0 (1 bit)
access : read-only
CLEARED : WDT cleared
bits : 1 - 1 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WINT : Watchdog Interrupt
bits : 2 - 2 (1 bit)
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