\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Maintenance Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INVALL : Cache Controller Invalidate All
bits : 0 - 0 (1 bit)
access : write-only
Enumeration: INVALLSelect
0x0 : NO
No effect
0x1 : YES
Invalidate all cache entries
End of enumeration elements list.
Maintenance Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INDEX : Invalidate Index
bits : 4 - 7 (4 bit)
access : write-only
Monitor Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Cache Controller Monitor Counter Mode
bits : 0 - 1 (2 bit)
Enumeration: MODESelect
0x0 : CYCLE
Cycle Counter
0x1 : IHIT
Instruction Hit Counter
0x2 : DHIT
Data Hit Counter
End of enumeration elements list.
Monitor Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MENABLE : Monitor Enable
bits : 0 - 0 (1 bit)
access : write-only
Enumeration: MENABLESelect
0x0 : DIS
Disable Monitor Counter
0x1 : EN
Enable Monitor Counter
End of enumeration elements list.
Monitor Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Monitor Software Reset
bits : 0 - 0 (1 bit)
access : write-only
Enumeration: SWRSTSelect
0x0 : NO
No effect
0x1 : YES
Reset event counter register
End of enumeration elements list.
Monitor Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENTCNT : Monitor Event Counter
bits : 0 - 31 (32 bit)
access : read-only
Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CEN : Cache Enable
bits : 0 - 0 (1 bit)
access : write-only
Enumeration: CENSelect
0x0 : NO
Disable Cache Controller
0x1 : YES
Enable Cache Controller
End of enumeration elements list.
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSTS : Cache Controller Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration: CSTSSelect
0x0 : DIS
Cache Controller Disabled
0x1 : EN
Cache Controller Enabled
End of enumeration elements list.
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : VERSION
bits : 0 - 11 (12 bit)
access : read-only
MFN : MFN
bits : 16 - 19 (4 bit)
access : read-only
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