\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only
DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only
DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only
DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only
DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only
PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only
PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only
RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only
RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only
AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only
DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only
DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only
DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only
DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only
PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only
PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only
RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only
RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only
AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only
Power and Clocks Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only
DFLL0LOCKC : DFLL0 Locked on Coarse Value
bits : 1 - 1 (1 bit)
access : read-only
DFLL0LOCKF : DFLL0 Locked on Fine Value
bits : 2 - 2 (1 bit)
access : read-only
DFLL0RDY : DFLL0 Synchronization Ready
bits : 3 - 3 (1 bit)
access : read-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only
DFLL0OOB : DFLL0 Track Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only
PLL0LOCK : PLL0 Locked on Accurate value
bits : 6 - 6 (1 bit)
access : read-only
PLL0LOCKLOST : PLL0 lock lost value
bits : 7 - 7 (1 bit)
access : read-only
RCFASTLOCK : RCFAST Locked on Accurate value
bits : 13 - 13 (1 bit)
access : read-only
RCFASTLOCKLOST : RCFAST lock lost value
bits : 14 - 14 (1 bit)
access : read-only
Generic Clock Control
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Unlock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Unlock Address
bits : 0 - 9 (10 bit)
access : write-only
KEY : Unlock Key
bits : 24 - 31 (8 bit)
access : write-only
Chip Specific Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Generic Clock Control
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Oscillator Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Oscillator Mode
bits : 0 - 0 (1 bit)
GAIN : Gain
bits : 1 - 2 (2 bit)
AGC : Automatic Gain Control
bits : 3 - 3 (1 bit)
STARTUP : Oscillator Start-up Time
bits : 8 - 11 (4 bit)
OSCEN : Oscillator Enable
bits : 16 - 16 (1 bit)
PLL0 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLEN : PLL Enable
bits : 0 - 0 (1 bit)
PLLOSC : PLL Oscillator Select
bits : 1 - 2 (2 bit)
PLLOPT : PLL Option
bits : 3 - 5 (3 bit)
PLLDIV : PLL Division Factor
bits : 8 - 11 (4 bit)
PLLMUL : PLL Multiply Factor
bits : 16 - 19 (4 bit)
PLLCOUNT : PLL Count
bits : 24 - 29 (6 bit)
Generic Clock Control
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
DFLL0 Config Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
MODE : Mode Selection
bits : 1 - 1 (1 bit)
STABLE : Stable DFLL Frequency
bits : 2 - 2 (1 bit)
LLAW : Lose Lock After Wake
bits : 3 - 3 (1 bit)
CCDIS : Chill Cycle Disable
bits : 5 - 5 (1 bit)
QLDIS : Quick Lock Disable
bits : 6 - 6 (1 bit)
RANGE : Range Value
bits : 16 - 17 (2 bit)
FCD : Fuse Calibration Done
bits : 23 - 23 (1 bit)
CALIB : Calibration Value
bits : 24 - 27 (4 bit)
DFLL Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINE : Fine Value
bits : 0 - 7 (8 bit)
COARSE : Coarse Value
bits : 16 - 20 (5 bit)
Generic Clock Control
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
DFLL0 Multiplier Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUL : DFLL Multiply Factor
bits : 0 - 15 (16 bit)
DFLL0 Step Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSTEP : Fine Maximum Step
bits : 0 - 7 (8 bit)
CSTEP : Coarse Maximum Step
bits : 16 - 20 (5 bit)
Generic Clock Control
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
DFLL0 Spread Spectrum Generator Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
access : write-only
PRBS : Pseudo Random Bit Sequence
bits : 1 - 1 (1 bit)
access : write-only
AMPLITUDE : SSG Amplitude
bits : 8 - 12 (5 bit)
access : write-only
STEPSIZE : SSG Step Size
bits : 16 - 20 (5 bit)
access : write-only
DFLL0 Ratio Registe
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RATIODIFF : Multiplication Ratio Difference
bits : 0 - 15 (16 bit)
access : read-only
4/8/12 MHz RC Oscillator Version Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Generic Clock Prescaler Version Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
PLL Version Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant nubmer
bits : 16 - 19 (4 bit)
Oscillator 0 Version Register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant nubmer
bits : 16 - 19 (4 bit)
DFLL Version Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
System RC Oscillator Version Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Frequency Locked Oscillator Version Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Generic Clock Control
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
80MHz RC Oscillator Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Generic Clock Version Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
SCIF Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Interrupt Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only
DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only
DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only
DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only
DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only
PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only
PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only
RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only
RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only
AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only
DFLL0 Synchronization Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchronization
bits : 0 - 0 (1 bit)
access : write-only
System RC Oscillator Calibration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALIB : Calibration Value
bits : 0 - 9 (10 bit)
FCD : Flash Calibration Done
bits : 16 - 16 (1 bit)
4/8/12 MHz RC Oscillator Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Oscillator Enable
bits : 0 - 0 (1 bit)
TUNEEN : Tuner Enable
bits : 1 - 1 (1 bit)
JITMODE : Jitter Mode
bits : 2 - 2 (1 bit)
NBPERIODS : Number of 32kHz Periods
bits : 4 - 6 (3 bit)
FCD : RCFAST Fuse Calibration Done
bits : 7 - 7 (1 bit)
FRANGE : Frequency Range
bits : 8 - 9 (2 bit)
LOCKMARGIN : Accepted Count Error for Lock
bits : 12 - 15 (4 bit)
CALIB : Oscillator Calibration Value
bits : 16 - 22 (7 bit)
Generic Clock Control
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
4/8/12 MHz RC Oscillator Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURTRIM : Current Trim Value
bits : 0 - 6 (7 bit)
CNTERR : Current Count Error
bits : 16 - 20 (5 bit)
SIGN : Sign of Current Count Error
bits : 21 - 21 (1 bit)
LOCK : Lock
bits : 24 - 24 (1 bit)
LOCKLOST : Lock Lost
bits : 25 - 25 (1 bit)
UPDATED : Current Trim Value Updated
bits : 31 - 31 (1 bit)
80 MHz RC Oscillator Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
FCD : Flash Calibration Done
bits : 7 - 7 (1 bit)
CALIB : Calibration Value
bits : 16 - 17 (2 bit)
Generic Clock Control
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Control
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
High Resolution Prescaler Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRPEN : High Resolution Prescaler Enable
bits : 0 - 0 (1 bit)
CKSEL : Clock Input Selection
bits : 1 - 3 (3 bit)
HRCOUNT : High Resolution Counter
bits : 8 - 31 (24 bit)
Generic Clock Control
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Fractional Prescaler Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPEN : High Resolution Prescaler Enable
bits : 0 - 0 (1 bit)
CKSEL : Clock Input Selection
bits : 1 - 3 (3 bit)
Fractional Prescaler Multiplier Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPMUL : Fractional Prescaler Multiplication Factor
bits : 0 - 15 (16 bit)
Generic Clock Control
address_offset : 0x6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Fractional Prescaler DIVIDER Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPDIV : Fractional Prescaler Division Factor
bits : 0 - 15 (16 bit)
Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only
DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : read-only
DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : read-only
DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : read-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only
DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only
PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : read-only
PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : read-only
RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : read-only
RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : read-only
AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only
DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : read-only
DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : read-only
DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : read-only
DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only
DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only
PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : read-only
PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : read-only
RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : read-only
RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : read-only
AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only
Generic Clock Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Clock Enable
bits : 0 - 0 (1 bit)
DIVEN : Divide Enable
bits : 1 - 1 (1 bit)
OSCSEL : Clock Select
bits : 8 - 12 (5 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
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