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SCIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IER

ICR

PCLKSR

GCCTRL1

UNLOCK

CSCR

GCCTRL2

OSCCTRL0

PLL

GCCTRL3

DFLL0CONF

DFLL0VAL

GCCTRL4

DFLL0MUL

DFLL0STEP

GCCTRL5

DFLL0SSG

DFLL0RATIO

RCFASTVERSION

GCLKPRESCVERSION

PLLIFAVERSION

OSCIFAVERSION

DFLLIFBVERSION

RCOSCIFAVERSION

FLOVERSION

GCCTRL6

RC80MVERSION

GCLKIFVERSION

VERSION

IDR

DFLL0SYNC

RCCR

RCFASTCFG

GCCTRL7

RCFASTSR

RC80MCR

GCCTRL8

GCCTRL9

HRPCR

GCCTRL10

FPCR

FPMUL

GCCTRL11

FPDIV

IMR

ISR

GCCTRL0


IER

Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST AE

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only

DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only

DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only

DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only

DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only

PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only

PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only

RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only

RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


ICR

Interrupt Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST AE

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only

DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only

DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only

DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only

DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only

PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only

PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only

RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only

RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


PCLKSR

Power and Clocks Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCLKSR PCLKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only

DFLL0LOCKC : DFLL0 Locked on Coarse Value
bits : 1 - 1 (1 bit)
access : read-only

DFLL0LOCKF : DFLL0 Locked on Fine Value
bits : 2 - 2 (1 bit)
access : read-only

DFLL0RDY : DFLL0 Synchronization Ready
bits : 3 - 3 (1 bit)
access : read-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only

DFLL0OOB : DFLL0 Track Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only

PLL0LOCK : PLL0 Locked on Accurate value
bits : 6 - 6 (1 bit)
access : read-only

PLL0LOCKLOST : PLL0 lock lost value
bits : 7 - 7 (1 bit)
access : read-only

RCFASTLOCK : RCFAST Locked on Accurate value
bits : 13 - 13 (1 bit)
access : read-only

RCFASTLOCKLOST : RCFAST lock lost value
bits : 14 - 14 (1 bit)
access : read-only


GCCTRL1

Generic Clock Control
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL1 GCCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


UNLOCK

Unlock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR KEY

ADDR : Unlock Address
bits : 0 - 9 (10 bit)
access : write-only

KEY : Unlock Key
bits : 24 - 31 (8 bit)
access : write-only


CSCR

Chip Specific Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCR CSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GCCTRL2

Generic Clock Control
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL2 GCCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


OSCCTRL0

Oscillator Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCTRL0 OSCCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE GAIN AGC STARTUP OSCEN

MODE : Oscillator Mode
bits : 0 - 0 (1 bit)

GAIN : Gain
bits : 1 - 2 (2 bit)

AGC : Automatic Gain Control
bits : 3 - 3 (1 bit)

STARTUP : Oscillator Start-up Time
bits : 8 - 11 (4 bit)

OSCEN : Oscillator Enable
bits : 16 - 16 (1 bit)


PLL

PLL0 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL PLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLEN PLLOSC PLLOPT PLLDIV PLLMUL PLLCOUNT

PLLEN : PLL Enable
bits : 0 - 0 (1 bit)

PLLOSC : PLL Oscillator Select
bits : 1 - 2 (2 bit)

PLLOPT : PLL Option
bits : 3 - 5 (3 bit)

PLLDIV : PLL Division Factor
bits : 8 - 11 (4 bit)

PLLMUL : PLL Multiply Factor
bits : 16 - 19 (4 bit)

PLLCOUNT : PLL Count
bits : 24 - 29 (6 bit)


GCCTRL3

Generic Clock Control
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL3 GCCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


DFLL0CONF

DFLL0 Config Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLL0CONF DFLL0CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE STABLE LLAW CCDIS QLDIS RANGE FCD CALIB

EN : Enable
bits : 0 - 0 (1 bit)

MODE : Mode Selection
bits : 1 - 1 (1 bit)

STABLE : Stable DFLL Frequency
bits : 2 - 2 (1 bit)

LLAW : Lose Lock After Wake
bits : 3 - 3 (1 bit)

CCDIS : Chill Cycle Disable
bits : 5 - 5 (1 bit)

QLDIS : Quick Lock Disable
bits : 6 - 6 (1 bit)

RANGE : Range Value
bits : 16 - 17 (2 bit)

FCD : Fuse Calibration Done
bits : 23 - 23 (1 bit)

CALIB : Calibration Value
bits : 24 - 27 (4 bit)


DFLL0VAL

DFLL Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLL0VAL DFLL0VAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINE COARSE

FINE : Fine Value
bits : 0 - 7 (8 bit)

COARSE : Coarse Value
bits : 16 - 20 (5 bit)


GCCTRL4

Generic Clock Control
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL4 GCCTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


DFLL0MUL

DFLL0 Multiplier Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLL0MUL DFLL0MUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUL

MUL : DFLL Multiply Factor
bits : 0 - 15 (16 bit)


DFLL0STEP

DFLL0 Step Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLL0STEP DFLL0STEP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSTEP CSTEP

FSTEP : Fine Maximum Step
bits : 0 - 7 (8 bit)

CSTEP : Coarse Maximum Step
bits : 16 - 20 (5 bit)


GCCTRL5

Generic Clock Control
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL5 GCCTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


DFLL0SSG

DFLL0 Spread Spectrum Generator Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLL0SSG DFLL0SSG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PRBS AMPLITUDE STEPSIZE

EN : Enable
bits : 0 - 0 (1 bit)
access : write-only

PRBS : Pseudo Random Bit Sequence
bits : 1 - 1 (1 bit)
access : write-only

AMPLITUDE : SSG Amplitude
bits : 8 - 12 (5 bit)
access : write-only

STEPSIZE : SSG Step Size
bits : 16 - 20 (5 bit)
access : write-only


DFLL0RATIO

DFLL0 Ratio Registe
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFLL0RATIO DFLL0RATIO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RATIODIFF

RATIODIFF : Multiplication Ratio Difference
bits : 0 - 15 (16 bit)
access : read-only


RCFASTVERSION

4/8/12 MHz RC Oscillator Version Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCFASTVERSION RCFASTVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


GCLKPRESCVERSION

Generic Clock Prescaler Version Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GCLKPRESCVERSION GCLKPRESCVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


PLLIFAVERSION

PLL Version Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLLIFAVERSION PLLIFAVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant nubmer
bits : 16 - 19 (4 bit)


OSCIFAVERSION

Oscillator 0 Version Register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSCIFAVERSION OSCIFAVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant nubmer
bits : 16 - 19 (4 bit)


DFLLIFBVERSION

DFLL Version Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFLLIFBVERSION DFLLIFBVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


RCOSCIFAVERSION

System RC Oscillator Version Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCOSCIFAVERSION RCOSCIFAVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


FLOVERSION

Frequency Locked Oscillator Version Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLOVERSION FLOVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


GCCTRL6

Generic Clock Control
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL6 GCCTRL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


RC80MVERSION

80MHz RC Oscillator Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RC80MVERSION RC80MVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


GCLKIFVERSION

Generic Clock Version Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GCLKIFVERSION GCLKIFVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


VERSION

SCIF Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


IDR

Interrupt Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST AE

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : write-only

DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : write-only

DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : write-only

DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : write-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : write-only

DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : write-only

PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : write-only

PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : write-only

RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : write-only

RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


DFLL0SYNC

DFLL0 Synchronization Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DFLL0SYNC DFLL0SYNC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC

SYNC : Synchronization
bits : 0 - 0 (1 bit)
access : write-only


RCCR

System RC Oscillator Calibration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCR RCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALIB FCD

CALIB : Calibration Value
bits : 0 - 9 (10 bit)

FCD : Flash Calibration Done
bits : 16 - 16 (1 bit)


RCFASTCFG

4/8/12 MHz RC Oscillator Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCFASTCFG RCFASTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TUNEEN JITMODE NBPERIODS FCD FRANGE LOCKMARGIN CALIB

EN : Oscillator Enable
bits : 0 - 0 (1 bit)

TUNEEN : Tuner Enable
bits : 1 - 1 (1 bit)

JITMODE : Jitter Mode
bits : 2 - 2 (1 bit)

NBPERIODS : Number of 32kHz Periods
bits : 4 - 6 (3 bit)

FCD : RCFAST Fuse Calibration Done
bits : 7 - 7 (1 bit)

FRANGE : Frequency Range
bits : 8 - 9 (2 bit)

LOCKMARGIN : Accepted Count Error for Lock
bits : 12 - 15 (4 bit)

CALIB : Oscillator Calibration Value
bits : 16 - 22 (7 bit)


GCCTRL7

Generic Clock Control
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL7 GCCTRL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


RCFASTSR

4/8/12 MHz RC Oscillator Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCFASTSR RCFASTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURTRIM CNTERR SIGN LOCK LOCKLOST UPDATED

CURTRIM : Current Trim Value
bits : 0 - 6 (7 bit)

CNTERR : Current Count Error
bits : 16 - 20 (5 bit)

SIGN : Sign of Current Count Error
bits : 21 - 21 (1 bit)

LOCK : Lock
bits : 24 - 24 (1 bit)

LOCKLOST : Lock Lost
bits : 25 - 25 (1 bit)

UPDATED : Current Trim Value Updated
bits : 31 - 31 (1 bit)


RC80MCR

80 MHz RC Oscillator Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC80MCR RC80MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN FCD CALIB

EN : Enable
bits : 0 - 0 (1 bit)

FCD : Flash Calibration Done
bits : 7 - 7 (1 bit)

CALIB : Calibration Value
bits : 16 - 17 (2 bit)


GCCTRL8

Generic Clock Control
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL8 GCCTRL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GCCTRL9

Generic Clock Control
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL9 GCCTRL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


HRPCR

High Resolution Prescaler Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRPCR HRPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRPEN CKSEL HRCOUNT

HRPEN : High Resolution Prescaler Enable
bits : 0 - 0 (1 bit)

CKSEL : Clock Input Selection
bits : 1 - 3 (3 bit)

HRCOUNT : High Resolution Counter
bits : 8 - 31 (24 bit)


GCCTRL10

Generic Clock Control
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL10 GCCTRL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


FPCR

Fractional Prescaler Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCR FPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPEN CKSEL

FPEN : High Resolution Prescaler Enable
bits : 0 - 0 (1 bit)

CKSEL : Clock Input Selection
bits : 1 - 3 (3 bit)


FPMUL

Fractional Prescaler Multiplier Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPMUL FPMUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPMUL

FPMUL : Fractional Prescaler Multiplication Factor
bits : 0 - 15 (16 bit)


GCCTRL11

Generic Clock Control
address_offset : 0x6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL11 GCCTRL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


FPDIV

Fractional Prescaler DIVIDER Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDIV FPDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPDIV

FPDIV : Fractional Prescaler Division Factor
bits : 0 - 15 (16 bit)


IMR

Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST AE

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only

DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : read-only

DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : read-only

DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : read-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only

DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only

PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : read-only

PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : read-only

RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : read-only

RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : read-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC0RDY DFLL0LOCKC DFLL0LOCKF DFLL0RDY DFLL0RCS DFLL0OOB PLL0LOCK PLL0LOCKLOST RCFASTLOCK RCFASTLOCKLOST AE

OSC0RDY : OSC0 Ready
bits : 0 - 0 (1 bit)
access : read-only

DFLL0LOCKC : DFLL0 Lock Coarse
bits : 1 - 1 (1 bit)
access : read-only

DFLL0LOCKF : DFLL0 Lock Fine
bits : 2 - 2 (1 bit)
access : read-only

DFLL0RDY : DFLL0 Ready
bits : 3 - 3 (1 bit)
access : read-only

DFLL0RCS : DFLL0 Reference Clock Stopped
bits : 4 - 4 (1 bit)
access : read-only

DFLL0OOB : DFLL0 Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only

PLL0LOCK : PLL0 Lock
bits : 6 - 6 (1 bit)
access : read-only

PLL0LOCKLOST : PLL0 Lock Lost
bits : 7 - 7 (1 bit)
access : read-only

RCFASTLOCK : RCFAST Lock
bits : 13 - 13 (1 bit)
access : read-only

RCFASTLOCKLOST : RCFAST Lock Lost
bits : 14 - 14 (1 bit)
access : read-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only


GCCTRL0

Generic Clock Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCCTRL0 GCCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN DIVEN OSCSEL DIV

CEN : Clock Enable
bits : 0 - 0 (1 bit)

DIVEN : Divide Enable
bits : 1 - 1 (1 bit)

OSCSEL : Clock Select
bits : 8 - 12 (5 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)



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