\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DIS : Disable
bits : 0 - 0 (1 bit)
access : write-only
EN : Enable
bits : 1 - 1 (1 bit)
access : write-only
FC0DIS : Frame Counter 0 Disable
bits : 2 - 2 (1 bit)
access : write-only
FC0EN : Frame Counter 0 Enable
bits : 3 - 3 (1 bit)
access : write-only
FC1DIS : Frame Counter 1 Disable
bits : 4 - 4 (1 bit)
access : write-only
FC1EN : Frame Counter 1 Enable
bits : 5 - 5 (1 bit)
access : write-only
FC2DIS : Frame Counter 2 Disable
bits : 6 - 6 (1 bit)
access : write-only
FC2EN : Frame Counter 2 Enable
bits : 7 - 7 (1 bit)
access : write-only
CDM : Clear Display Memory
bits : 8 - 8 (1 bit)
access : write-only
WDIS : Wake up Disable
bits : 9 - 9 (1 bit)
access : write-only
WEN : Wake up Enable
bits : 10 - 10 (1 bit)
access : write-only
BSTART : Blinking Start
bits : 11 - 11 (1 bit)
access : write-only
BSTOP : Blinking Stop
bits : 12 - 12 (1 bit)
access : write-only
CSTART : Circular Shift Start
bits : 13 - 13 (1 bit)
access : write-only
CSTOP : Circular Shift Stop
bits : 14 - 14 (1 bit)
access : write-only
Status Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FC0R : Frame Counter 0 Rollover
bits : 0 - 0 (1 bit)
access : write-only
Data Register Low 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 31 (32 bit)
Data Register High 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
Data Register Low 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 31 (32 bit)
Data Register High 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
Data Register Low 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 31 (32 bit)
Data Register High 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
Data Register Low 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 31 (32 bit)
Data Register High 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
Indirect Access Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
access : write-only
DMASK : Data Mask
bits : 8 - 15 (8 bit)
access : write-only
OFF : Byte Offset
bits : 16 - 20 (5 bit)
access : write-only
Blink Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Blinking Mode
bits : 0 - 0 (1 bit)
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
BSS0 : Blink Segment Selection 0
bits : 8 - 11 (4 bit)
BSS1 : Blink Segment Selection 1
bits : 12 - 15 (4 bit)
Circular Shift Register Configuration
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Direction
bits : 0 - 0 (1 bit)
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
SIZE : Size
bits : 3 - 5 (3 bit)
DATA : Circular Shift Register Value
bits : 8 - 15 (8 bit)
Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XBIAS : External Bias Generation
bits : 0 - 0 (1 bit)
WMOD : Waveform Mode
bits : 1 - 1 (1 bit)
BLANK : Blank LCD
bits : 2 - 2 (1 bit)
LOCK : Lock
bits : 3 - 3 (1 bit)
DUTY : Duty Select
bits : 8 - 9 (2 bit)
FCST : Fine Contrast
bits : 16 - 21 (6 bit)
NSU : Number of Segment Terminals in Use
bits : 24 - 29 (6 bit)
Character Mapping Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DREV : Digit Reverse Mode
bits : 0 - 0 (1 bit)
TDG : Type of Digit
bits : 1 - 2 (2 bit)
STSEG : Start Segment
bits : 8 - 13 (6 bit)
Character Mapping Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ASCII : ASCII Code
bits : 0 - 6 (7 bit)
access : write-only
Automated Character Mapping Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
MODE : Mode (sequential or scrolling)
bits : 3 - 3 (1 bit)
DREV : Digit Reverse
bits : 4 - 4 (1 bit)
TDG : Type of Digit
bits : 5 - 6 (2 bit)
STSEG : Start Segment
bits : 8 - 13 (6 bit)
STEPS : Scrolling Steps
bits : 16 - 23 (8 bit)
DIGN : Digit Number
bits : 24 - 27 (4 bit)
Automated Character Mapping Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ASCII : ASCII Code
bits : 0 - 6 (7 bit)
access : write-only
Automated Bit Mapping Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
SIZE : Size
bits : 8 - 12 (5 bit)
Automated Bit Mapping Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Segments Value
bits : 0 - 7 (8 bit)
access : write-only
DMASK : Data Mask
bits : 8 - 15 (8 bit)
access : write-only
OFF : Byte Offset
bits : 16 - 20 (5 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FC0R : Frame Counter 0 Rollover
bits : 0 - 0 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FC0R : Frame Counter 0 Rollover
bits : 0 - 0 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FC0R : Frame Counter 0 Rollover
bits : 0 - 0 (1 bit)
access : read-only
Version Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only
VARIANT : Variant Number
bits : 16 - 19 (4 bit)
access : read-only
Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : LCD Prescaler Select
bits : 0 - 0 (1 bit)
CLKDIV : LCD Clock Division
bits : 1 - 3 (3 bit)
FC0 : Frame Counter 0
bits : 8 - 12 (5 bit)
FC0PB : Frame Counter 0 Prescaler Bypass
bits : 13 - 13 (1 bit)
FC1 : Frame Counter 1
bits : 16 - 20 (5 bit)
FC2 : Frame Counter 2
bits : 24 - 28 (5 bit)
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FC0R : Frame Counter 0 Rollover
bits : 0 - 0 (1 bit)
access : read-only
FC0S : Frame Counter 0 Status
bits : 1 - 1 (1 bit)
access : read-only
FC1S : Frame Counter 1 Status
bits : 2 - 2 (1 bit)
access : read-only
FC2S : Frame Counter 2 Status
bits : 3 - 3 (1 bit)
access : read-only
EN : LCDCA Status
bits : 4 - 4 (1 bit)
access : read-only
WEN : Wake up Status
bits : 5 - 5 (1 bit)
access : read-only
BLKS : Blink Status
bits : 6 - 6 (1 bit)
access : read-only
CSRS : Circular Shift Register Status
bits : 7 - 7 (1 bit)
access : read-only
CPS : Charge Pump Status
bits : 8 - 8 (1 bit)
access : read-only
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