Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receive Enable
bits : 0 - 0 (1 bit)
Enumeration: RXENSelect
0x0 : OFF
No effect
0x1 : ON
Enables Data Receive if RXDIS is not set
End of enumeration elements list.
RXDIS : Receive Disable
bits : 1 - 1 (1 bit)
Enumeration: RXDISSelect
0x0 : OFF
No effect
0x1 : ON
Disables Data Receive
End of enumeration elements list.
CKEN : Clocks Enable
bits : 2 - 2 (1 bit)
Enumeration: CKENSelect
0x0 : OFF
No effect
0x1 : ON
Enables clocks if CKDIS is not set
End of enumeration elements list.
CKDIS : Clocks Disable
bits : 3 - 3 (1 bit)
Enumeration: CKDISSelect
0x0 : OFF
No effect
0x1 : ON
Disables clocks
End of enumeration elements list.
TXEN : Transmit Enable
bits : 4 - 4 (1 bit)
Enumeration: TXENSelect
0x0 : OFF
No effect
0x1 : ON
Enables Data Transmit if TXDIS is not set
End of enumeration elements list.
TXDIS : Transmit Disable
bits : 5 - 5 (1 bit)
Enumeration: TXDISSelect
0x0 : OFF
No effect
0x1 : ON
Disables Data Transmit
End of enumeration elements list.
SWRST : Software Reset
bits : 7 - 7 (1 bit)
Enumeration: SWRSTSelect
0x0 : OFF
No effect
0x1 : ON
Performs a software reset. Has priority on any other bit in CR
End of enumeration elements list.
Status Set Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXOR : Receive Overrun
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : NO
No effect
0x1 : SET
Sets corresponding SR bit
End of enumeration elements list.
TXUR : Transmit Underrun
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : NO
No effect
0x1 : SET
Sets corresponding SR bit
End of enumeration elements list.
RXORCH : Receive Overrun Channels
bits : 8 - 9 (2 bit)
TXURCH : Transmit Underrun Channels
bits : 20 - 21 (2 bit)
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Enable
bits : 1 - 1 (1 bit)
Enumeration: RXRDYSelect
0x0 : OFF
No effect
0x1 : ON
Enables the corresponding interrupt
End of enumeration elements list.
RXOR : Receive Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : OFF
No effect
0x1 : ON
Enables the corresponding interrupt
End of enumeration elements list.
TXRDY : Transmit Ready Interrupt Enable
bits : 5 - 5 (1 bit)
Enumeration: TXRDYSelect
0x0 : OFF
No effect
0x1 : ON
Enables the corresponding interrupt
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Enable
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : OFF
No effect
0x1 : ON
Enables the corresponding interrupt
End of enumeration elements list.
Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receive Ready Interrupt Disable
bits : 1 - 1 (1 bit)
Enumeration: RXRDYSelect
0x0 : OFF
No effect
0x1 : ON
Disables the corresponding interrupt
End of enumeration elements list.
RXOR : Receive Overrun Interrupt Disable
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : OFF
No effect
0x1 : ON
Disables the corresponding interrupt
End of enumeration elements list.
TXRDY : Transmit Ready Interrupt Disable
bits : 5 - 5 (1 bit)
Enumeration: TXRDYSelect
0x0 : OFF
No effect
0x1 : ON
Disables the corresponding interrupt
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Disable
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : OFF
No effect
0x1 : ON
Disables the corresponding interrupt
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receive Ready Interrupt Mask
bits : 1 - 1 (1 bit)
Enumeration: RXRDYSelect
0x0 : DISABLED
The corresponding interrupt is disabled
0x1 : ENABLED
The corresponding interrupt is enabled
End of enumeration elements list.
RXOR : Receive Overrun Interrupt Mask
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : DISABLED
The corresponding interrupt is disabled
0x1 : ENABLED
The corresponding interrupt is enabled
End of enumeration elements list.
TXRDY : Transmit Ready Interrupt Mask
bits : 5 - 5 (1 bit)
Enumeration: TXRDYSelect
0x0 : DISABLED
The corresponding interrupt is disabled
0x1 : ENABLED
The corresponding interrupt is enabled
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Mask
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : DISABLED
The corresponding interrupt is disabled
0x1 : ENABLED
The corresponding interrupt is enabled
End of enumeration elements list.
Receive Holding Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDAT : Receive Data
bits : 0 - 31 (32 bit)
Transmit Holding Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDAT : Transmit Data
bits : 0 - 31 (32 bit)
Version Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell.
bits : 0 - 11 (12 bit)
VARIANT : Reserved. Value subject to change. No functionality associated.
bits : 16 - 19 (4 bit)
Parameter Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FORMAT : Data protocol format
bits : 7 - 7 (1 bit)
Enumeration: FORMATSelect
0x0 : I2S
I2S format, stereo with IWS low for left channel
End of enumeration elements list.
NBCHAN : Maximum number of channels - 1
bits : 16 - 20 (5 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Master/Slave/Controller Mode
bits : 0 - 0 (1 bit)
Enumeration: MODESelect
0x0 : SLAVE
Slave mode (only serial data handled, clocks received from external master or controller)
0x1 : MASTER
Master mode (clocks generated and output by IISC, serial data handled if CR.RXEN and/or CR.TXEN written to 1)
End of enumeration elements list.
DATALENGTH : Data Word Length
bits : 2 - 4 (3 bit)
Enumeration: DATALENGTHSelect
0x0 : 32
32 bits
0x1 : 24
24 bits
0x2 : 20
20 bits
0x3 : 18
18 bits
0x4 : 16
16 bits
0x5 : 16C
16 bits compact stereo
0x6 : 8
8 bits
0x7 : 8C
8 bits compact stereo
End of enumeration elements list.
RXMONO : Receiver Mono
bits : 8 - 8 (1 bit)
Enumeration: RXMONOSelect
0x0 : STEREO
Normal mode
0x1 : MONO
Left channel data is duplicated to right channel
End of enumeration elements list.
RXDMA : Single or Multiple DMA Channels for Receiver
bits : 9 - 9 (1 bit)
Enumeration: RXDMASelect
0x0 : SINGLE
Single DMA channel
0x1 : MULTIPLE
One DMA channel per data channel
End of enumeration elements list.
RXLOOP : Loop-back Test Mode
bits : 10 - 10 (1 bit)
Enumeration: RXLOOPSelect
0x0 : OFF
Normal mode
0x1 : ON
ISDO internally connected to ISDI
End of enumeration elements list.
TXMONO : Transmitter Mono
bits : 12 - 12 (1 bit)
Enumeration: TXMONOSelect
0x0 : STEREO
Normal mode
0x1 : MONO
Left channel data is duplicated to right channel
End of enumeration elements list.
TXDMA : Single or Multiple DMA Channels for Transmitter
bits : 13 - 13 (1 bit)
Enumeration: TXDMASelect
0x0 : SINGLE
Single DMA channel
0x1 : MULTIPLE
One DMA channel per data channel
End of enumeration elements list.
TXSAME : Transmit Data when Underrun
bits : 14 - 14 (1 bit)
Enumeration: TXSAMESelect
0x0 : ZERO
Zero data transmitted in case of underrun
0x1 : SAME
Last data transmitted in case of underrun
End of enumeration elements list.
IMCKFS : Master Clock to fs Ratio
bits : 24 - 29 (6 bit)
Enumeration: IMCKFSSelect
0x0 : 16
16 fs
0x1 : 32
32 fs
0x3 : 64
64 fs
0x7 : 128
128 fs
0xf : 256
256 fs
0x17 : 384
384 fs
0x1f : 512
512 fs
0x2f : 768
768 fs
0x3f : 1024
1024 fs
End of enumeration elements list.
IMCKMODE : Master Clock Mode
bits : 30 - 30 (1 bit)
Enumeration: IMCKMODESelect
0x0 : NO_IMCK
No IMCK generated
0x1 : IMCK
IMCK generated
End of enumeration elements list.
IWS24 : IWS Data Slot Width
bits : 31 - 31 (1 bit)
Enumeration: IWS24Select
0x0 : 32
IWS Data Slot is 32-bit wide for DATALENGTH=18/20/24-bit
0x1 : 24
IWS Data Slot is 24-bit wide for DATALENGTH=18/20/24-bit
End of enumeration elements list.
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receive Enable
bits : 0 - 0 (1 bit)
Enumeration: RXENSelect
0x0 : OFF
Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request
0x1 : ON
Receiver is effectively enabled, following a CR.RXEN request
End of enumeration elements list.
RXRDY : Receive Ready
bits : 1 - 1 (1 bit)
Enumeration: RXRDYSelect
0x0 : EMPTY
The register RHR is empty and can't be read
0x1 : FULL
The register RHR is full and is ready to be read
End of enumeration elements list.
RXOR : Receive Overrun
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : NO
No overrun
0x1 : YES
The previous received data has not been read. This data is lost
End of enumeration elements list.
TXEN : Transmit Enable
bits : 4 - 4 (1 bit)
Enumeration: TXENSelect
0x0 : OFF
Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request
0x1 : ON
Transmitter is effectively enabled, following a CR.TXEN request
End of enumeration elements list.
TXRDY : Transmit Ready
bits : 5 - 5 (1 bit)
Enumeration: TXRDYSelect
0x0 : FULL
The register THR is full and can't be written
0x1 : EMPTY
The register THR is empty and is ready to be written
End of enumeration elements list.
TXUR : Transmit Underrun
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : NO
No underrun
0x1 : YES
The last bit of the last data written to the register THR has been set. Until the next write to THR, data will be sent according to MR.TXSAME field
End of enumeration elements list.
RXORCH : Receive Overrun Channels
bits : 8 - 9 (2 bit)
Enumeration: RXORCHSelect
0x0 : LEFT
Overrun first occurred on left channel
0x1 : RIGHT
Overrun first occurred on right channel
End of enumeration elements list.
TXURCH : Transmit Underrun Channels
bits : 20 - 21 (2 bit)
Enumeration: TXURCHSelect
0x0 : LEFT
Underrun first occurred on left channel
0x1 : RIGHT
Underrun first occurred on right channel
End of enumeration elements list.
Status Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXOR : Receive Overrun
bits : 2 - 2 (1 bit)
Enumeration: RXORSelect
0x0 : NO
No effect
0x1 : CLEAR
Clears the corresponding SR bit
End of enumeration elements list.
TXUR : Transmit Underrun
bits : 6 - 6 (1 bit)
Enumeration: TXURSelect
0x0 : NO
No effect
0x1 : CLEAR
Clears the corresponding SR bit
End of enumeration elements list.
RXORCH : Receive Overrun Channels
bits : 8 - 9 (2 bit)
TXURCH : Transmit Underrun Channels
bits : 20 - 21 (2 bit)
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