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TWIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TWIM_CR

CR

TWIM_NCMDR

NCMDR

TWIM_RHR

RHR

TWIM_THR

THR

TWIM_SR

SR

TWIM_IER

IER

TWIM_IDR

IDR

TWIM_IMR

IMR

TWIM_SCR

SCR

TWIM_PR

PR

TWIM_VR

VR

TWIM_HSCWGR

HSCWGR

TWIM_SRR

SRR

TWIM_CWGR

CWGR

TWIM_HSSRR

HSSRR

TWIM_SMBTR

SMBTR

TWIM_CMDR

CMDR


TWIM_CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_CR TWIM_CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEN MDIS SMEN SMDIS SWRST STOP

MEN : Master Enable
bits : 0 - 0 (1 bit)

MDIS : Master Disable
bits : 1 - 1 (1 bit)

SMEN : SMBus Enable
bits : 4 - 4 (1 bit)

SMDIS : SMBus Disable
bits : 5 - 5 (1 bit)

SWRST : Software Reset
bits : 7 - 7 (1 bit)

STOP : Stop the current transfer
bits : 8 - 8 (1 bit)


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEN MDIS SMEN SMDIS SWRST STOP

MEN : Master Enable
bits : 0 - 0 (1 bit)

MDIS : Master Disable
bits : 1 - 1 (1 bit)

SMEN : SMBus Enable
bits : 4 - 4 (1 bit)

SMDIS : SMBus Disable
bits : 5 - 5 (1 bit)

SWRST : Software Reset
bits : 7 - 7 (1 bit)

STOP : Stop the current transfer
bits : 8 - 8 (1 bit)


TWIM_NCMDR

Next Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_NCMDR TWIM_NCMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ SADR TENBIT REPSAME START STOP VALID NBYTES PECEN ACKLAST HS HSMCODE

READ : Transfer Direction
bits : 0 - 0 (1 bit)

SADR : Slave Address
bits : 1 - 10 (10 bit)

TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)

REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)

START : Send START condition
bits : 13 - 13 (1 bit)

STOP : Send STOP condition
bits : 14 - 14 (1 bit)

VALID : CMDR Valid
bits : 15 - 15 (1 bit)

NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)

PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)

ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)

HS : HS-mode
bits : 26 - 26 (1 bit)

HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)


NCMDR

Next Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCMDR NCMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ SADR TENBIT REPSAME START STOP VALID NBYTES PECEN ACKLAST HS HSMCODE

READ : Transfer Direction
bits : 0 - 0 (1 bit)

SADR : Slave Address
bits : 1 - 10 (10 bit)

TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)

REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)

START : Send START condition
bits : 13 - 13 (1 bit)

STOP : Send STOP condition
bits : 14 - 14 (1 bit)

VALID : CMDR Valid
bits : 15 - 15 (1 bit)

NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)

PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)

ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)

HS : HS-mode
bits : 26 - 26 (1 bit)

HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)


TWIM_RHR

Receive Holding Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_RHR TWIM_RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Received Data
bits : 0 - 7 (8 bit)


RHR

Receive Holding Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Received Data
bits : 0 - 7 (8 bit)


TWIM_THR

Transmit Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_THR TWIM_THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Data to Transmit
bits : 0 - 7 (8 bit)


THR

Transmit Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Data to Transmit
bits : 0 - 7 (8 bit)


TWIM_SR

Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_SR TWIM_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP MENB HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

MENB : Master Interface Enable
bits : 16 - 16 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


SR

Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP MENB HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

MENB : Master Interface Enable
bits : 16 - 16 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


TWIM_IER

Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_IER TWIM_IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


TWIM_IDR

Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_IDR TWIM_IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


TWIM_IMR

Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_IMR TWIM_IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY CRDY CCOMP IDLE BUSFREE ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)

TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)

CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)

BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


TWIM_SCR

Status Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_SCR TWIM_SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCOMP ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


SCR

Status Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCOMP ANAK DNAK ARBLST SMBALERT TOUT PECERR STOP HSMCACK

CCOMP : Command Complete
bits : 3 - 3 (1 bit)

ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)

DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)

ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)

SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)

TOUT : Timeout
bits : 12 - 12 (1 bit)

PECERR : PEC Error
bits : 13 - 13 (1 bit)

STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)

HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)


TWIM_PR

Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_PR TWIM_PR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS

HS : HS-mode
bits : 0 - 0 (1 bit)


PR

Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PR PR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS

HS : HS-mode
bits : 0 - 0 (1 bit)


TWIM_VR

Version Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIM_VR TWIM_VR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


VR

Version Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VR VR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant number
bits : 16 - 19 (4 bit)


TWIM_HSCWGR

HS-mode Clock Waveform Generator
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_HSCWGR TWIM_HSCWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH STASTO DATA EXP

LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)

HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)

STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)

DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)

EXP : Clock Prescaler
bits : 28 - 30 (3 bit)


HSCWGR

HS-mode Clock Waveform Generator
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSCWGR HSCWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH STASTO DATA EXP

LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)

HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)

STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)

DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)

EXP : Clock Prescaler
bits : 28 - 30 (3 bit)


TWIM_SRR

Slew Rate Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_SRR TWIM_SRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADRIVEL DASLEW CLDRIVEL CLSLEW FILTER

DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)

DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)

CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)

CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)

FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)


SRR

Slew Rate Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRR SRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADRIVEL DASLEW CLDRIVEL CLSLEW FILTER

DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)

DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)

CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)

CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)

FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)


TWIM_CWGR

Clock Waveform Generator Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_CWGR TWIM_CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH STASTO DATA EXP

LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)

HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)

STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)

DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)

EXP : Clock Prescaler
bits : 28 - 30 (3 bit)


CWGR

Clock Waveform Generator Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWGR CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW HIGH STASTO DATA EXP

LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)

HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)

STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)

DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)

EXP : Clock Prescaler
bits : 28 - 30 (3 bit)


TWIM_HSSRR

HS-mode Slew Rate Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_HSSRR TWIM_HSSRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADRIVEL DASLEW CLDRIVEL CLDRIVEH CLSLEW FILTER

DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)

DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)

CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)

CLDRIVEH : Clock Drive Strength HIGH
bits : 20 - 21 (2 bit)

CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)

FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)


HSSRR

HS-mode Slew Rate Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSSRR HSSRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DADRIVEL DASLEW CLDRIVEL CLDRIVEH CLSLEW FILTER

DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)

DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)

CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)

CLDRIVEH : Clock Drive Strength HIGH
bits : 20 - 21 (2 bit)

CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)

FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)


TWIM_SMBTR

SMBus Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_SMBTR TWIM_SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLOWS TLOWM THMAX EXP

TLOWS : Slave Clock stretch maximum cycles
bits : 0 - 7 (8 bit)

TLOWM : Master Clock stretch maximum cycles
bits : 8 - 15 (8 bit)

THMAX : Clock High maximum cycles
bits : 16 - 23 (8 bit)

EXP : SMBus Timeout Clock prescaler
bits : 28 - 31 (4 bit)


SMBTR

SMBus Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMBTR SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLOWS TLOWM THMAX EXP

TLOWS : Slave Clock stretch maximum cycles
bits : 0 - 7 (8 bit)

TLOWM : Master Clock stretch maximum cycles
bits : 8 - 15 (8 bit)

THMAX : Clock High maximum cycles
bits : 16 - 23 (8 bit)

EXP : SMBus Timeout Clock prescaler
bits : 28 - 31 (4 bit)


TWIM_CMDR

Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIM_CMDR TWIM_CMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ SADR TENBIT REPSAME START STOP VALID NBYTES PECEN ACKLAST HS HSMCODE

READ : Transfer Direction
bits : 0 - 0 (1 bit)

SADR : Slave Address
bits : 1 - 10 (10 bit)

TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)

REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)

START : Send START condition
bits : 13 - 13 (1 bit)

STOP : Send STOP condition
bits : 14 - 14 (1 bit)

VALID : CMDR Valid
bits : 15 - 15 (1 bit)

NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)

PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)

ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)

HS : HS-mode
bits : 26 - 26 (1 bit)

HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)


CMDR

Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMDR CMDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ SADR TENBIT REPSAME START STOP VALID NBYTES PECEN ACKLAST HS HSMCODE

READ : Transfer Direction
bits : 0 - 0 (1 bit)

SADR : Slave Address
bits : 1 - 10 (10 bit)

TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)

REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)

START : Send START condition
bits : 13 - 13 (1 bit)

STOP : Send STOP condition
bits : 14 - 14 (1 bit)

VALID : CMDR Valid
bits : 15 - 15 (1 bit)

NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)

PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)

ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)

HS : HS-mode
bits : 26 - 26 (1 bit)

HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)



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