\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MEN : Master Enable
bits : 0 - 0 (1 bit)
MDIS : Master Disable
bits : 1 - 1 (1 bit)
SMEN : SMBus Enable
bits : 4 - 4 (1 bit)
SMDIS : SMBus Disable
bits : 5 - 5 (1 bit)
SWRST : Software Reset
bits : 7 - 7 (1 bit)
STOP : Stop the current transfer
bits : 8 - 8 (1 bit)
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MEN : Master Enable
bits : 0 - 0 (1 bit)
MDIS : Master Disable
bits : 1 - 1 (1 bit)
SMEN : SMBus Enable
bits : 4 - 4 (1 bit)
SMDIS : SMBus Disable
bits : 5 - 5 (1 bit)
SWRST : Software Reset
bits : 7 - 7 (1 bit)
STOP : Stop the current transfer
bits : 8 - 8 (1 bit)
Next Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ : Transfer Direction
bits : 0 - 0 (1 bit)
SADR : Slave Address
bits : 1 - 10 (10 bit)
TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)
REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)
START : Send START condition
bits : 13 - 13 (1 bit)
STOP : Send STOP condition
bits : 14 - 14 (1 bit)
VALID : CMDR Valid
bits : 15 - 15 (1 bit)
NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)
PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)
ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)
HS : HS-mode
bits : 26 - 26 (1 bit)
HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)
Next Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ : Transfer Direction
bits : 0 - 0 (1 bit)
SADR : Slave Address
bits : 1 - 10 (10 bit)
TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)
REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)
START : Send START condition
bits : 13 - 13 (1 bit)
STOP : Send STOP condition
bits : 14 - 14 (1 bit)
VALID : CMDR Valid
bits : 15 - 15 (1 bit)
NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)
PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)
ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)
HS : HS-mode
bits : 26 - 26 (1 bit)
HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)
Receive Holding Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received Data
bits : 0 - 7 (8 bit)
Receive Holding Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received Data
bits : 0 - 7 (8 bit)
Transmit Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Data to Transmit
bits : 0 - 7 (8 bit)
Transmit Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Data to Transmit
bits : 0 - 7 (8 bit)
Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
MENB : Master Interface Enable
bits : 16 - 16 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
MENB : Master Interface Enable
bits : 16 - 16 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RHR Data Ready
bits : 0 - 0 (1 bit)
TXRDY : THR Data Ready
bits : 1 - 1 (1 bit)
CRDY : Ready for More Commands
bits : 2 - 2 (1 bit)
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
IDLE : Master Interface is Idle
bits : 4 - 4 (1 bit)
BUSFREE : Two-wire Bus is Free
bits : 5 - 5 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Status Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Status Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CCOMP : Command Complete
bits : 3 - 3 (1 bit)
ANAK : NAK in Address Phase Received
bits : 8 - 8 (1 bit)
DNAK : NAK in Data Phase Received
bits : 9 - 9 (1 bit)
ARBLST : Arbitration Lost
bits : 10 - 10 (1 bit)
SMBALERT : SMBus Alert
bits : 11 - 11 (1 bit)
TOUT : Timeout
bits : 12 - 12 (1 bit)
PECERR : PEC Error
bits : 13 - 13 (1 bit)
STOP : Stop Request Accepted
bits : 14 - 14 (1 bit)
HSMCACK : ACK in HS-mode Master Code Phase Received
bits : 17 - 17 (1 bit)
Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HS : HS-mode
bits : 0 - 0 (1 bit)
Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HS : HS-mode
bits : 0 - 0 (1 bit)
Version Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
Version Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version number
bits : 0 - 11 (12 bit)
VARIANT : Variant number
bits : 16 - 19 (4 bit)
HS-mode Clock Waveform Generator
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)
HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)
STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)
DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)
EXP : Clock Prescaler
bits : 28 - 30 (3 bit)
HS-mode Clock Waveform Generator
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)
HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)
STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)
DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)
EXP : Clock Prescaler
bits : 28 - 30 (3 bit)
Slew Rate Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)
DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)
CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)
CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)
FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)
Slew Rate Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)
DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)
CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)
CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)
FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)
Clock Waveform Generator Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)
HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)
STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)
DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)
EXP : Clock Prescaler
bits : 28 - 30 (3 bit)
Clock Waveform Generator Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW : Clock Low Cycles
bits : 0 - 7 (8 bit)
HIGH : Clock High Cycles
bits : 8 - 15 (8 bit)
STASTO : START and STOP Cycles
bits : 16 - 23 (8 bit)
DATA : Data Setup and Hold Cycles
bits : 24 - 27 (4 bit)
EXP : Clock Prescaler
bits : 28 - 30 (3 bit)
HS-mode Slew Rate Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)
DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)
CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)
CLDRIVEH : Clock Drive Strength HIGH
bits : 20 - 21 (2 bit)
CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)
FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)
HS-mode Slew Rate Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADRIVEL : Data Drive Strength LOW
bits : 0 - 2 (3 bit)
DASLEW : Data Slew Limit
bits : 8 - 9 (2 bit)
CLDRIVEL : Clock Drive Strength LOW
bits : 16 - 18 (3 bit)
CLDRIVEH : Clock Drive Strength HIGH
bits : 20 - 21 (2 bit)
CLSLEW : Clock Slew Limit
bits : 24 - 25 (2 bit)
FILTER : Input Spike Filter Control
bits : 28 - 29 (2 bit)
SMBus Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLOWS : Slave Clock stretch maximum cycles
bits : 0 - 7 (8 bit)
TLOWM : Master Clock stretch maximum cycles
bits : 8 - 15 (8 bit)
THMAX : Clock High maximum cycles
bits : 16 - 23 (8 bit)
EXP : SMBus Timeout Clock prescaler
bits : 28 - 31 (4 bit)
SMBus Timing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLOWS : Slave Clock stretch maximum cycles
bits : 0 - 7 (8 bit)
TLOWM : Master Clock stretch maximum cycles
bits : 8 - 15 (8 bit)
THMAX : Clock High maximum cycles
bits : 16 - 23 (8 bit)
EXP : SMBus Timeout Clock prescaler
bits : 28 - 31 (4 bit)
Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ : Transfer Direction
bits : 0 - 0 (1 bit)
SADR : Slave Address
bits : 1 - 10 (10 bit)
TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)
REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)
START : Send START condition
bits : 13 - 13 (1 bit)
STOP : Send STOP condition
bits : 14 - 14 (1 bit)
VALID : CMDR Valid
bits : 15 - 15 (1 bit)
NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)
PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)
ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)
HS : HS-mode
bits : 26 - 26 (1 bit)
HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)
Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READ : Transfer Direction
bits : 0 - 0 (1 bit)
SADR : Slave Address
bits : 1 - 10 (10 bit)
TENBIT : Ten Bit Addressing Mode
bits : 11 - 11 (1 bit)
REPSAME : Transfer is to same address as previous address
bits : 12 - 12 (1 bit)
START : Send START condition
bits : 13 - 13 (1 bit)
STOP : Send STOP condition
bits : 14 - 14 (1 bit)
VALID : CMDR Valid
bits : 15 - 15 (1 bit)
NBYTES : Number of data bytes in transfer
bits : 16 - 23 (8 bit)
PECEN : Packet Error Checking Enable
bits : 24 - 24 (1 bit)
ACKLAST : ACK Last Master RX Byte
bits : 25 - 25 (1 bit)
HS : HS-mode
bits : 26 - 26 (1 bit)
HSMCODE : HS-mode Master Code
bits : 28 - 30 (3 bit)
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