\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Device General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UADD : USB Address
bits : 0 - 6 (7 bit)
ADDEN : Address Enable
bits : 7 - 7 (1 bit)
DETACH : Detach
bits : 8 - 8 (1 bit)
RMWKUP : Remote Wake-Up
bits : 9 - 9 (1 bit)
SPDCONF : Speed configuration
bits : 10 - 11 (2 bit)
LS : Low Speed Mode Force
bits : 12 - 12 (1 bit)
TSTJ : Test mode J
bits : 13 - 13 (1 bit)
TSTK : Test mode K
bits : 14 - 14 (1 bit)
TSTPCKT : Test Packet mode
bits : 15 - 15 (1 bit)
OPMODE2 : Specific Operational mode
bits : 16 - 16 (1 bit)
GNAK : Global NAK
bits : 17 - 17 (1 bit)
Device Global Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPE : SUSP Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
MSOFE : MSOF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
SOFE : SOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
EORSTE : EORST Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
WAKEUPE : WAKEUP Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
EORSME : EORSM Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
UPRSME : UPRSM Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
EP0INTE : EP0INT Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
EP1INTE : EP1INT Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-only
EP2INTE : EP2INT Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-only
EP3INTE : EP3INT Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-only
EP4INTE : EP4INT Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-only
EP5INTE : EP5INT Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-only
EP6INTE : EP6INT Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-only
EP7INTE : EP7INT Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-only
Endpoint Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)
Enumeration: EPBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
Enumeration: EPSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
Enumeration: EPDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
Enumeration: EPTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)
Endpoint Status Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Device Global Interrupt Enable Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPEC : SUSP Interrupt Enable Clear
bits : 0 - 0 (1 bit)
access : write-only
MSOFEC : MSOF Interrupt Enable Clear
bits : 1 - 1 (1 bit)
access : write-only
SOFEC : SOF Interrupt Enable Clear
bits : 2 - 2 (1 bit)
access : write-only
EORSTEC : EORST Interrupt Enable Clear
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPEC : WAKEUP Interrupt Enable Clear
bits : 4 - 4 (1 bit)
access : write-only
EORSMEC : EORSM Interrupt Enable Clear
bits : 5 - 5 (1 bit)
access : write-only
UPRSMEC : UPRSM Interrupt Enable Clear
bits : 6 - 6 (1 bit)
access : write-only
EP0INTEC : EP0INT Interrupt Enable Clear
bits : 12 - 12 (1 bit)
access : write-only
EP1INTEC : EP1INT Interrupt Enable Clear
bits : 13 - 13 (1 bit)
access : write-only
EP2INTEC : EP2INT Interrupt Enable Clear
bits : 14 - 14 (1 bit)
access : write-only
EP3INTEC : EP3INT Interrupt Enable Clear
bits : 15 - 15 (1 bit)
access : write-only
EP4INTEC : EP4INT Interrupt Enable Clear
bits : 16 - 16 (1 bit)
access : write-only
EP5INTEC : EP5INT Interrupt Enable Clear
bits : 17 - 17 (1 bit)
access : write-only
EP6INTEC : EP6INT Interrupt Enable Clear
bits : 18 - 18 (1 bit)
access : write-only
EP7INTEC : EP7INT Interrupt Enable Clear
bits : 19 - 19 (1 bit)
access : write-only
Endpoint Status Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
Enumeration: CTRLDIRSelect
0x0 : OUT
None
0x1 : IN
None
End of enumeration elements list.
Endpoint Status Clear Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Endpoint Status Clear Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only
Device Global Interrupt Enable Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPES : SUSP Interrupt Enable Set
bits : 0 - 0 (1 bit)
access : write-only
MSOFES : MSOF Interrupt Enable Set
bits : 1 - 1 (1 bit)
access : write-only
SOFES : SOF Interrupt Enable Set
bits : 2 - 2 (1 bit)
access : write-only
EORSTES : EORST Interrupt Enable Set
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPES : WAKEUP Interrupt Enable Set
bits : 4 - 4 (1 bit)
access : write-only
EORSMES : EORSM Interrupt Enable Set
bits : 5 - 5 (1 bit)
access : write-only
UPRSMES : UPRSM Interrupt Enable Set
bits : 6 - 6 (1 bit)
access : write-only
EP0INTES : EP0INT Interrupt Enable Set
bits : 12 - 12 (1 bit)
access : write-only
EP1INTES : EP1INT Interrupt Enable Set
bits : 13 - 13 (1 bit)
access : write-only
EP2INTES : EP2INT Interrupt Enable Set
bits : 14 - 14 (1 bit)
access : write-only
EP3INTES : EP3INT Interrupt Enable Set
bits : 15 - 15 (1 bit)
access : write-only
EP4INTES : EP4INT Interrupt Enable Set
bits : 16 - 16 (1 bit)
access : write-only
EP5INTES : EP5INT Interrupt Enable Set
bits : 17 - 17 (1 bit)
access : write-only
EP6INTES : EP6INT Interrupt Enable Set
bits : 18 - 18 (1 bit)
access : write-only
EP7INTES : EP7INT Interrupt Enable Set
bits : 19 - 19 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Status Set Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only
Endpoint Enable/Reset Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEN0 : Endpoint0 Enable
bits : 0 - 0 (1 bit)
EPEN1 : Endpoint1 Enable
bits : 1 - 1 (1 bit)
EPEN2 : Endpoint2 Enable
bits : 2 - 2 (1 bit)
EPEN3 : Endpoint3 Enable
bits : 3 - 3 (1 bit)
EPEN4 : Endpoint4 Enable
bits : 4 - 4 (1 bit)
EPEN5 : Endpoint5 Enable
bits : 5 - 5 (1 bit)
EPEN6 : Endpoint6 Enable
bits : 6 - 6 (1 bit)
EPEN7 : Endpoint7 Enable
bits : 7 - 7 (1 bit)
Endpoint Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET token disable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only
BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only
Endpoint Control Set Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Device Frame Number Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
access : read-only
FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-only
FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
access : read-only
Endpoint Control Set Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Set Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only
STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only
NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only
NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only
BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only
BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only
Endpoint Control Clear Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : STALLEDE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLRQ Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
TXINE Clear
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only
STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only
NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only
STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only
BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only
BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only
Device Global Interupt Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSP : Suspend Interrupt
bits : 0 - 0 (1 bit)
access : read-only
MSOF : Micro Start of Frame Interrupt
bits : 1 - 1 (1 bit)
access : read-only
SOF : Start of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only
EORST : End of Reset Interrupt
bits : 3 - 3 (1 bit)
access : read-only
WAKEUP : Wake-Up Interrupt
bits : 4 - 4 (1 bit)
access : read-only
EORSM : End Of Resume Interrupt
bits : 5 - 5 (1 bit)
access : read-only
UPRSM : Upstream Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only
EP0INT : Endpoint 0 Interrupt
bits : 12 - 12 (1 bit)
access : read-only
EP1INT : Endpoint 1 Interrupt
bits : 13 - 13 (1 bit)
access : read-only
EP2INT : Endpoint 2 Interrupt
bits : 14 - 14 (1 bit)
access : read-only
EP3INT : Endpoint 3 Interrupt
bits : 15 - 15 (1 bit)
access : read-only
EP4INT : Endpoint 4 Interrupt
bits : 16 - 16 (1 bit)
access : read-only
EP5INT : Endpoint 5 Interrupt
bits : 17 - 17 (1 bit)
access : read-only
EP6INT : Endpoint 6 Interrupt
bits : 18 - 18 (1 bit)
access : read-only
EP7INT : Endpoint 7 Interrupt
bits : 19 - 19 (1 bit)
access : read-only
Host General Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFE : SOF Enable
bits : 8 - 8 (1 bit)
RESET : Send USB Reset
bits : 9 - 9 (1 bit)
RESUME : Send USB Resume
bits : 10 - 10 (1 bit)
SPDCONF : Speed Configuration
bits : 12 - 13 (2 bit)
TSTJ : Test J
bits : 16 - 16 (1 bit)
TSTK : Test K
bits : 17 - 17 (1 bit)
Host Global Interrupt Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNI : Device Connection Interrupt
bits : 0 - 0 (1 bit)
access : read-only
DDISCI : Device Disconnection Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RSTI : USB Reset Sent Interrupt
bits : 2 - 2 (1 bit)
access : read-only
RSMEDI : Downstream Resume Sent Interrupt
bits : 3 - 3 (1 bit)
access : read-only
RXRSMI : Upstream Resume Received Interrupt
bits : 4 - 4 (1 bit)
access : read-only
HSOFI : Host SOF Interrupt
bits : 5 - 5 (1 bit)
access : read-only
HWUPI : Host Wake-Up Interrupt
bits : 6 - 6 (1 bit)
access : read-only
P0INT : Pipe 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only
P1INT : Pipe 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only
P2INT : Pipe 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only
P3INT : Pipe 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only
P4INT : Pipe 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only
P5INT : Pipe 5 Interrupt
bits : 13 - 13 (1 bit)
access : read-only
P6INT : Pipe 6 Interrupt
bits : 14 - 14 (1 bit)
access : read-only
Host Global Interrrupt Clear Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIC : DCONNI Clear
bits : 0 - 0 (1 bit)
access : write-only
DDISCIC : DDISCI Clear
bits : 1 - 1 (1 bit)
access : write-only
RSTIC : RSTI Clear
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIC : RSMEDI Clear
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIC : RXRSMI Clear
bits : 4 - 4 (1 bit)
access : write-only
HSOFIC : HSOFI Clear
bits : 5 - 5 (1 bit)
access : write-only
HWUPIC : HWUPI Clear
bits : 6 - 6 (1 bit)
access : write-only
Host Global Interrupt Set Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIS : DCONNI Set
bits : 0 - 0 (1 bit)
access : write-only
DDISCIS : DDISCI Set
bits : 1 - 1 (1 bit)
access : write-only
RSTIS : RSTI Set
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIS : RSMEDI Set
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIS : RXRSMI Set
bits : 4 - 4 (1 bit)
access : write-only
HSOFIS : HSOFI Set
bits : 5 - 5 (1 bit)
access : write-only
HWUPIS : HWUPI Set
bits : 6 - 6 (1 bit)
access : write-only
Host Global Interrupt Enable Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIE : DCONNI Enable
bits : 0 - 0 (1 bit)
access : read-only
DDISCIE : DDISCI Enable
bits : 1 - 1 (1 bit)
access : read-only
RSTIE : RSTI Enable
bits : 2 - 2 (1 bit)
access : read-only
RSMEDIE : RSMEDI Enable
bits : 3 - 3 (1 bit)
access : read-only
RXRSMIE : RXRSMI Enable
bits : 4 - 4 (1 bit)
access : read-only
HSOFIE : HSOFI Enable
bits : 5 - 5 (1 bit)
access : read-only
HWUPIE : HWUPI Enable
bits : 6 - 6 (1 bit)
access : read-only
P0INTE : P0INT Enable
bits : 8 - 8 (1 bit)
access : read-only
P1INTE : P1INT Enable
bits : 9 - 9 (1 bit)
access : read-only
P2INTE : P2INT Enable
bits : 10 - 10 (1 bit)
access : read-only
P3INTE : P3INT Enable
bits : 11 - 11 (1 bit)
access : read-only
P4INTE : P4INT Enable
bits : 12 - 12 (1 bit)
access : read-only
P5INTE : P5INT Enable
bits : 13 - 13 (1 bit)
access : read-only
P6INTE : P6INT Enable
bits : 14 - 14 (1 bit)
access : read-only
P7INTE : P7INT Enable
bits : 15 - 15 (1 bit)
access : read-only
Host Global Interrupt Enable Clear Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIEC : DCONNIE Clear
bits : 0 - 0 (1 bit)
access : write-only
DDISCIEC : DDISCIE Clear
bits : 1 - 1 (1 bit)
access : write-only
RSTIEC : RSTIE Clear
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIEC : RSMEDIE Clear
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIEC : RXRSMIE Clear
bits : 4 - 4 (1 bit)
access : write-only
HSOFIEC : HSOFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
HWUPIEC : HWUPIE Clear
bits : 6 - 6 (1 bit)
access : write-only
P0INTEC : P0INTE Clear
bits : 8 - 8 (1 bit)
access : write-only
P1INTEC : P1INTE Clear
bits : 9 - 9 (1 bit)
access : write-only
P2INTEC : P2INTE Clear
bits : 10 - 10 (1 bit)
access : write-only
P3INTEC : P3INTE Clear
bits : 11 - 11 (1 bit)
access : write-only
P4INTEC : P4INTE Clear
bits : 12 - 12 (1 bit)
access : write-only
P5INTEC : P5INTE Clear
bits : 13 - 13 (1 bit)
access : write-only
P6INTEC : P6INTE Clear
bits : 14 - 14 (1 bit)
access : write-only
P7INTEC : P7INTE Clear
bits : 15 - 15 (1 bit)
access : write-only
Host Global Interrupt Enable Set Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIES : DCONNIE Set
bits : 0 - 0 (1 bit)
access : write-only
DDISCIES : DDISCIE Set
bits : 1 - 1 (1 bit)
access : write-only
RSTIES : RSTIE Set
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIES : RSMEDIE Set
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIES : RXRSMIE Set
bits : 4 - 4 (1 bit)
access : write-only
HSOFIES : HSOFIE Set
bits : 5 - 5 (1 bit)
access : write-only
HWUPIES : HWUPIE Set
bits : 6 - 6 (1 bit)
access : write-only
P0INTES : P0INTE Set
bits : 8 - 8 (1 bit)
access : write-only
P1INTES : P1INTE Set
bits : 9 - 9 (1 bit)
access : write-only
P2INTES : P2INTE Set
bits : 10 - 10 (1 bit)
access : write-only
P3INTES : P3INTE Set
bits : 11 - 11 (1 bit)
access : write-only
P4INTES : P4INTE Set
bits : 12 - 12 (1 bit)
access : write-only
P5INTES : P5INTE Set
bits : 13 - 13 (1 bit)
access : write-only
P6INTES : P6INTE Set
bits : 14 - 14 (1 bit)
access : write-only
P7INTES : P7INTE Set
bits : 15 - 15 (1 bit)
access : write-only
Pipe Reset Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEN0 : Pipe0 Enable
bits : 0 - 0 (1 bit)
PEN1 : Pipe1 Enable
bits : 1 - 1 (1 bit)
PEN2 : Pipe2 Enable
bits : 2 - 2 (1 bit)
PEN3 : Pipe3 Enable
bits : 3 - 3 (1 bit)
PEN4 : Pipe4 Enable
bits : 4 - 4 (1 bit)
PEN5 : Pipe5 Enable
bits : 5 - 5 (1 bit)
PEN6 : Pipe6 Enable
bits : 6 - 6 (1 bit)
PEN7 : Pipe7 Enable
bits : 7 - 7 (1 bit)
Host Frame Number Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
access : read-only
FNUM : Frame Number
bits : 3 - 13 (11 bit)
FLENHIGH : Frame Length
bits : 16 - 23 (8 bit)
access : read-only
Host Start of Frame Control Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLENC : Frame Length Control
bits : 0 - 13 (14 bit)
FLENCE : Frame Length Control Enable
bits : 16 - 16 (1 bit)
Pipe Configuration Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Configuration Register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBK : Pipe Banks
bits : 2 - 2 (1 bit)
Enumeration: PBKSelect
0x0 : SINGLE
None
0x1 : DOUBLE
None
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
Enumeration: PSIZESelect
0x0 : 8
None
0x1 : 16
None
0x2 : 32
None
0x3 : 64
None
0x4 : 128
None
0x5 : 256
None
0x6 : 512
None
0x7 : 1024
None
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
Enumeration: PTOKENSelect
0x0 : SETUP
None
0x1 : IN
None
0x2 : OUT
None
End of enumeration elements list.
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
Enumeration: PTYPESelect
0x0 : CONTROL
None
0x1 : ISOCHRONOUS
None
0x2 : BULK
None
0x3 : INTERRUPT
None
End of enumeration elements list.
PINGEN : Ping Enable
bits : 20 - 20 (1 bit)
BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)
Pipe Status Register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Register
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Pipe Status Clear Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Clear Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only
PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Status Set Register
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only
Pipe Control Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Register
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only
INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only
Pipe Control Set Register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Set Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only
PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only
RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only
PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only
INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe Control Clear Register
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only
PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only
ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only
RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only
NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only
PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only
INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only
INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only
Pipe In Request
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Pipe In Request
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
Device Global Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPC : SUSP Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
MSOFC : MSOF Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
SOFC : SOF Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
EORSTC : EORST Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPC : WAKEUP Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
EORSMC : EORSM Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
UPRSMC : UPRSM Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
General Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRZCLK : Freeze USB Clock
bits : 14 - 14 (1 bit)
USBE : USBC Enable
bits : 15 - 15 (1 bit)
UIMOD : USBC Mode
bits : 24 - 24 (1 bit)
General Status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VBUSRQ : VBus Request
bits : 9 - 9 (1 bit)
access : read-only
SPEED : Speed Status
bits : 12 - 13 (2 bit)
access : read-only
Enumeration: SPEEDSelect
0x0 : FULL
None
0x1 : HIGH
None
0x2 : LOW
None
End of enumeration elements list.
CLKUSABLE : USB Clock Usable
bits : 14 - 14 (1 bit)
access : read-only
SUSPEND : Suspend module state
bits : 16 - 16 (1 bit)
access : read-only
General Status Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RAMACERIC : RAMACERI Clear
bits : 8 - 8 (1 bit)
access : write-only
VBUSRQC : VBUSRQ Clear
bits : 9 - 9 (1 bit)
access : write-only
General Status Set Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RAMACERIS : RAMACERI Set
bits : 8 - 8 (1 bit)
access : write-only
VBUSRQS : VBUSRQ Set
bits : 9 - 9 (1 bit)
access : write-only
IP Version Register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only
VARIANT : Variant Number
bits : 16 - 18 (3 bit)
access : read-only
IP Features Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPTNBRMAX : Maximum Number of Pipes/Endpints
bits : 0 - 3 (4 bit)
access : read-only
UTMIMODE : UTMI Mode
bits : 8 - 8 (1 bit)
access : read-only
IP PB address size Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UADDRSIZE : IP PB Address Size
bits : 0 - 31 (32 bit)
IP Name Part One: HUSB
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNAME1 : IP Name Part One
bits : 0 - 31 (32 bit)
IP Name Part Two: HOST
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNAME2 : IP Name Part Two
bits : 0 - 31 (32 bit)
USB internal finite state machine
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRDSTATE : DualRoleDevice state
bits : 0 - 3 (4 bit)
access : read-only
Enumeration: DRDSTATESelect
0x0 : A_IDLE
None
0x1 : A_WAIT_VRISE
None
0x2 : A_WAIT_BCON
None
0x3 : A_HOST
None
0x4 : A_SUSPEND
None
0x5 : A_PERIPHERAL
None
0x6 : A_WAIT_VFALL
None
0x7 : A_VBUS_ERR
None
0x8 : A_WAIT_DISCHARGE
None
0x9 : B_IDLE
None
0xa : B_PERIPHERAL
None
0xb : B_WAIT_BEGIN_HNP
None
0xc : B_WAIT_DISCHARGE
None
0xd : B_WAIT_ACON
None
0xe : B_HOST
None
0xf : B_SRP_INIT
None
End of enumeration elements list.
Endpoint descriptor table
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDESCA : USB Descriptor Address
bits : 0 - 31 (32 bit)
Device Global Interrupt Set Regsiter
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPS : SUSP Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
MSOFS : MSOF Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
SOFS : SOF Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
EORSTS : EORST Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPS : WAKEUP Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
EORSMS : EORSM Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
UPRSMS : UPRSM Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
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