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USBC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UDCON

UDINTE

UECFG0

UECFG1

UECFG2

UECFG3

UECFG4

UECFG5

UECFG6

UECFG7

UESTA0

UESTA1

UESTA2

UESTA3

UDINTECLR

UESTA4

UESTA5

UESTA6

UESTA7

UESTA0CLR

UESTA1CLR

UESTA2CLR

UESTA3CLR

UESTA4CLR

UESTA5CLR

UESTA6CLR

UESTA7CLR

UDINTESET

UESTA0SET

UESTA1SET

UESTA2SET

UESTA3SET

UESTA4SET

UESTA5SET

UESTA6SET

UESTA7SET

UERST

UECON0

UECON1

UECON2

UECON3

UECON4

UECON5

UECON6

UECON7

UECON0SET

UECON1SET

UECON2SET

UECON3SET

UDFNUM

UECON4SET

UECON5SET

UECON6SET

UECON7SET

UECON0CLR

UECON1CLR

UECON2CLR

UECON3CLR

UECON4CLR

UECON5CLR

UECON6CLR

UECON7CLR

UDINT

UHCON

UHINT

UHINTCLR

UHINTSET

UHINTE

UHINTECLR

UHINTESET

UPRST

UHFNUM

UHSOFC

UPCFG0

UPCFG1

UPCFG2

UPCFG3

UPCFG4

UPCFG5

UPCFG6

UPCFG7

UPSTA0

UPSTA1

UPSTA2

UPSTA3

UPSTA4

UPSTA5

UPSTA6

UPSTA7

UPSTA0CLR

UPSTA1CLR

UPSTA2CLR

UPSTA3CLR

UPSTA4CLR

UPSTA5CLR

UPSTA6CLR

UPSTA7CLR

UPSTA0SET

UPSTA1SET

UPSTA2SET

UPSTA3SET

UPSTA4SET

UPSTA5SET

UPSTA6SET

UPSTA7SET

UPCON0

UPCON1

UPCON2

UPCON3

UPCON4

UPCON5

UPCON6

UPCON7

UPCON0SET

UPCON1SET

UPCON2SET

UPCON3SET

UPCON4SET

UPCON5SET

UPCON6SET

UPCON7SET

UPCON0CLR

UPCON1CLR

UPCON2CLR

UPCON3CLR

UPCON4CLR

UPCON5CLR

UPCON6CLR

UPCON7CLR

UPINRQ0

UPINRQ1

UPINRQ2

UPINRQ3

UPINRQ4

UPINRQ5

UPINRQ6

UPINRQ7

UDINTCLR

USBCON

USBSTA

USBSTACLR

USBSTASET

UVERS

UFEATURES

UADDRSIZE

UNAME1

UNAME2

USBFSM

UDESC

UDINTSET


UDCON

Device General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDCON UDCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UADD ADDEN DETACH RMWKUP SPDCONF LS TSTJ TSTK TSTPCKT OPMODE2 GNAK

UADD : USB Address
bits : 0 - 6 (7 bit)

ADDEN : Address Enable
bits : 7 - 7 (1 bit)

DETACH : Detach
bits : 8 - 8 (1 bit)

RMWKUP : Remote Wake-Up
bits : 9 - 9 (1 bit)

SPDCONF : Speed configuration
bits : 10 - 11 (2 bit)

LS : Low Speed Mode Force
bits : 12 - 12 (1 bit)

TSTJ : Test mode J
bits : 13 - 13 (1 bit)

TSTK : Test mode K
bits : 14 - 14 (1 bit)

TSTPCKT : Test Packet mode
bits : 15 - 15 (1 bit)

OPMODE2 : Specific Operational mode
bits : 16 - 16 (1 bit)

GNAK : Global NAK
bits : 17 - 17 (1 bit)


UDINTE

Device Global Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UDINTE UDINTE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPE MSOFE SOFE EORSTE WAKEUPE EORSME UPRSME EP0INTE EP1INTE EP2INTE EP3INTE EP4INTE EP5INTE EP6INTE EP7INTE

SUSPE : SUSP Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

MSOFE : MSOF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

SOFE : SOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

EORSTE : EORST Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

WAKEUPE : WAKEUP Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

EORSME : EORSM Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

UPRSME : UPRSM Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

EP0INTE : EP0INT Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

EP1INTE : EP1INT Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-only

EP2INTE : EP2INT Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-only

EP3INTE : EP3INT Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-only

EP4INTE : EP4INT Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-only

EP5INTE : EP5INT Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-only

EP6INTE : EP6INT Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-only

EP7INTE : EP7INT Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-only


UECFG0

Endpoint Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG0 UECFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG1

Endpoint Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG1 UECFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG2

Endpoint Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG2 UECFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG3

Endpoint Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG3 UECFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG4

Endpoint Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG4 UECFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG5

Endpoint Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG5 UECFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG6

Endpoint Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG6 UECFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UECFG7

Endpoint Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UECFG7 UECFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPBK EPSIZE EPDIR EPTYPE REPNB

EPBK : Endpoint Bank
bits : 2 - 2 (1 bit)

Enumeration: EPBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)

Enumeration: EPSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)

Enumeration: EPDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)

Enumeration: EPTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

REPNB : Redirected Endpoint Number
bits : 16 - 19 (4 bit)


UESTA0

Endpoint Status Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA0 UESTA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA1

Endpoint Status Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA1 UESTA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA2

Endpoint Status Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA2 UESTA2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA3

Endpoint Status Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA3 UESTA3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UDINTECLR

Device Global Interrupt Enable Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDINTECLR UDINTECLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEC MSOFEC SOFEC EORSTEC WAKEUPEC EORSMEC UPRSMEC EP0INTEC EP1INTEC EP2INTEC EP3INTEC EP4INTEC EP5INTEC EP6INTEC EP7INTEC

SUSPEC : SUSP Interrupt Enable Clear
bits : 0 - 0 (1 bit)
access : write-only

MSOFEC : MSOF Interrupt Enable Clear
bits : 1 - 1 (1 bit)
access : write-only

SOFEC : SOF Interrupt Enable Clear
bits : 2 - 2 (1 bit)
access : write-only

EORSTEC : EORST Interrupt Enable Clear
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPEC : WAKEUP Interrupt Enable Clear
bits : 4 - 4 (1 bit)
access : write-only

EORSMEC : EORSM Interrupt Enable Clear
bits : 5 - 5 (1 bit)
access : write-only

UPRSMEC : UPRSM Interrupt Enable Clear
bits : 6 - 6 (1 bit)
access : write-only

EP0INTEC : EP0INT Interrupt Enable Clear
bits : 12 - 12 (1 bit)
access : write-only

EP1INTEC : EP1INT Interrupt Enable Clear
bits : 13 - 13 (1 bit)
access : write-only

EP2INTEC : EP2INT Interrupt Enable Clear
bits : 14 - 14 (1 bit)
access : write-only

EP3INTEC : EP3INT Interrupt Enable Clear
bits : 15 - 15 (1 bit)
access : write-only

EP4INTEC : EP4INT Interrupt Enable Clear
bits : 16 - 16 (1 bit)
access : write-only

EP5INTEC : EP5INT Interrupt Enable Clear
bits : 17 - 17 (1 bit)
access : write-only

EP6INTEC : EP6INT Interrupt Enable Clear
bits : 18 - 18 (1 bit)
access : write-only

EP7INTEC : EP7INT Interrupt Enable Clear
bits : 19 - 19 (1 bit)
access : write-only


UESTA4

Endpoint Status Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA4 UESTA4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA5

Endpoint Status Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA5 UESTA5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA6

Endpoint Status Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA6 UESTA6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA7

Endpoint Status Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UESTA7 UESTA7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI STALLEDI DTSEQ RAMACERI NBUSYBK CURRBK CTRLDIR

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBK : Number Of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: CTRLDIRSelect

0x0 : OUT

None

0x1 : IN

None

End of enumeration elements list.


UESTA0CLR

Endpoint Status Clear Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA0CLR UESTA0CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA1CLR

Endpoint Status Clear Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA1CLR UESTA1CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA2CLR

Endpoint Status Clear Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA2CLR UESTA2CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA3CLR

Endpoint Status Clear Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA3CLR UESTA3CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA4CLR

Endpoint Status Clear Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA4CLR UESTA4CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA5CLR

Endpoint Status Clear Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA5CLR UESTA5CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA6CLR

Endpoint Status Clear Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA6CLR UESTA6CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UESTA7CLR

Endpoint Status Clear Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA7CLR UESTA7CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC STALLEDIC RAMACERIC

TXINIC : TXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : RXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : RXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKOUTI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKINI Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIC : STALLEDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 11 - 11 (1 bit)
access : write-only


UDINTESET

Device Global Interrupt Enable Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDINTESET UDINTESET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPES MSOFES SOFES EORSTES WAKEUPES EORSMES UPRSMES EP0INTES EP1INTES EP2INTES EP3INTES EP4INTES EP5INTES EP6INTES EP7INTES

SUSPES : SUSP Interrupt Enable Set
bits : 0 - 0 (1 bit)
access : write-only

MSOFES : MSOF Interrupt Enable Set
bits : 1 - 1 (1 bit)
access : write-only

SOFES : SOF Interrupt Enable Set
bits : 2 - 2 (1 bit)
access : write-only

EORSTES : EORST Interrupt Enable Set
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPES : WAKEUP Interrupt Enable Set
bits : 4 - 4 (1 bit)
access : write-only

EORSMES : EORSM Interrupt Enable Set
bits : 5 - 5 (1 bit)
access : write-only

UPRSMES : UPRSM Interrupt Enable Set
bits : 6 - 6 (1 bit)
access : write-only

EP0INTES : EP0INT Interrupt Enable Set
bits : 12 - 12 (1 bit)
access : write-only

EP1INTES : EP1INT Interrupt Enable Set
bits : 13 - 13 (1 bit)
access : write-only

EP2INTES : EP2INT Interrupt Enable Set
bits : 14 - 14 (1 bit)
access : write-only

EP3INTES : EP3INT Interrupt Enable Set
bits : 15 - 15 (1 bit)
access : write-only

EP4INTES : EP4INT Interrupt Enable Set
bits : 16 - 16 (1 bit)
access : write-only

EP5INTES : EP5INT Interrupt Enable Set
bits : 17 - 17 (1 bit)
access : write-only

EP6INTES : EP6INT Interrupt Enable Set
bits : 18 - 18 (1 bit)
access : write-only

EP7INTES : EP7INT Interrupt Enable Set
bits : 19 - 19 (1 bit)
access : write-only


UESTA0SET

Endpoint Status Set Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA0SET UESTA0SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA1SET

Endpoint Status Set Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA1SET UESTA1SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA2SET

Endpoint Status Set Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA2SET UESTA2SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA3SET

Endpoint Status Set Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA3SET UESTA3SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA4SET

Endpoint Status Set Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA4SET UESTA4SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA5SET

Endpoint Status Set Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA5SET UESTA5SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA6SET

Endpoint Status Set Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA6SET UESTA6SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UESTA7SET

Endpoint Status Set Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UESTA7SET UESTA7SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS STALLEDIS RAMACERIS NBUSYBKS

TXINIS : TXINI Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : RXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : RXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKOUTI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKINI Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDIS : STALLEDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKS : NBUSYBK Set
bits : 12 - 12 (1 bit)
access : write-only


UERST

Endpoint Enable/Reset Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UERST UERST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPEN0 EPEN1 EPEN2 EPEN3 EPEN4 EPEN5 EPEN6 EPEN7

EPEN0 : Endpoint0 Enable
bits : 0 - 0 (1 bit)

EPEN1 : Endpoint1 Enable
bits : 1 - 1 (1 bit)

EPEN2 : Endpoint2 Enable
bits : 2 - 2 (1 bit)

EPEN3 : Endpoint3 Enable
bits : 3 - 3 (1 bit)

EPEN4 : Endpoint4 Enable
bits : 4 - 4 (1 bit)

EPEN5 : Endpoint5 Enable
bits : 5 - 5 (1 bit)

EPEN6 : Endpoint6 Enable
bits : 6 - 6 (1 bit)

EPEN7 : Endpoint7 Enable
bits : 7 - 7 (1 bit)


UECON0

Endpoint Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON0 UECON0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET token disable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON1

Endpoint Control Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON1 UECON1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON2

Endpoint Control Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON2 UECON2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON3

Endpoint Control Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON3 UECON3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON4

Endpoint Control Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON4 UECON4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON5

Endpoint Control Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON5 UECON5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON6

Endpoint Control Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON6 UECON6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON7

Endpoint Control Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UECON7 UECON7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE STALLEDE NREPLY RAMACERE NBUSYBKE KILLBK FIFOCON NYETDIS RSTDT STALLRQ BUSY0 BUSY1

TXINE : TXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : RXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : RXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKOUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKIN Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

STALLEDE : STALLED Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

NREPLY : No Reply
bits : 8 - 8 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

NYETDIS : NYET Token Enable
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only

BUSY0 : Busy Bank1 Enable
bits : 24 - 24 (1 bit)
access : read-only

BUSY1 : Busy Bank0 Enable
bits : 25 - 25 (1 bit)
access : read-only


UECON0SET

Endpoint Control Set Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON0SET UECON0SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON1SET

Endpoint Control Set Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON1SET UECON1SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON2SET

Endpoint Control Set Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON2SET UECON2SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON3SET

Endpoint Control Set Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON3SET UECON3SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UDFNUM

Device Frame Number Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UDFNUM UDFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFNUM FNUM FNCERR

MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
access : read-only

FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-only

FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
access : read-only


UECON4SET

Endpoint Control Set Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON4SET UECON4SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON5SET

Endpoint Control Set Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON5SET UECON5SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON6SET

Endpoint Control Set Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON6SET UECON6SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON7SET

Endpoint Control Set Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON7SET UECON7SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES STALLEDES NREPLYS RAMACERES NBUSYBKES KILLBKS NYETDISS RSTDTS STALLRQS BUSY0S BUSY1S

TXINES : TXINE Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : RXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : RXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKOUTE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKINE Set
bits : 4 - 4 (1 bit)
access : write-only

STALLEDES : STALLEDE Set
bits : 6 - 6 (1 bit)
access : write-only

NREPLYS : NREPLY Set
bits : 8 - 8 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : KILLBK Set
bits : 13 - 13 (1 bit)
access : write-only

NYETDISS : NYETDIS Set
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : RSTDT Set
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALLRQ Set
bits : 19 - 19 (1 bit)
access : write-only

BUSY0S : BUSY0 Set
bits : 24 - 24 (1 bit)
access : write-only

BUSY1S : BUSY1 Set
bits : 25 - 25 (1 bit)
access : write-only


UECON0CLR

Endpoint Control Clear Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON0CLR UECON0CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : STALLEDE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLRQ Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON1CLR

TXINE Clear
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON1CLR UECON1CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON2CLR

TXINE Clear
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON2CLR UECON2CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON3CLR

TXINE Clear
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON3CLR UECON3CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON4CLR

TXINE Clear
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON4CLR UECON4CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON5CLR

TXINE Clear
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON5CLR UECON5CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON6CLR

TXINE Clear
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON6CLR UECON6CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UECON7CLR

TXINE Clear
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UECON7CLR UECON7CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC STALLEDEC NREPLYC RAMACEREC NBUSYBKEC FIFOCONC NYETDISC STALLRQC BUSY0C BUSY1C

TXINEC : TXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : RXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : RXOUTE Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKOUTE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKINE Clear
bits : 4 - 4 (1 bit)
access : write-only

STALLEDEC : RXSTPE Clear
bits : 6 - 6 (1 bit)
access : write-only

NREPLYC : NREPLY Clear
bits : 8 - 8 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 11 - 11 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

NYETDISC : NYETDIS Clear
bits : 17 - 17 (1 bit)
access : write-only

STALLRQC : STALLEDE Clear
bits : 19 - 19 (1 bit)
access : write-only

BUSY0C : BUSY0 Clear
bits : 24 - 24 (1 bit)
access : write-only

BUSY1C : BUSY1 Clear
bits : 25 - 25 (1 bit)
access : write-only


UDINT

Device Global Interupt Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UDINT UDINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSP MSOF SOF EORST WAKEUP EORSM UPRSM EP0INT EP1INT EP2INT EP3INT EP4INT EP5INT EP6INT EP7INT

SUSP : Suspend Interrupt
bits : 0 - 0 (1 bit)
access : read-only

MSOF : Micro Start of Frame Interrupt
bits : 1 - 1 (1 bit)
access : read-only

SOF : Start of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only

EORST : End of Reset Interrupt
bits : 3 - 3 (1 bit)
access : read-only

WAKEUP : Wake-Up Interrupt
bits : 4 - 4 (1 bit)
access : read-only

EORSM : End Of Resume Interrupt
bits : 5 - 5 (1 bit)
access : read-only

UPRSM : Upstream Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only

EP0INT : Endpoint 0 Interrupt
bits : 12 - 12 (1 bit)
access : read-only

EP1INT : Endpoint 1 Interrupt
bits : 13 - 13 (1 bit)
access : read-only

EP2INT : Endpoint 2 Interrupt
bits : 14 - 14 (1 bit)
access : read-only

EP3INT : Endpoint 3 Interrupt
bits : 15 - 15 (1 bit)
access : read-only

EP4INT : Endpoint 4 Interrupt
bits : 16 - 16 (1 bit)
access : read-only

EP5INT : Endpoint 5 Interrupt
bits : 17 - 17 (1 bit)
access : read-only

EP6INT : Endpoint 6 Interrupt
bits : 18 - 18 (1 bit)
access : read-only

EP7INT : Endpoint 7 Interrupt
bits : 19 - 19 (1 bit)
access : read-only


UHCON

Host General Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UHCON UHCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOFE RESET RESUME SPDCONF TSTJ TSTK

SOFE : SOF Enable
bits : 8 - 8 (1 bit)

RESET : Send USB Reset
bits : 9 - 9 (1 bit)

RESUME : Send USB Resume
bits : 10 - 10 (1 bit)

SPDCONF : Speed Configuration
bits : 12 - 13 (2 bit)

TSTJ : Test J
bits : 16 - 16 (1 bit)

TSTK : Test K
bits : 17 - 17 (1 bit)


UHINT

Host Global Interrupt Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UHINT UHINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNI DDISCI RSTI RSMEDI RXRSMI HSOFI HWUPI P0INT P1INT P2INT P3INT P4INT P5INT P6INT

DCONNI : Device Connection Interrupt
bits : 0 - 0 (1 bit)
access : read-only

DDISCI : Device Disconnection Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RSTI : USB Reset Sent Interrupt
bits : 2 - 2 (1 bit)
access : read-only

RSMEDI : Downstream Resume Sent Interrupt
bits : 3 - 3 (1 bit)
access : read-only

RXRSMI : Upstream Resume Received Interrupt
bits : 4 - 4 (1 bit)
access : read-only

HSOFI : Host SOF Interrupt
bits : 5 - 5 (1 bit)
access : read-only

HWUPI : Host Wake-Up Interrupt
bits : 6 - 6 (1 bit)
access : read-only

P0INT : Pipe 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only

P1INT : Pipe 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only

P2INT : Pipe 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only

P3INT : Pipe 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only

P4INT : Pipe 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only

P5INT : Pipe 5 Interrupt
bits : 13 - 13 (1 bit)
access : read-only

P6INT : Pipe 6 Interrupt
bits : 14 - 14 (1 bit)
access : read-only


UHINTCLR

Host Global Interrrupt Clear Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UHINTCLR UHINTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIC DDISCIC RSTIC RSMEDIC RXRSMIC HSOFIC HWUPIC

DCONNIC : DCONNI Clear
bits : 0 - 0 (1 bit)
access : write-only

DDISCIC : DDISCI Clear
bits : 1 - 1 (1 bit)
access : write-only

RSTIC : RSTI Clear
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIC : RSMEDI Clear
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIC : RXRSMI Clear
bits : 4 - 4 (1 bit)
access : write-only

HSOFIC : HSOFI Clear
bits : 5 - 5 (1 bit)
access : write-only

HWUPIC : HWUPI Clear
bits : 6 - 6 (1 bit)
access : write-only


UHINTSET

Host Global Interrupt Set Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UHINTSET UHINTSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIS DDISCIS RSTIS RSMEDIS RXRSMIS HSOFIS HWUPIS

DCONNIS : DCONNI Set
bits : 0 - 0 (1 bit)
access : write-only

DDISCIS : DDISCI Set
bits : 1 - 1 (1 bit)
access : write-only

RSTIS : RSTI Set
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIS : RSMEDI Set
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIS : RXRSMI Set
bits : 4 - 4 (1 bit)
access : write-only

HSOFIS : HSOFI Set
bits : 5 - 5 (1 bit)
access : write-only

HWUPIS : HWUPI Set
bits : 6 - 6 (1 bit)
access : write-only


UHINTE

Host Global Interrupt Enable Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UHINTE UHINTE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIE DDISCIE RSTIE RSMEDIE RXRSMIE HSOFIE HWUPIE P0INTE P1INTE P2INTE P3INTE P4INTE P5INTE P6INTE P7INTE

DCONNIE : DCONNI Enable
bits : 0 - 0 (1 bit)
access : read-only

DDISCIE : DDISCI Enable
bits : 1 - 1 (1 bit)
access : read-only

RSTIE : RSTI Enable
bits : 2 - 2 (1 bit)
access : read-only

RSMEDIE : RSMEDI Enable
bits : 3 - 3 (1 bit)
access : read-only

RXRSMIE : RXRSMI Enable
bits : 4 - 4 (1 bit)
access : read-only

HSOFIE : HSOFI Enable
bits : 5 - 5 (1 bit)
access : read-only

HWUPIE : HWUPI Enable
bits : 6 - 6 (1 bit)
access : read-only

P0INTE : P0INT Enable
bits : 8 - 8 (1 bit)
access : read-only

P1INTE : P1INT Enable
bits : 9 - 9 (1 bit)
access : read-only

P2INTE : P2INT Enable
bits : 10 - 10 (1 bit)
access : read-only

P3INTE : P3INT Enable
bits : 11 - 11 (1 bit)
access : read-only

P4INTE : P4INT Enable
bits : 12 - 12 (1 bit)
access : read-only

P5INTE : P5INT Enable
bits : 13 - 13 (1 bit)
access : read-only

P6INTE : P6INT Enable
bits : 14 - 14 (1 bit)
access : read-only

P7INTE : P7INT Enable
bits : 15 - 15 (1 bit)
access : read-only


UHINTECLR

Host Global Interrupt Enable Clear Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UHINTECLR UHINTECLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIEC DDISCIEC RSTIEC RSMEDIEC RXRSMIEC HSOFIEC HWUPIEC P0INTEC P1INTEC P2INTEC P3INTEC P4INTEC P5INTEC P6INTEC P7INTEC

DCONNIEC : DCONNIE Clear
bits : 0 - 0 (1 bit)
access : write-only

DDISCIEC : DDISCIE Clear
bits : 1 - 1 (1 bit)
access : write-only

RSTIEC : RSTIE Clear
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIEC : RSMEDIE Clear
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIEC : RXRSMIE Clear
bits : 4 - 4 (1 bit)
access : write-only

HSOFIEC : HSOFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

HWUPIEC : HWUPIE Clear
bits : 6 - 6 (1 bit)
access : write-only

P0INTEC : P0INTE Clear
bits : 8 - 8 (1 bit)
access : write-only

P1INTEC : P1INTE Clear
bits : 9 - 9 (1 bit)
access : write-only

P2INTEC : P2INTE Clear
bits : 10 - 10 (1 bit)
access : write-only

P3INTEC : P3INTE Clear
bits : 11 - 11 (1 bit)
access : write-only

P4INTEC : P4INTE Clear
bits : 12 - 12 (1 bit)
access : write-only

P5INTEC : P5INTE Clear
bits : 13 - 13 (1 bit)
access : write-only

P6INTEC : P6INTE Clear
bits : 14 - 14 (1 bit)
access : write-only

P7INTEC : P7INTE Clear
bits : 15 - 15 (1 bit)
access : write-only


UHINTESET

Host Global Interrupt Enable Set Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UHINTESET UHINTESET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIES DDISCIES RSTIES RSMEDIES RXRSMIES HSOFIES HWUPIES P0INTES P1INTES P2INTES P3INTES P4INTES P5INTES P6INTES P7INTES

DCONNIES : DCONNIE Set
bits : 0 - 0 (1 bit)
access : write-only

DDISCIES : DDISCIE Set
bits : 1 - 1 (1 bit)
access : write-only

RSTIES : RSTIE Set
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIES : RSMEDIE Set
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIES : RXRSMIE Set
bits : 4 - 4 (1 bit)
access : write-only

HSOFIES : HSOFIE Set
bits : 5 - 5 (1 bit)
access : write-only

HWUPIES : HWUPIE Set
bits : 6 - 6 (1 bit)
access : write-only

P0INTES : P0INTE Set
bits : 8 - 8 (1 bit)
access : write-only

P1INTES : P1INTE Set
bits : 9 - 9 (1 bit)
access : write-only

P2INTES : P2INTE Set
bits : 10 - 10 (1 bit)
access : write-only

P3INTES : P3INTE Set
bits : 11 - 11 (1 bit)
access : write-only

P4INTES : P4INTE Set
bits : 12 - 12 (1 bit)
access : write-only

P5INTES : P5INTE Set
bits : 13 - 13 (1 bit)
access : write-only

P6INTES : P6INTE Set
bits : 14 - 14 (1 bit)
access : write-only

P7INTES : P7INTE Set
bits : 15 - 15 (1 bit)
access : write-only


UPRST

Pipe Reset Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPRST UPRST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEN0 PEN1 PEN2 PEN3 PEN4 PEN5 PEN6 PEN7

PEN0 : Pipe0 Enable
bits : 0 - 0 (1 bit)

PEN1 : Pipe1 Enable
bits : 1 - 1 (1 bit)

PEN2 : Pipe2 Enable
bits : 2 - 2 (1 bit)

PEN3 : Pipe3 Enable
bits : 3 - 3 (1 bit)

PEN4 : Pipe4 Enable
bits : 4 - 4 (1 bit)

PEN5 : Pipe5 Enable
bits : 5 - 5 (1 bit)

PEN6 : Pipe6 Enable
bits : 6 - 6 (1 bit)

PEN7 : Pipe7 Enable
bits : 7 - 7 (1 bit)


UHFNUM

Host Frame Number Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UHFNUM UHFNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFNUM FNUM FLENHIGH

MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
access : read-only

FNUM : Frame Number
bits : 3 - 13 (11 bit)

FLENHIGH : Frame Length
bits : 16 - 23 (8 bit)
access : read-only


UHSOFC

Host Start of Frame Control Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UHSOFC UHSOFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLENC FLENCE

FLENC : Frame Length Control
bits : 0 - 13 (14 bit)

FLENCE : Frame Length Control Enable
bits : 16 - 16 (1 bit)


UPCFG0

Pipe Configuration Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG0 UPCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG1

Pipe Configuration Register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG1 UPCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG2

Pipe Configuration Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG2 UPCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG3

Pipe Configuration Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG3 UPCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG4

Pipe Configuration Register
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG4 UPCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG5

Pipe Configuration Register
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG5 UPCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG6

Pipe Configuration Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG6 UPCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPCFG7

Pipe Configuration Register
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPCFG7 UPCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBK PSIZE PTOKEN PTYPE PINGEN BINTERVAL

PBK : Pipe Banks
bits : 2 - 2 (1 bit)

Enumeration: PBKSelect

0x0 : SINGLE

None

0x1 : DOUBLE

None

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)

Enumeration: PSIZESelect

0x0 : 8

None

0x1 : 16

None

0x2 : 32

None

0x3 : 64

None

0x4 : 128

None

0x5 : 256

None

0x6 : 512

None

0x7 : 1024

None

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)

Enumeration: PTOKENSelect

0x0 : SETUP

None

0x1 : IN

None

0x2 : OUT

None

End of enumeration elements list.

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)

Enumeration: PTYPESelect

0x0 : CONTROL

None

0x1 : ISOCHRONOUS

None

0x2 : BULK

None

0x3 : INTERRUPT

None

End of enumeration elements list.

PINGEN : Ping Enable
bits : 20 - 20 (1 bit)

BINTERVAL : binterval parameter
bits : 24 - 31 (8 bit)


UPSTA0

Pipe Status Register
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA0 UPSTA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA1

Pipe Status Register
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA1 UPSTA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA2

Pipe Status Register
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA2 UPSTA2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA3

Pipe Status Register
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA3 UPSTA3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA4

Pipe Status Register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA4 UPSTA4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA5

Pipe Status Register
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA5 UPSTA5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA6

Pipe Status Register
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA6 UPSTA6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA7

Pipe Status Register
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA7 UPSTA7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI ERRORFI RXSTALLDI DTSEQ RAMACERI NBUSYBK CURRBK

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ERRORFI : Errorflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

RAMACERI : Ram Access Error Interrupt
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBK : Number of Busy Bank
bits : 12 - 13 (2 bit)
access : read-only

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only


UPSTA0CLR

Pipe Status Clear Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA0CLR UPSTA0CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA1CLR

Pipe Status Clear Register
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA1CLR UPSTA1CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA2CLR

Pipe Status Clear Register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA2CLR UPSTA2CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA3CLR

Pipe Status Clear Register
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA3CLR UPSTA3CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA4CLR

Pipe Status Clear Register
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA4CLR UPSTA4CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA5CLR

Pipe Status Clear Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA5CLR UPSTA5CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA6CLR

Pipe Status Clear Register
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA6CLR UPSTA6CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA7CLR

Pipe Status Clear Register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA7CLR UPSTA7CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC PERRIC NAKEDIC ERRORFIC RXSTALLDIC RAMACERIC

RXINIC : RXINI Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : TXOUTI Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : TXSTPI Clear
bits : 2 - 2 (1 bit)
access : write-only

PERRIC : PERRI Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIC : NAKEDI Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIC : ERRORFI Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : RXSTALLDI Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIC : RAMACERI Clear
bits : 10 - 10 (1 bit)
access : write-only


UPSTA0SET

Pipe Status Set Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA0SET UPSTA0SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA1SET

Pipe Status Set Register
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA1SET UPSTA1SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA2SET

Pipe Status Set Register
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA2SET UPSTA2SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA3SET

Pipe Status Set Register
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA3SET UPSTA3SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA4SET

Pipe Status Set Register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA4SET UPSTA4SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA5SET

Pipe Status Set Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA5SET UPSTA5SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA6SET

Pipe Status Set Register
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA6SET UPSTA6SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPSTA7SET

Pipe Status Set Register
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPSTA7SET UPSTA7SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS ERRORFIS RXSTALLDIS RAMACERIS

RXINIS : RXINI Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : TXOUTI Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : TXSTPI Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : PERRI Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKEDI Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIS : ERRORFI Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : RXSTALLDI Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERIS : RAMACERI Set
bits : 10 - 10 (1 bit)
access : write-only


UPCON0

Pipe Control Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON0 UPCON0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON1

Pipe Control Register
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON1 UPCON1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON2

Pipe Control Register
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON2 UPCON2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON3

Pipe Control Register
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON3 UPCON3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON4

Pipe Control Register
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON4 UPCON4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON5

Pipe Control Register
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON5 UPCON5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON6

Pipe Control Register
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON6 UPCON6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON7

Pipe Control Register
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UPCON7 UPCON7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE ERRORFIE RXSTALLDE RAMACERE NBUSYBKE FIFOCON PFREEZE INITDTGL INITBK

RXINE : RXIN Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : TXOUT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : TXSTP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : PERR Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKED Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

ERRORFIE : ERRORFI Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : RXTALLD Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

RAMACERE : RAMACER Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

NBUSYBKE : NBUSYBKInterrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

INITDTGL : Data Toggle Initialization
bits : 18 - 18 (1 bit)
access : read-only

INITBK : Bank Initialization
bits : 19 - 19 (1 bit)
access : read-only


UPCON0SET

Pipe Control Set Register
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON0SET UPCON0SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON1SET

Pipe Control Set Register
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON1SET UPCON1SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON2SET

Pipe Control Set Register
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON2SET UPCON2SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON3SET

Pipe Control Set Register
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON3SET UPCON3SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON4SET

Pipe Control Set Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON4SET UPCON4SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON5SET

Pipe Control Set Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON5SET UPCON5SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON6SET

Pipe Control Set Register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON6SET UPCON6SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON7SET

Pipe Control Set Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON7SET UPCON7SET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES ERRORFIES RXSTALLDES RAMACERES NBUSYBKES FIFOCONS PFREEZES INITDTGLS INITBKS

RXINES : RXINE Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : TXOUTE Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : TXSTPE Set
bits : 2 - 2 (1 bit)
access : write-only

PERRES : PERRE Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKEDE Set
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIES : ERRORFIE Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : RXSTALLDE Set
bits : 6 - 6 (1 bit)
access : write-only

RAMACERES : RAMACERE Set
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKES : NBUSYBKE Set
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONS : FIFOCON Set
bits : 14 - 14 (1 bit)
access : write-only

PFREEZES : PFREEZE Set
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLS : INITDTGL Set
bits : 18 - 18 (1 bit)
access : write-only

INITBKS : INITBK Set
bits : 19 - 19 (1 bit)
access : write-only


UPCON0CLR

Pipe Control Clear Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON0CLR UPCON0CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON1CLR

Pipe Control Clear Register
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON1CLR UPCON1CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON2CLR

Pipe Control Clear Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON2CLR UPCON2CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON3CLR

Pipe Control Clear Register
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON3CLR UPCON3CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON4CLR

Pipe Control Clear Register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON4CLR UPCON4CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON5CLR

Pipe Control Clear Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON5CLR UPCON5CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON6CLR

Pipe Control Clear Register
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON6CLR UPCON6CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPCON7CLR

Pipe Control Clear Register
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UPCON7CLR UPCON7CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC ERRORFIEC RXSTALLDEC RAMACEREC NBUSYBKEC FIFOCONC PFREEZEC INITDTGLC INITBKC

RXINEC : RXINE Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : TXOUTE Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : TXSTPE Clear
bits : 2 - 2 (1 bit)
access : write-only

PERREC : PERRE Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKEDE Clear
bits : 4 - 4 (1 bit)
access : write-only

ERRORFIEC : ERRORFIE Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : RXTALLDE Clear
bits : 6 - 6 (1 bit)
access : write-only

RAMACEREC : RAMACERE Clear
bits : 10 - 10 (1 bit)
access : write-only

NBUSYBKEC : NBUSYBKE Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFOCON Clear
bits : 14 - 14 (1 bit)
access : write-only

PFREEZEC : PFREEZE Clear
bits : 17 - 17 (1 bit)
access : write-only

INITDTGLC : INITDTGL Clear
bits : 18 - 18 (1 bit)
access : read-only

INITBKC : INITBK Clear
bits : 19 - 19 (1 bit)
access : write-only


UPINRQ0

Pipe In Request
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ0 UPINRQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ1

Pipe In Request
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ1 UPINRQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ2

Pipe In Request
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ2 UPINRQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ3

Pipe In Request
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ3 UPINRQ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ4

Pipe In Request
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ4 UPINRQ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ5

Pipe In Request
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ5 UPINRQ5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ6

Pipe In Request
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ6 UPINRQ6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UPINRQ7

Pipe In Request
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPINRQ7 UPINRQ7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)


UDINTCLR

Device Global Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDINTCLR UDINTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPC MSOFC SOFC EORSTC WAKEUPC EORSMC UPRSMC

SUSPC : SUSP Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

MSOFC : MSOF Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

SOFC : SOF Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

EORSTC : EORST Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPC : WAKEUP Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

EORSMC : EORSM Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

UPRSMC : UPRSM Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only


USBCON

General Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCON USBCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZCLK USBE UIMOD

FRZCLK : Freeze USB Clock
bits : 14 - 14 (1 bit)

USBE : USBC Enable
bits : 15 - 15 (1 bit)

UIMOD : USBC Mode
bits : 24 - 24 (1 bit)


USBSTA

General Status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USBSTA USBSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUSRQ SPEED CLKUSABLE SUSPEND

VBUSRQ : VBus Request
bits : 9 - 9 (1 bit)
access : read-only

SPEED : Speed Status
bits : 12 - 13 (2 bit)
access : read-only

Enumeration: SPEEDSelect

0x0 : FULL

None

0x1 : HIGH

None

0x2 : LOW

None

End of enumeration elements list.

CLKUSABLE : USB Clock Usable
bits : 14 - 14 (1 bit)
access : read-only

SUSPEND : Suspend module state
bits : 16 - 16 (1 bit)
access : read-only


USBSTACLR

General Status Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USBSTACLR USBSTACLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMACERIC VBUSRQC

RAMACERIC : RAMACERI Clear
bits : 8 - 8 (1 bit)
access : write-only

VBUSRQC : VBUSRQ Clear
bits : 9 - 9 (1 bit)
access : write-only


USBSTASET

General Status Set Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USBSTASET USBSTASET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMACERIS VBUSRQS

RAMACERIS : RAMACERI Set
bits : 8 - 8 (1 bit)
access : write-only

VBUSRQS : VBUSRQ Set
bits : 9 - 9 (1 bit)
access : write-only


UVERS

IP Version Register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UVERS UVERS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant Number
bits : 16 - 18 (3 bit)
access : read-only


UFEATURES

IP Features Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UFEATURES UFEATURES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPTNBRMAX UTMIMODE

EPTNBRMAX : Maximum Number of Pipes/Endpints
bits : 0 - 3 (4 bit)
access : read-only

UTMIMODE : UTMI Mode
bits : 8 - 8 (1 bit)
access : read-only


UADDRSIZE

IP PB address size Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UADDRSIZE UADDRSIZE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UADDRSIZE

UADDRSIZE : IP PB Address Size
bits : 0 - 31 (32 bit)


UNAME1

IP Name Part One: HUSB
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UNAME1 UNAME1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNAME1

UNAME1 : IP Name Part One
bits : 0 - 31 (32 bit)


UNAME2

IP Name Part Two: HOST
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UNAME2 UNAME2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNAME2

UNAME2 : IP Name Part Two
bits : 0 - 31 (32 bit)


USBFSM

USB internal finite state machine
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USBFSM USBFSM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDSTATE

DRDSTATE : DualRoleDevice state
bits : 0 - 3 (4 bit)
access : read-only

Enumeration: DRDSTATESelect

0x0 : A_IDLE

None

0x1 : A_WAIT_VRISE

None

0x2 : A_WAIT_BCON

None

0x3 : A_HOST

None

0x4 : A_SUSPEND

None

0x5 : A_PERIPHERAL

None

0x6 : A_WAIT_VFALL

None

0x7 : A_VBUS_ERR

None

0x8 : A_WAIT_DISCHARGE

None

0x9 : B_IDLE

None

0xa : B_PERIPHERAL

None

0xb : B_WAIT_BEGIN_HNP

None

0xc : B_WAIT_DISCHARGE

None

0xd : B_WAIT_ACON

None

0xe : B_HOST

None

0xf : B_SRP_INIT

None

End of enumeration elements list.


UDESC

Endpoint descriptor table
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDESC UDESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDESCA

UDESCA : USB Descriptor Address
bits : 0 - 31 (32 bit)


UDINTSET

Device Global Interrupt Set Regsiter
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UDINTSET UDINTSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPS MSOFS SOFS EORSTS WAKEUPS EORSMS UPRSMS

SUSPS : SUSP Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

MSOFS : MSOF Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

SOFS : SOF Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

EORSTS : EORST Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPS : WAKEUP Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

EORSMS : EORSM Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

UPRSMS : UPRSM Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only



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