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BSCIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IER

ICR

PCLKSR

BR1

UNLOCK

CSCR

BR2

OSCCTRL32

RC32KCR

BR3

RC32KTUNE

BOD33CTRL

BOD33LEVEL

BOD33SAMPLING

BOD18CTRL

BOD18LEVEL

BRIFBVERSION

BGREFIFBVERSION

VREGIFGVERSION

BODIFCVERSION

RC32KIFBVERSION

OSC32IFAVERSION

VERSION

IDR

VREGCR

VREGNCSR

VREGLPCSR

RC1MCR

BGCR

BGCTRL

BGSR

IMR

ISR

BR0


IER

Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK LPBGRDY AE

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : write-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : write-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : write-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : write-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : write-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : write-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : write-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : write-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : write-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : write-only

VREGOK : Main VREG OK
bits : 10 - 10 (1 bit)
access : write-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


ICR

Interrupt Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK LPBGRDY AE

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : write-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : write-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : write-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : write-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : write-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : write-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : write-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : write-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : write-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : write-only

VREGOK : Main VREG OK
bits : 10 - 10 (1 bit)
access : write-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


PCLKSR

Power and Clocks Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCLKSR PCLKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK RC1MRDY LPBGRDY

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : read-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : read-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : read-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : read-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : read-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : read-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : read-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : read-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : read-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : read-only

VREGOK : Main VREG OK
bits : 10 - 10 (1 bit)
access : read-only

RC1MRDY : RC 1MHz Oscillator Ready
bits : 11 - 11 (1 bit)
access : read-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : read-only


BR1

Backup Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR1 BR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UNLOCK

Unlock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR KEY

ADDR : Unlock Address
bits : 0 - 9 (10 bit)
access : write-only

KEY : Unlock Key
bits : 24 - 31 (8 bit)
access : write-only

Enumeration: KEYSelect

0xaa : VALID

Valid Key to Unlock register

End of enumeration elements list.


CSCR

Chip Specific Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCR CSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BR2

Backup Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR2 BR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OSCCTRL32

Oscillator 32 Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCTRL32 OSCCTRL32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32EN PINSEL EN32K EN1K MODE SELCURR STARTUP

OSC32EN : 32 KHz Oscillator Enable
bits : 0 - 0 (1 bit)

PINSEL : Pins Select
bits : 1 - 1 (1 bit)

EN32K : 32 KHz output Enable
bits : 2 - 2 (1 bit)

EN1K : 1 KHz output Enable
bits : 3 - 3 (1 bit)

MODE : Oscillator Mode
bits : 8 - 10 (3 bit)

SELCURR : Current selection
bits : 12 - 15 (4 bit)

STARTUP : Oscillator Start-up Time
bits : 16 - 18 (3 bit)


RC32KCR

32 kHz RC Oscillator Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC32KCR RC32KCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCEN EN32K EN1K MODE REF FCD

EN : Enable as Generic clock source
bits : 0 - 0 (1 bit)

TCEN : Temperature Compensation Enable
bits : 1 - 1 (1 bit)

EN32K : Enable 32 KHz output
bits : 2 - 2 (1 bit)

EN1K : Enable 1 kHz output
bits : 3 - 3 (1 bit)

MODE : Mode Selection
bits : 4 - 4 (1 bit)

REF : Reference select
bits : 5 - 5 (1 bit)

FCD : Flash calibration done
bits : 7 - 7 (1 bit)


BR3

Backup Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR3 BR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RC32KTUNE

32kHz RC Oscillator Tuning Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC32KTUNE RC32KTUNE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINE COARSE

FINE : Fine value
bits : 0 - 5 (6 bit)

COARSE : Coarse Value
bits : 16 - 22 (7 bit)


BOD33CTRL

BOD33 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD33CTRL BOD33CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HYST ACTION MODE FCD SFV

EN : Enable
bits : 0 - 0 (1 bit)

HYST : BOD Hysteresis
bits : 1 - 1 (1 bit)

ACTION : Action
bits : 8 - 9 (2 bit)

MODE : Operation modes
bits : 16 - 16 (1 bit)

FCD : BOD Fuse Calibration Done
bits : 30 - 30 (1 bit)

SFV : BOD Control Register Store Final Value
bits : 31 - 31 (1 bit)


BOD33LEVEL

BOD33 Level Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD33LEVEL BOD33LEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : BOD Value
bits : 0 - 5 (6 bit)


BOD33SAMPLING

BOD33 Sampling Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD33SAMPLING BOD33SAMPLING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CSSEL PSEL

CEN : Clock Enable
bits : 0 - 0 (1 bit)

CSSEL : Clock Source Select
bits : 1 - 1 (1 bit)

PSEL : Prescaler Select
bits : 8 - 11 (4 bit)


BOD18CTRL

BOD18 Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD18CTRL BOD18CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HYST ACTION MODE FCD SFV

EN : Enable
bits : 0 - 0 (1 bit)

HYST : BOD Hysteresis
bits : 1 - 1 (1 bit)

ACTION : Action
bits : 8 - 9 (2 bit)

MODE : Operation modes
bits : 16 - 16 (1 bit)

FCD : BOD Fuse Calibration Done
bits : 30 - 30 (1 bit)

SFV : BOD Control Register Store Final Value
bits : 31 - 31 (1 bit)


BOD18LEVEL

BOD18 Level Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD18LEVEL BOD18LEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL RANGE

VAL : BOD Value
bits : 0 - 5 (6 bit)

RANGE : BOD Threshold Range
bits : 31 - 31 (1 bit)


BRIFBVERSION

Backup Register Interface Version Register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRIFBVERSION BRIFBVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)

VARIANT : Variant Number
bits : 16 - 19 (4 bit)


BGREFIFBVERSION

BGREFIFB Version Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BGREFIFBVERSION BGREFIFBVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant Number
bits : 16 - 19 (4 bit)
access : read-only


VREGIFGVERSION

VREGIFA Version Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VREGIFGVERSION VREGIFGVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant Number
bits : 16 - 19 (4 bit)
access : read-only


BODIFCVERSION

BODIFC Version Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BODIFCVERSION BODIFCVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)

VARIANT : Variant Number
bits : 16 - 19 (4 bit)


RC32KIFBVERSION

32 kHz RC Oscillator Version Register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RC32KIFBVERSION RC32KIFBVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant number
bits : 16 - 19 (4 bit)
access : read-only


OSC32IFAVERSION

32 KHz Oscillator Version Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSC32IFAVERSION OSC32IFAVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)

VARIANT : Variant nubmer
bits : 16 - 19 (4 bit)


VERSION

BSCIF Version Register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)

VARIANT : Variant Number
bits : 16 - 19 (4 bit)


IDR

Interrupt Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK LPBGRDY AE

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : write-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : write-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : write-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : write-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : write-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : write-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : write-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : write-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : write-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : write-only

VREGOK : Mai n VREG OK
bits : 10 - 10 (1 bit)
access : write-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : write-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : write-only


VREGCR

Voltage Regulator Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGCR VREGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS SSG SSW SSWEVT SFV

DIS : Voltage Regulator disable
bits : 0 - 0 (1 bit)

SSG : Spread Spectrum Generator Enable
bits : 8 - 8 (1 bit)

SSW : Stop Switching
bits : 9 - 9 (1 bit)

SSWEVT : Stop Switching On Event Enable
bits : 10 - 10 (1 bit)

SFV : Store Final Value
bits : 31 - 31 (1 bit)


VREGNCSR

Normal Mode Control and Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGNCSR VREGNCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VREGLPCSR

LP Mode Control and Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGLPCSR VREGLPCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RC1MCR

1MHz RC Clock Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RC1MCR RC1MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOE FCD CLKCAL

CLKOE : 1MHz RC Osc Clock Output Enable
bits : 0 - 0 (1 bit)

FCD : Flash Calibration Done
bits : 7 - 7 (1 bit)

CLKCAL : 1MHz RC Osc Calibration
bits : 8 - 12 (5 bit)


BGCR

Bandgap Calibration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGCR BGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BGCTRL

Bandgap Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGCTRL BGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCISEL TSEN

ADCISEL : ADC Input Selection
bits : 0 - 1 (2 bit)

Enumeration: ADCISELSelect

0x0 : DIS

None

0x1 : VTEMP

None

0x2 : VREF

None

End of enumeration elements list.

TSEN : Temperature Sensor Enable
bits : 8 - 8 (1 bit)


BGSR

Bandgap Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BGSR BGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGBUFRDY BGRDY LPBGRDY VREF

BGBUFRDY : Bandgap Buffer Ready
bits : 0 - 7 (8 bit)
access : read-only

Enumeration: BGBUFRDYSelect

0x1 : FLASH

None

0x2 : PLL

None

0x4 : VREG

None

0x8 : BUFRR

None

0x10 : ADC

None

0x20 : LCD

None

End of enumeration elements list.

BGRDY : Bandgap Voltage Reference Ready
bits : 16 - 16 (1 bit)
access : read-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 17 - 17 (1 bit)
access : read-only

VREF : Voltage Reference Used by the System
bits : 18 - 19 (2 bit)
access : read-only


IMR

Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK LPBGRDY AE

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : read-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : read-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : read-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : read-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : read-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : read-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : read-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : read-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : read-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : read-only

VREGOK : Main VREG OK
bits : 10 - 10 (1 bit)
access : read-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : read-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC32RDY RC32KRDY RC32KLOCK RC32KREFE RC32KSAT BOD33DET BOD18DET BOD33SYNRDY BOD18SYNRDY SSWRDY VREGOK LPBGRDY AE

OSC32RDY : 32kHz Oscillator Ready
bits : 0 - 0 (1 bit)
access : read-only

RC32KRDY : 32kHz RC Oscillator Ready
bits : 1 - 1 (1 bit)
access : read-only

RC32KLOCK : 32kHz RC Oscillator Lock
bits : 2 - 2 (1 bit)
access : read-only

RC32KREFE : 32kHz RC Oscillator Reference Error
bits : 3 - 3 (1 bit)
access : read-only

RC32KSAT : 32kHz RC Oscillator Saturation
bits : 4 - 4 (1 bit)
access : read-only

BOD33DET : BOD33 Detected
bits : 5 - 5 (1 bit)
access : read-only

BOD18DET : BOD18 Detected
bits : 6 - 6 (1 bit)
access : read-only

BOD33SYNRDY : BOD33 Synchronization Ready
bits : 7 - 7 (1 bit)
access : read-only

BOD18SYNRDY : BOD18 Synchronization Ready
bits : 8 - 8 (1 bit)
access : read-only

SSWRDY : VREG Stop Switching Ready
bits : 9 - 9 (1 bit)
access : read-only

VREGOK : Main VREG OK
bits : 10 - 10 (1 bit)
access : read-only

LPBGRDY : Low Power Bandgap Voltage Reference Ready
bits : 12 - 12 (1 bit)
access : read-only

AE : Access Error
bits : 31 - 31 (1 bit)
access : read-only


BR0

Backup Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR0 BR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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