Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Remap Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCB0 : Remap Command bit for Master 0
bits : 0 - 0 (1 bit)
Enumeration: RCB0Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB1 : Remap Command bit for Master 1
bits : 1 - 1 (1 bit)
Enumeration: RCB1Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB2 : Remap Command bit for Master 2
bits : 2 - 2 (1 bit)
Enumeration: RCB2Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB3 : Remap Command bit for Master 3
bits : 3 - 3 (1 bit)
Enumeration: RCB3Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB4 : Remap Command bit for Master 4
bits : 4 - 4 (1 bit)
Enumeration: RCB4Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB5 : Remap Command bit for Master 5
bits : 5 - 5 (1 bit)
Enumeration: RCB5Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB6 : Remap Command bit for Master 6
bits : 6 - 6 (1 bit)
Enumeration: RCB6Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB7 : Remap Command bit for Master 7
bits : 7 - 7 (1 bit)
Enumeration: RCB7Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB8 : Remap Command bit for Master 8
bits : 8 - 8 (1 bit)
Enumeration: RCB8Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB9 : Remap Command bit for Master 9
bits : 9 - 9 (1 bit)
Enumeration: RCB9Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB10 : Remap Command bit for Master 10
bits : 10 - 10 (1 bit)
Enumeration: RCB10Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB11 : Remap Command bit for Master 11
bits : 11 - 11 (1 bit)
Enumeration: RCB11Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB12 : Remap Command bit for Master 12
bits : 12 - 12 (1 bit)
Enumeration: RCB12Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB13 : Remap Command bit for Master 13
bits : 13 - 13 (1 bit)
Enumeration: RCB13Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB14 : Remap Command bit for Master 14
bits : 14 - 14 (1 bit)
Enumeration: RCB14Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB15 : Remap Command bit for Master 15
bits : 15 - 15 (1 bit)
Enumeration: RCB15Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Master Remap Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCB0 : Remap Command bit for Master 0
bits : 0 - 0 (1 bit)
Enumeration: RCB0Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB1 : Remap Command bit for Master 1
bits : 1 - 1 (1 bit)
Enumeration: RCB1Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB2 : Remap Command bit for Master 2
bits : 2 - 2 (1 bit)
Enumeration: RCB2Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB3 : Remap Command bit for Master 3
bits : 3 - 3 (1 bit)
Enumeration: RCB3Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB4 : Remap Command bit for Master 4
bits : 4 - 4 (1 bit)
Enumeration: RCB4Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB5 : Remap Command bit for Master 5
bits : 5 - 5 (1 bit)
Enumeration: RCB5Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB6 : Remap Command bit for Master 6
bits : 6 - 6 (1 bit)
Enumeration: RCB6Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB7 : Remap Command bit for Master 7
bits : 7 - 7 (1 bit)
Enumeration: RCB7Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB8 : Remap Command bit for Master 8
bits : 8 - 8 (1 bit)
Enumeration: RCB8Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB9 : Remap Command bit for Master 9
bits : 9 - 9 (1 bit)
Enumeration: RCB9Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB10 : Remap Command bit for Master 10
bits : 10 - 10 (1 bit)
Enumeration: RCB10Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB11 : Remap Command bit for Master 11
bits : 11 - 11 (1 bit)
Enumeration: RCB11Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB12 : Remap Command bit for Master 12
bits : 12 - 12 (1 bit)
Enumeration: RCB12Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB13 : Remap Command bit for Master 13
bits : 13 - 13 (1 bit)
Enumeration: RCB13Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB14 : Remap Command bit for Master 14
bits : 14 - 14 (1 bit)
Enumeration: RCB14Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
RCB15 : Remap Command bit for Master 15
bits : 15 - 15 (1 bit)
Enumeration: RCB15Select
0x0 : 0
Disable remapped address decoding for master
0x1 : 1
Enable remapped address decoding for master
End of enumeration elements list.
Special Function Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Special Function Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x12A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Special Function Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Special Function Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Special Function Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Priority Register B for Slave
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Special Function Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Special Function Register
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Master Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Special Function Register
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Slave Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Special Function Register
address_offset : 0x7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Priority Register A for Slave
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Priority Register B for Slave
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xA58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xA94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register A for Slave
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Number of Allowed Cycles for a Burst
bits : 0 - 7 (8 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0x0 : NO_DEFAULT
No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
0x1 : LAST_DEFAULT
Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
0x2 : FIXED_DEFAULT
Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Index of Default Master
bits : 18 - 21 (4 bit)
ARBT : Arbitration Type
bits : 24 - 24 (1 bit)
Enumeration: ARBTSelect
0x0 : ROUND_ROBIN
Round-Robin Arbitration
0x1 : FIXED_PRIORITY
Fixed Priority Arbitration
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0xC64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Priority Register A for Slave
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xC84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0xD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Master Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0x0 : INFINITE
Infinite Length
0x1 : SINGLE
Single Access
0x2 : FOUR_BEAT
Four Beat Burst
0x3 : EIGHT_BEAT
Eight Beat Burst
0x4 : SIXTEEN_BEAT
Sixteen Beat Burst
End of enumeration elements list.
Priority Register B for Slave
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Special Function Register
address_offset : 0xED8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFR : Special Function Register
bits : 0 - 31 (32 bit)
Priority Register A for Slave
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Priority Register A for Slave
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 3 (4 bit)
M1PR : Master 1 Priority
bits : 4 - 7 (4 bit)
M2PR : Master 2 Priority
bits : 8 - 11 (4 bit)
M3PR : Master 3 Priority
bits : 12 - 15 (4 bit)
M4PR : Master 4 Priority
bits : 16 - 19 (4 bit)
M5PR : Master 5 Priority
bits : 20 - 23 (4 bit)
M6PR : Master 6 Priority
bits : 24 - 27 (4 bit)
M7PR : Master 7 Priority
bits : 28 - 31 (4 bit)
Priority Register B for Slave
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 3 (4 bit)
M9PR : Master 9 Priority
bits : 4 - 7 (4 bit)
M10PR : Master 10 Priority
bits : 8 - 11 (4 bit)
M11PR : Master 11 Priority
bits : 12 - 15 (4 bit)
M12PR : Master 12 Priority
bits : 16 - 19 (4 bit)
M13PR : Master 13 Priority
bits : 20 - 23 (4 bit)
M14PR : Master 14 Priority
bits : 24 - 27 (4 bit)
M15PR : Master 15 Priority
bits : 28 - 31 (4 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.