Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
Enumeration: RSTRXSelect
0x0 : 0
No effect
0x1 : 1
Resets the receiver
End of enumeration elements list.
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
Enumeration: RSTTXSelect
0x0 : 0
No effect
0x1 : 1
Resets the transmitter
End of enumeration elements list.
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
Enumeration: RXENSelect
0x0 : 0
No effect
0x1 : 1
Enables the receiver, if RXDIS is 0
End of enumeration elements list.
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
Enumeration: RXDISSelect
0x0 : 0
No effect
0x1 : 1
Disables the receiver
End of enumeration elements list.
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
Enumeration: TXENSelect
0x0 : 0
No effect
0x1 : 1
Enables the transmitter if TXDIS is 0
End of enumeration elements list.
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
Enumeration: TXDISSelect
0x0 : 0
No effect
0x1 : 1
Disables the transmitter
End of enumeration elements list.
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
Enumeration: RSTSTASelect
0x0 : 0
No effect
0x1 : 1
Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR
End of enumeration elements list.
STTBRK : Start Break
bits : 9 - 9 (1 bit)
Enumeration: STTBRKSelect
0x0 : 0
No effect
0x1 : 1
Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted
End of enumeration elements list.
STPBRK : Stop Break
bits : 10 - 10 (1 bit)
Enumeration: STPBRKSelect
0x0 : 0
No effect
0x1 : 1
Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted
End of enumeration elements list.
STTTO : Start Time-out
bits : 11 - 11 (1 bit)
Enumeration: STTTOSelect
0x0 : 0
No effect
0x1 : 1
Starts waiting for a character before clocking the time-out counter
End of enumeration elements list.
SENDA : Send Address
bits : 12 - 12 (1 bit)
Enumeration: SENDASelect
0x0 : 0
No effect
0x1 : 1
In Multi-drop Mode only, the next character written to the THR is sent with the address bit set
End of enumeration elements list.
RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)
Enumeration: RSTITSelect
0x0 : 0
No effect
0x1 : 1
Resets ITERATION in CSR. No effect if the ISO7816 is not enabled
End of enumeration elements list.
RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)
Enumeration: RSTNACKSelect
0x0 : 0
No effect
0x1 : 1
Resets NACK in CSR
End of enumeration elements list.
RETTO : Rearm Time-out
bits : 15 - 15 (1 bit)
Enumeration: RETTOSelect
0x0 : 0
No effect
0x1 : 1
Restart Time-out
End of enumeration elements list.
DTREN : Data Terminal Ready Enable
bits : 16 - 16 (1 bit)
Enumeration: DTRENSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin DTR at 0
End of enumeration elements list.
DTRDIS : Data Terminal Ready Disable
bits : 17 - 17 (1 bit)
Enumeration: DTRDISSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin DTR to 1
End of enumeration elements list.
RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)
Enumeration: RTSENSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin RTS to 0
End of enumeration elements list.
RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)
Enumeration: RTSDISSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin RTS to 1
End of enumeration elements list.
LINABT : Abort the current LIN transmission
bits : 20 - 20 (1 bit)
LINWKUP : Sends a wakeup signal on the LIN bus
bits : 21 - 21 (1 bit)
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
Enumeration: RSTRXSelect
0x0 : 0
No effect
0x1 : 1
Resets the receiver
End of enumeration elements list.
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
Enumeration: RSTTXSelect
0x0 : 0
No effect
0x1 : 1
Resets the transmitter
End of enumeration elements list.
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
Enumeration: RXENSelect
0x0 : 0
No effect
0x1 : 1
Enables the receiver, if RXDIS is 0
End of enumeration elements list.
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
Enumeration: RXDISSelect
0x0 : 0
No effect
0x1 : 1
Disables the receiver
End of enumeration elements list.
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
Enumeration: TXENSelect
0x0 : 0
No effect
0x1 : 1
Enables the transmitter if TXDIS is 0
End of enumeration elements list.
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
Enumeration: TXDISSelect
0x0 : 0
No effect
0x1 : 1
Disables the transmitter
End of enumeration elements list.
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
Enumeration: RSTSTASelect
0x0 : 0
No effect
0x1 : 1
Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR
End of enumeration elements list.
STTBRK : Start Break
bits : 9 - 9 (1 bit)
Enumeration: STTBRKSelect
0x0 : 0
No effect
0x1 : 1
Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted
End of enumeration elements list.
STPBRK : Stop Break
bits : 10 - 10 (1 bit)
Enumeration: STPBRKSelect
0x0 : 0
No effect
0x1 : 1
Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted
End of enumeration elements list.
STTTO : Start Time-out
bits : 11 - 11 (1 bit)
Enumeration: STTTOSelect
0x0 : 0
No effect
0x1 : 1
Starts waiting for a character before clocking the time-out counter
End of enumeration elements list.
SENDA : Send Address
bits : 12 - 12 (1 bit)
Enumeration: SENDASelect
0x0 : 0
No effect
0x1 : 1
In Multi-drop Mode only, the next character written to the THR is sent with the address bit set
End of enumeration elements list.
RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)
Enumeration: RSTITSelect
0x0 : 0
No effect
0x1 : 1
Resets ITERATION in CSR. No effect if the ISO7816 is not enabled
End of enumeration elements list.
RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)
Enumeration: RSTNACKSelect
0x0 : 0
No effect
0x1 : 1
Resets NACK in CSR
End of enumeration elements list.
RETTO : Rearm Time-out
bits : 15 - 15 (1 bit)
Enumeration: RETTOSelect
0x0 : 0
No effect
0x1 : 1
Restart Time-out
End of enumeration elements list.
DTREN : Data Terminal Ready Enable
bits : 16 - 16 (1 bit)
Enumeration: DTRENSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin DTR at 0
End of enumeration elements list.
DTRDIS : Data Terminal Ready Disable
bits : 17 - 17 (1 bit)
Enumeration: DTRDISSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin DTR to 1
End of enumeration elements list.
RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)
Enumeration: RTSENSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin RTS to 0
End of enumeration elements list.
FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)
Enumeration: FCSSelect
0x0 : 0
No effect
0x1 : 1
Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer)
End of enumeration elements list.
RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)
Enumeration: RTSDISSelect
0x0 : 0
No effect
0x1 : 1
Drives the pin RTS to 1
End of enumeration elements list.
RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)
Enumeration: RCSSelect
0x0 : 0
No effect
0x1 : 1
Releases the Slave Select Line NSS (RTS pin)
End of enumeration elements list.
LINABT : Abort the current LIN transmission
bits : 20 - 20 (1 bit)
LINWKUP : Sends a wakeup signal on the LIN bus
bits : 21 - 21 (1 bit)
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
ITER : Iteration Interrupt Mask
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Mask
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Mask
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
NACK : Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Mask
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Received Interrupt Mask
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Mask
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Mask
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Mask
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Mask
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Mask
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Mask
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Mask
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
ITER : Iteration Interrupt Mask
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
Enumeration: UNRESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Mask
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Mask
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
NACK : Non Acknowledge Interrupt Mask
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Received Interrupt Mask
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Mask
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Mask
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Mask
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
MANE : Manchester Error Interrupt Mask
bits : 20 - 20 (1 bit)
MANEA : Manchester Error Interrupt Mask
bits : 24 - 24 (1 bit)
Enumeration: MANEASelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Mask
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Mask
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Mask
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Mask
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Mask
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Mask
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
The interrupt is disabled
0x1 : 1
The interrupt is enabled
End of enumeration elements list.
Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled
0x1 : 1
At least one complete character has been received and RHR has not yet been read
End of enumeration elements list.
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1
0x1 : 1
There is no character in the THR
End of enumeration elements list.
RXBRK : Break Received/End of Break
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Break received or End of Break detected since the last RSTSTA
0x1 : 1
Break Received or End of Break detected since the last RSTSTA
End of enumeration elements list.
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No overrun error has occurred since since the last RSTSTA
0x1 : 1
At least one overrun error has occurred since the last RSTSTA
End of enumeration elements list.
FRAME : Framing Error
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No stop bit has been detected low since the last RSTSTA
0x1 : 1
At least one stop bit has been detected low since the last RSTSTA
End of enumeration elements list.
PARE : Parity Error
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No parity error has been detected since the last RSTSTA
0x1 : 1
At least one parity error has been detected since the last RSTSTA
End of enumeration elements list.
TIMEOUT : Receiver Time-out
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
There has not been a time-out since the last Start Time-out command or the Time-out Register is 0
0x1 : 1
There has been a time-out since the last Start Time-out command
End of enumeration elements list.
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled
0x1 : 1
There is at least one character in either THR or the Transmit Shift Register
End of enumeration elements list.
ITER : Max number of Repetitions Reached
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
Maximum number of repetitions has not been reached since the last RSIT
0x1 : 1
Maximum number of repetitions has been reached since the last RSIT
End of enumeration elements list.
TXBUFE : Transmission Buffer Empty
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
The signal Buffer Empty from the Transmit PDC channel is inactive
0x1 : 1
The signal Buffer Empty from the Transmit PDC channel is active
End of enumeration elements list.
RXBUFF : Reception Buffer Full
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
The signal Buffer Full from the Receive PDC channel is inactive
0x1 : 1
The signal Buffer Full from the Receive PDC channel is active
End of enumeration elements list.
NACK : Non Acknowledge or LIN Break Sent or LIN Break Received
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Non Acknowledge has not been detected since the last RSTNACK
0x1 : 1
At least one Non Acknowledge has been detected since the last RSTNACK
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Flag
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No input change has been detected on the RI pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the RI pin since the last read of CSR
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Flag
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No input change has been detected on the DSR pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the DSR pin since the last read of CSR
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Flag
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No input change has been detected on the DCD pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the DCD pin since the last read of CSR
End of enumeration elements list.
CTSIC : Clear to Send Input Change Flag
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No input change has been detected on the CTS pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the CTS pin since the last read of CSR
End of enumeration elements list.
RI : Image of RI Input
bits : 20 - 20 (1 bit)
Enumeration: RISelect
0x0 : 0
RI is at 0
0x1 : 1
RI is at 1
End of enumeration elements list.
DSR : Image of DSR Input
bits : 21 - 21 (1 bit)
Enumeration: DSRSelect
0x0 : 0
DSR is at 0
0x1 : 1
DSR is at 1
End of enumeration elements list.
DCD : Image of DCD Input
bits : 22 - 22 (1 bit)
Enumeration: DCDSelect
0x0 : 0
DCD is at 0
0x1 : 1
DCD is at 1
End of enumeration elements list.
LINBLS : LIN Bus Line Status
bits : 23 - 23 (1 bit)
Enumeration: LINBLSSelect
0x0 : 0
CTS is at 0
0x1 : 1
CTS is at 1
End of enumeration elements list.
LINBE : LIN Bit Error
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Error
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
COMM_TX is at 0
0x1 : 1
COMM_TX is at 1
End of enumeration elements list.
LINHTE : LIN Header Timeout Error
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
COMM_RX is at 0
0x1 : 1
COMM_RX is at 1
End of enumeration elements list.
Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled
0x1 : 1
At least one complete character has been received and RHR has not yet been read
End of enumeration elements list.
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1
0x1 : 1
There is no character in the THR
End of enumeration elements list.
RXBRK : Break Received/End of Break
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Break received or End of Break detected since the last RSTSTA
0x1 : 1
Break Received or End of Break detected since the last RSTSTA
End of enumeration elements list.
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No overrun error has occurred since since the last RSTSTA
0x1 : 1
At least one overrun error has occurred since the last RSTSTA
End of enumeration elements list.
FRAME : Framing Error
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No stop bit has been detected low since the last RSTSTA
0x1 : 1
At least one stop bit has been detected low since the last RSTSTA
End of enumeration elements list.
PARE : Parity Error
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No parity error has been detected since the last RSTSTA
0x1 : 1
At least one parity error has been detected since the last RSTSTA
End of enumeration elements list.
TIMEOUT : Receiver Time-out
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
There has not been a time-out since the last Start Time-out command or the Time-out Register is 0
0x1 : 1
There has been a time-out since the last Start Time-out command
End of enumeration elements list.
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled
0x1 : 1
There is at least one character in either THR or the Transmit Shift Register
End of enumeration elements list.
ITER : Max number of Repetitions Reached
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
Maximum number of repetitions has not been reached since the last RSIT
0x1 : 1
Maximum number of repetitions has been reached since the last RSIT
End of enumeration elements list.
UNRE : SPI Underrun Error
bits : 10 - 10 (1 bit)
Enumeration: UNRESelect
0x0 : 0
No SPI underrun error has occurred since the last RSTSTA
0x1 : 1
At least one SPI underrun error has occurred since the last RSTSTA
End of enumeration elements list.
TXBUFE : Transmission Buffer Empty
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
The signal Buffer Empty from the Transmit PDC channel is inactive
0x1 : 1
The signal Buffer Empty from the Transmit PDC channel is active
End of enumeration elements list.
RXBUFF : Reception Buffer Full
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
The signal Buffer Full from the Receive PDC channel is inactive
0x1 : 1
The signal Buffer Full from the Receive PDC channel is active
End of enumeration elements list.
NACK : Non Acknowledge
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Non Acknowledge has not been detected since the last RSTNACK
0x1 : 1
At least one Non Acknowledge has been detected since the last RSTNACK
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Flag
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No input change has been detected on the RI pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the RI pin since the last read of CSR
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Flag
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No input change has been detected on the DSR pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the DSR pin since the last read of CSR
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Flag
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No input change has been detected on the DCD pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the DCD pin since the last read of CSR
End of enumeration elements list.
CTSIC : Clear to Send Input Change Flag
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No input change has been detected on the CTS pin since the last read of CSR
0x1 : 1
At least one input change has been detected on the CTS pin since the last read of CSR
End of enumeration elements list.
RI : Image of RI Input
bits : 20 - 20 (1 bit)
Enumeration: RISelect
0x0 : 0
RI is at 0
0x1 : 1
RI is at 1
End of enumeration elements list.
DSR : Image of DSR Input
bits : 21 - 21 (1 bit)
Enumeration: DSRSelect
0x0 : 0
DSR is at 0
0x1 : 1
DSR is at 1
End of enumeration elements list.
DCD : Image of DCD Input
bits : 22 - 22 (1 bit)
Enumeration: DCDSelect
0x0 : 0
DCD is at 0
0x1 : 1
DCD is at 1
End of enumeration elements list.
LINBLS : LIN Bus Line Status
bits : 23 - 23 (1 bit)
Enumeration: LINBLSSelect
0x0 : 0
CTS is at 0
0x1 : 1
CTS is at 1
End of enumeration elements list.
CTS : Image of CTS Input
bits : 23 - 23 (1 bit)
Enumeration: CTSSelect
0x0 : 0
CTS is at 0
0x1 : 1
CTS is at 1
End of enumeration elements list.
MANERR : Manchester Error
bits : 24 - 24 (1 bit)
Enumeration: MANERRSelect
0x0 : 0
No Manchester error has been detected since the last RSTSTA
0x1 : 1
At least one Manchester error has been detected since the last RSTSTA
End of enumeration elements list.
LINBE : LIN Bit Error
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Error
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
COMM_TX is at 0
0x1 : 1
COMM_TX is at 1
End of enumeration elements list.
LINHTE : LIN Header Timeout Error
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
COMM_RX is at 0
0x1 : 1
COMM_RX is at 1
End of enumeration elements list.
Receiver Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 8 (9 bit)
RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
Enumeration: RXSYNHSelect
0x0 : 0
Last character received is a Data
0x1 : 1
Last character received is a Command
End of enumeration elements list.
Receiver Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 8 (9 bit)
RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
Enumeration: RXSYNHSelect
0x0 : 0
Last character received is a Data
0x1 : 1
Last character received is a Command
End of enumeration elements list.
Transmitter Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
TXSYNH : Sync Field to be transmitted
bits : 15 - 15 (1 bit)
Enumeration: TXSYNHSelect
0x0 : 0
The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC
0x1 : 1
The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC
End of enumeration elements list.
Transmitter Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
TXSYNH : Sync Field to be transmitted
bits : 15 - 15 (1 bit)
Enumeration: TXSYNHSelect
0x0 : 0
The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC
0x1 : 1
The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC
End of enumeration elements list.
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divisor
bits : 0 - 15 (16 bit)
Enumeration: CDSelect
0x0 : DISABLE
Disables the clock
0x1 : BYPASS
Clock Divisor Bypass
0x2 : 2
Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD;
End of enumeration elements list.
FP : Fractional Part
bits : 16 - 18 (3 bit)
Enumeration: FPSelect
0x0 : 0
Fractional divider is disabled
End of enumeration elements list.
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divisor
bits : 0 - 15 (16 bit)
Enumeration: CDSelect
0x0 : DISABLE
Disables the clock
0x1 : BYPASS
Clock Divisor Bypass
0x2 : 2
Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD) Baud Rate (Synchronous Mode) = Selected Clock/CD
End of enumeration elements list.
FP : Fractional Part
bits : 16 - 18 (3 bit)
Enumeration: FPSelect
0x0 : 0
Fractional divider is disabled
End of enumeration elements list.
Receiver Time-out Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Time-out Value
bits : 0 - 16 (17 bit)
Enumeration: TOSelect
0x0 : DISABLE
Disables the RX Time-out function
End of enumeration elements list.
Receiver Time-out Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Time-out Value
bits : 0 - 16 (17 bit)
Enumeration: TOSelect
0x0 : DISABLE
Disables the RX Time-out function
End of enumeration elements list.
Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TG : Timeguard Value
bits : 0 - 7 (8 bit)
Enumeration: TGSelect
0x0 : DISABLE
Disables the TX Timeguard function.
End of enumeration elements list.
Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TG : Timeguard Value
bits : 0 - 7 (8 bit)
Enumeration: TGSelect
0x0 : DISABLE
Disables the TX Timeguard function.
End of enumeration elements list.
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
MODE : Usart Mode
bits : 0 - 3 (4 bit)
Enumeration: MODESelect
0x0 : NORMAL
Normal
0x1 : RS485
RS485
0x2 : HARDWARE
Hardware Handshaking
0x3 : MODEM
Modem
0x4 : ISO7816_T0
IS07816 Protocol: T = 0
0x6 : ISO7816_T1
IS07816 Protocol: T = 1
0x8 : IRDA
IrDA
0xa : LIN_Master
LIN Master
0xb : LIN_Slave
LIN Slave
0xe : SPI_Master
SPI Master
0xf : SPI_Slave
SPI Slave
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
Enumeration: USCLKSSelect
0x0 : MCK
MCK
0x1 : MCK_DIV
MCK / DIV
0x3 : SCK
SCK
End of enumeration elements list.
CHRL : Character Length.
bits : 6 - 7 (2 bit)
Enumeration: CHRLSelect
0x0 : 5
5 bits
0x1 : 6
6 bits
0x2 : 7
7 bits
0x3 : 8
8 bits
End of enumeration elements list.
CPHA : SPI CLock Phase
bits : 8 - 8 (1 bit)
Enumeration: CPHASelect
0x0 : 0
Data is changed on the leading edge of SPCK and captured on the following edge of SPCK
0x1 : 1
Data is captured on the leading edge of SPCK and changed on the following edge of SPCK
End of enumeration elements list.
PAR : Parity Type
bits : 9 - 11 (3 bit)
Enumeration: PARSelect
0x0 : EVEN
Even parity
0x1 : ODD
Odd parity
0x2 : SPACE
Parity forced to 0 (Space)
0x3 : MARK
Parity forced to 1 (Mark)
0x4 : NONE
No Parity
0x5 : 5
No Parity
0x6 : MULTI
Multi-drop mode
0x7 : 7
Multi-drop mode
End of enumeration elements list.
NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
Enumeration: NBSTOPSelect
0x0 : 1
1 stop bit
0x1 : 1_5
1.5 stop bits (Only valid if SYNC=0)
0x2 : 2
2 stop bits
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
Enumeration: CHMODESelect
0x0 : NORMAL
Normal Mode
0x1 : ECHO
Automatic Echo. Receiver input is connected to the TXD pin
0x2 : LOCAL_LOOP
Local Loopback. Transmitter output is connected to the Receiver Input
0x3 : REMOTE_LOOP
Remote Loopback. RXD pin is internally connected to the TXD pin
End of enumeration elements list.
CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
Enumeration: CPOLSelect
0x0 : ZERO
The inactive state value of SPCK is logic level zero
0x1 : ONE
The inactive state value of SPCK is logic level one
End of enumeration elements list.
MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
Enumeration: MODE9Select
0x0 : 0
CHRL defines character length
0x1 : 1
9-bit character length
End of enumeration elements list.
CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
Enumeration: CLKOSelect
0x0 : 0
The USART does not drive the SCK pin
0x1 : 1
The USART drives the SCK pin if USCLKS does not select the external clock SCK
End of enumeration elements list.
OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
Enumeration: OVERSelect
0x0 : X16
16x Oversampling
0x1 : X8
8x Oversampling
End of enumeration elements list.
INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)
Enumeration: INACKSelect
0x0 : 0
The NACK is generated
0x1 : 1
The NACK is not generated
End of enumeration elements list.
DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)
Enumeration: DSNACKSelect
0x0 : 0
NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set)
0x1 : 1
Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted
End of enumeration elements list.
INVDATA : Inverted data
bits : 23 - 23 (1 bit)
MAX_ITERATION : Max interation
bits : 24 - 26 (3 bit)
FILTER : Infrared Receive Line Filter
bits : 28 - 28 (1 bit)
Enumeration: FILTERSelect
0x0 : 0
The USART does not filter the receive line
0x1 : 1
The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority)
End of enumeration elements list.
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Usart Mode
bits : 0 - 3 (4 bit)
Enumeration: MODESelect
0x0 : NORMAL
Normal
0x1 : RS485
RS485
0x2 : HARDWARE
Hardware Handshaking
0x3 : MODEM
Modem
0x4 : ISO7816_T0
IS07816 Protocol: T = 0
0x6 : ISO7816_T1
IS07816 Protocol: T = 1
0x8 : IRDA
IrDA
0xa : LIN_Master
LIN Master
0xb : LIN_Slave
LIN Slave
0xe : SPI_Master
SPI Master
0xf : SPI_Slave
SPI Slave
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
Enumeration: USCLKSSelect
0x0 : MCK
MCK
0x1 : MCK_DIV
MCK / DIV
0x3 : SCK
SCK
End of enumeration elements list.
CHRL : Character Length.
bits : 6 - 7 (2 bit)
Enumeration: CHRLSelect
0x0 : 5
5 bits
0x1 : 6
6 bits
0x2 : 7
7 bits
0x3 : 8
8 bits
End of enumeration elements list.
CPHA : SPI CLock Phase
bits : 8 - 8 (1 bit)
Enumeration: CPHASelect
0x0 : 0
Data is changed on the leading edge of SPCK and captured on the following edge of SPCK
0x1 : 1
Data is captured on the leading edge of SPCK and changed on the following edge of SPCK
End of enumeration elements list.
SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)
Enumeration: SYNCSelect
0x0 : 0
USART operates in Synchronous Mode
0x1 : 1
USART operates in Asynchronous Mode
End of enumeration elements list.
PAR : Parity Type
bits : 9 - 11 (3 bit)
Enumeration: PARSelect
0x0 : EVEN
Even parity
0x1 : ODD
Odd parity
0x2 : SPACE
Parity forced to 0 (Space)
0x3 : MARK
Parity forced to 1 (Mark)
0x4 : NONE
No Parity
0x5 : 5
No Parity
0x6 : MULTI
Multi-drop mode
0x7 : 7
Multi-drop mode
End of enumeration elements list.
NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
Enumeration: NBSTOPSelect
0x0 : 1
1 stop bit
0x1 : 1_5
1.5 stop bits (Only valid if SYNC=0)
0x2 : 2
2 stop bits
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
Enumeration: CHMODESelect
0x0 : NORMAL
Normal Mode
0x1 : ECHO
Automatic Echo. Receiver input is connected to the TXD pin
0x2 : LOCAL_LOOP
Local Loopback. Transmitter output is connected to the Receiver Input
0x3 : REMOTE_LOOP
Remote Loopback. RXD pin is internally connected to the TXD pin
End of enumeration elements list.
CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
Enumeration: CPOLSelect
0x0 : ZERO
The inactive state value of SPCK is logic level zero
0x1 : ONE
The inactive state value of SPCK is logic level one
End of enumeration elements list.
MSBF : Bit Order
bits : 16 - 16 (1 bit)
Enumeration: MSBFSelect
0x0 : LSBF
Least Significant Bit first
0x1 : MSBF
Most Significant Bit first
End of enumeration elements list.
MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
Enumeration: MODE9Select
0x0 : 0
CHRL defines character length
0x1 : 1
9-bit character length
End of enumeration elements list.
CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
Enumeration: CLKOSelect
0x0 : 0
The USART does not drive the SCK pin
0x1 : 1
The USART drives the SCK pin if USCLKS does not select the external clock SCK
End of enumeration elements list.
OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
Enumeration: OVERSelect
0x0 : X16
16x Oversampling
0x1 : X8
8x Oversampling
End of enumeration elements list.
INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)
Enumeration: INACKSelect
0x0 : 0
The NACK is generated
0x1 : 1
The NACK is not generated
End of enumeration elements list.
DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)
Enumeration: DSNACKSelect
0x0 : 0
NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set)
0x1 : 1
Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted
End of enumeration elements list.
VAR_SYNC : Variable synchronization of command/data sync Start Frame Delimiter
bits : 22 - 22 (1 bit)
Enumeration: VAR_SYNCSelect
0x0 : 0
User defined configuration of command or data sync field depending on SYNC value
0x1 : 1
The sync field is updated when a character is written into THR register
End of enumeration elements list.
INVDATA : Inverted data
bits : 23 - 23 (1 bit)
MAX_ITERATION : Max interation
bits : 24 - 26 (3 bit)
FILTER : Infrared Receive Line Filter
bits : 28 - 28 (1 bit)
Enumeration: FILTERSelect
0x0 : 0
The USART does not filter the receive line
0x1 : 1
The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority)
End of enumeration elements list.
MAN : Manchester Encoder/Decoder Enable
bits : 29 - 29 (1 bit)
Enumeration: MANSelect
0x0 : 0
Manchester Encoder/Decoder is disabled
0x1 : 1
Manchester Encoder/Decoder is enabled
End of enumeration elements list.
MODSYNC : Manchester Synchronization Mode
bits : 30 - 30 (1 bit)
Enumeration: MODSYNCSelect
0x0 : 0
The Manchester Start bit is a 0 to 1 transition
0x1 : 1
The Manchester Start bit is a 1 to 0 transition
End of enumeration elements list.
ONEBIT : Start Frame Delimiter selector
bits : 31 - 31 (1 bit)
Enumeration: ONEBITSelect
0x0 : 0
Start Frame delimiter is COMMAND or DATA SYNC
0x1 : 1
Start Frame delimiter is One Bit
End of enumeration elements list.
FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 10 (11 bit)
Enumeration: FI_DI_RATIOSelect
0x0 : DISABLE
Baud Rate = 0
End of enumeration elements list.
FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 10 (11 bit)
Enumeration: FI_DI_RATIOSelect
0x0 : DISABLE
Baud Rate = 0
End of enumeration elements list.
Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NB_ERRORS : Error number during ISO7816 transfers
bits : 0 - 7 (8 bit)
Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NB_ERRORS : Error number during ISO7816 transfers
bits : 0 - 7 (8 bit)
IrDA Filter Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRDA_FILTER : Irda filter
bits : 0 - 7 (8 bit)
IrDA Filter Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRDA_FILTER : Irda filter
bits : 0 - 7 (8 bit)
Manchester Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PL : Transmitter Preamble Length
bits : 0 - 3 (4 bit)
Enumeration: TX_PLSelect
0x0 : 0
The Transmitter Preamble pattern generation is disabled
End of enumeration elements list.
TX_PP : Transmitter Preamble Pattern
bits : 8 - 9 (2 bit)
Enumeration: TX_PPSelect
0x0 : 0
ALL_ONE
0x1 : 1
ALL_ZERO
0x2 : 2
ZERO_ONE
0x3 : 3
ONE_ZERO
End of enumeration elements list.
TX_MPOL : Transmitter Manchester Polarity
bits : 12 - 12 (1 bit)
Enumeration: TX_MPOLSelect
0x0 : 0
Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition
0x1 : 1
Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition
End of enumeration elements list.
RX_PL : Receiver Preamble Length
bits : 16 - 19 (4 bit)
Enumeration: RX_PLSelect
0x0 : 0
The receiver preamble pattern detection is disabled
End of enumeration elements list.
RX_PP : Receiver Preamble Pattern detected
bits : 24 - 25 (2 bit)
Enumeration: RX_PPSelect
0x0 : 0
ALL_ONE
0x1 : 1
ALL_ZERO
0x2 : 2
ZERO_ONE
0x3 : 3
ONE_ZERO
End of enumeration elements list.
RX_MPOL : Receiver Manchester Polarity
bits : 28 - 28 (1 bit)
Enumeration: RX_MPOLSelect
0x0 : 0
Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition
0x1 : 1
Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition
End of enumeration elements list.
DRIFT : Drift compensation
bits : 30 - 30 (1 bit)
Enumeration: DRIFTSelect
0x0 : 0
The USART can not recover from an important clock drift
0x1 : 1
The USART can recover from clock drift. The 16X clock mode must be enabled
End of enumeration elements list.
Manchester Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PL : Transmitter Preamble Length
bits : 0 - 3 (4 bit)
Enumeration: TX_PLSelect
0x0 : 0
The Transmitter Preamble pattern generation is disabled
End of enumeration elements list.
TX_PP : Transmitter Preamble Pattern
bits : 8 - 9 (2 bit)
Enumeration: TX_PPSelect
0x0 : 0
ALL_ONE
0x1 : 1
ALL_ZERO
0x2 : 2
ZERO_ONE
0x3 : 3
ONE_ZERO
End of enumeration elements list.
TX_MPOL : Transmitter Manchester Polarity
bits : 12 - 12 (1 bit)
Enumeration: TX_MPOLSelect
0x0 : 0
Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition
0x1 : 1
Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition
End of enumeration elements list.
RX_PL : Receiver Preamble Length
bits : 16 - 19 (4 bit)
Enumeration: RX_PLSelect
0x0 : 0
The receiver preamble pattern detection is disabled
End of enumeration elements list.
RX_PP : Receiver Preamble Pattern detected
bits : 24 - 25 (2 bit)
Enumeration: RX_PPSelect
0x0 : 0
ALL_ONE
0x1 : 1
ALL_ZERO
0x2 : 2
ZERO_ONE
0x3 : 3
ONE_ZERO
End of enumeration elements list.
RX_MPOL : Receiver Manchester Polarity
bits : 28 - 28 (1 bit)
Enumeration: RX_MPOLSelect
0x0 : 0
Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition
0x1 : 1
Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition
End of enumeration elements list.
DRIFT : Drift compensation
bits : 30 - 30 (1 bit)
Enumeration: DRIFTSelect
0x0 : 0
The USART can not recover from an important clock drift
0x1 : 1
The USART can recover from clock drift. The 16X clock mode must be enabled
End of enumeration elements list.
LIN Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACT : LIN Node Action
bits : 0 - 1 (2 bit)
Enumeration: NACTSelect
0x0 : PUBLISH
The LIN Controller transmits the response
0x1 : SUBSCRIBE
The LIN Controller receives the response
0x2 : IGNORE
The LIN Controller doesn't transmit and doesn't receive the response
End of enumeration elements list.
PARDIS : Parity Disable
bits : 2 - 2 (1 bit)
CHKDIS : Checksum Disable
bits : 3 - 3 (1 bit)
CHKTYP : Checksum Type
bits : 4 - 4 (1 bit)
DLM : Data Length Mode
bits : 5 - 5 (1 bit)
FSDIS : Frame Slot Mode Disable
bits : 6 - 6 (1 bit)
WKUPTYP : Wakeup Signal Type
bits : 7 - 7 (1 bit)
DLC : Data Length Control
bits : 8 - 15 (8 bit)
PDCM : PDC Mode
bits : 16 - 16 (1 bit)
SYNCDIS : Synchronization Disable
bits : 17 - 17 (1 bit)
LIN Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACT : LIN Node Action
bits : 0 - 1 (2 bit)
Enumeration: NACTSelect
0x0 : PUBLISH
The LIN Controller transmits the response
0x1 : SUBSCRIBE
The LIN Controller receives the response
0x2 : IGNORE
The LIN Controller doesn't transmit and doesn't receive the response
End of enumeration elements list.
PARDIS : Parity Disable
bits : 2 - 2 (1 bit)
CHKDIS : Checksum Disable
bits : 3 - 3 (1 bit)
CHKTYP : Checksum Type
bits : 4 - 4 (1 bit)
DLM : Data Length Mode
bits : 5 - 5 (1 bit)
FSDIS : Frame Slot Mode Disable
bits : 6 - 6 (1 bit)
WKUPTYP : Wakeup Signal Type
bits : 7 - 7 (1 bit)
DLC : Data Length Control
bits : 8 - 15 (8 bit)
PDCM : PDC Mode
bits : 16 - 16 (1 bit)
SYNCDIS : Synchronization Disable
bits : 17 - 17 (1 bit)
LIN Identifier Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDCHR : Identifier Character
bits : 0 - 7 (8 bit)
LIN Identifier Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDCHR : Identifier Character
bits : 0 - 7 (8 bit)
LIN Baud Rate Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LINCD : Clock Divider after Synchronization
bits : 0 - 15 (16 bit)
LINFP : Fractional Part after Synchronization
bits : 16 - 18 (3 bit)
LIN Baud Rate Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LINCD : Clock Divider after Synchronization
bits : 0 - 15 (16 bit)
LINFP : Fractional Part after Synchronization
bits : 16 - 18 (3 bit)
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Enable
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXRDY : Transmitter Ready Interrupt Enable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXEMPTY : Transmitter Empty Interrupt Enable
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
ITER : Iteration Interrupt Enable
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Enable
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Enable
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
NACK : Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Enable
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Enable
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Enable
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Enable
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Enable
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Enable
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Enable
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Enable
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Enable
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Enable
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Enable
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Enable
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Enable
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXRDY : Transmitter Ready Interrupt Enable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXEMPTY : Transmitter Empty Interrupt Enable
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
ITER : Iteration Interrupt Enable
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
UNRE : SPI Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
Enumeration: UNRESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Enable
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Enable
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
NACK : Non Acknowledge Interrupt Enable
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Enable
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Enable
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Enable
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Enable
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
MANE : Manchester Error Interrupt Enable
bits : 20 - 20 (1 bit)
MANEA : Manchester Error Interrupt Enable
bits : 24 - 24 (1 bit)
Enumeration: MANEASelect
0x0 : 0
No effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Enable
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Enable
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Enable
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Enable
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Enable
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Enable
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Enable
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
No Effect
0x1 : 1
Enables the interrupt
End of enumeration elements list.
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Disable
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXRDY : Transmitter Ready Interrupt Disable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXEMPTY : Transmitter Empty Interrupt Disable
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
ITER : Iteration Interrupt Disable
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Disable
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Disable
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
NACK : Non Acknowledge or LIN Break Sent or LIN Break Received Interrupt Disable
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Disable
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Disable
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Disable
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Disable
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Disable
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Disable
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Disable
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Disable
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Disable
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Disable
bits : 0 - 0 (1 bit)
Enumeration: RXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXRDY : Transmitter Ready Interrupt Disable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
Enumeration: RXBRKSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
Enumeration: OVRESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
Enumeration: FRAMESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
Enumeration: PARESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
Enumeration: TIMEOUTSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXEMPTY : Transmitter Empty Interrupt Disable
bits : 9 - 9 (1 bit)
Enumeration: TXEMPTYSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
ITER : Iteration Interrupt Disable
bits : 10 - 10 (1 bit)
Enumeration: ITERSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
Enumeration: UNRESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
TXBUFE : Buffer Empty Interrupt Disable
bits : 11 - 11 (1 bit)
Enumeration: TXBUFESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
RXBUFF : Buffer Full Interrupt Disable
bits : 12 - 12 (1 bit)
Enumeration: RXBUFFSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
NACK : Non Acknowledge Interrupt Disable
bits : 13 - 13 (1 bit)
Enumeration: NACKSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Disable
bits : 14 - 14 (1 bit)
LINTC : LIN Transfer Conpleted Interrupt Disable
bits : 15 - 15 (1 bit)
RIIC : Ring Indicator Input Change Disable
bits : 16 - 16 (1 bit)
Enumeration: RIICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
DSRIC : Data Set Ready Input Change Disable
bits : 17 - 17 (1 bit)
Enumeration: DSRICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
DCDIC : Data Carrier Detect Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
Enumeration: DCDICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
Enumeration: CTSICSelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
MANE : Manchester Error Interrupt Disable
bits : 20 - 20 (1 bit)
MANEA : Manchester Error Interrupt Disable
bits : 24 - 24 (1 bit)
Enumeration: MANEASelect
0x0 : 0
No effect
0x1 : 1
Disables the corresponding interrupt
End of enumeration elements list.
LINBE : LIN Bus Error Interrupt Disable
bits : 25 - 25 (1 bit)
LINISFE : LIN Inconsistent Synch Field Error Interrupt Disable
bits : 26 - 26 (1 bit)
LINIPE : LIN Identifier Parity Interrupt Disable
bits : 27 - 27 (1 bit)
LINCE : LIN Checksum Error Interrupt Disable
bits : 28 - 28 (1 bit)
LINSNRE : LIN Slave Not Responding Error Interrupt Disable
bits : 29 - 29 (1 bit)
LINSTE : LIN Synch Tolerance Error Interrupt Disable
bits : 30 - 30 (1 bit)
Enumeration: LINSTESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
LINHTE : LIN Header Timeout Error Interrupt Disable
bits : 31 - 31 (1 bit)
Enumeration: LINHTESelect
0x0 : 0
No Effect
0x1 : 1
Disables the interrupt
End of enumeration elements list.
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
Enumeration: WPENSelect
0x0 : 0
Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII)
0x1 : 1
Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII)
End of enumeration elements list.
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
Enumeration: WPENSelect
0x0 : 0
Disables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII)
0x1 : 1
Enables the Write Protect if WPKEY corresponds to 0x858365 ( USA in ACII)
End of enumeration elements list.
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPV : Write Protect Violation Status
bits : 0 - 0 (1 bit)
Enumeration: WPVSelect
0x0 : 0
No Write Protect Violation has occurred since the last read of the WPSR register
0x1 : 1
A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC
End of enumeration elements list.
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPV : Write Protect Violation Status
bits : 0 - 0 (1 bit)
Enumeration: WPVSelect
0x0 : 0
No Write Protect Violation has occurred since the last read of the WPSR register
0x1 : 1
A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC
End of enumeration elements list.
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version
bits : 0 - 11 (12 bit)
MFN : MFN
bits : 16 - 19 (4 bit)
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version
bits : 0 - 11 (12 bit)
MFN : MFN
bits : 16 - 19 (4 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.