Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Channel Control Register Channel
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
Channel Control Register Channel
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
Stepper Motor Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Counter Value Channel
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Counter Value Channel
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Register A Channel
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Register B Channel
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Register A Channel
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Status Register Channel
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Disable Register Channel
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Mask Register Channel
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
Register B Channel
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Counter Value Channel
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Status Register Channel
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Register A Channel
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Interrupt Disable Register Channel
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Mask Register Channel
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
Register B Channel
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Channel Mode Register Channel
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
0x0 : TIMER_DIV1_CLOCK
TIMER_DIV1_CLOCK
0x1 : TIMER_DIV2_CLOCK
TIMER_DIV2_CLOCK
0x2 : TIMER_DIV3_CLOCK
TIMER_DIV3_CLOCK
0x3 : TIMER_DIV4_CLOCK
TIMER_DIV4_CLOCK
0x4 : TIMER_DIV5_CLOCK
TIMER_DIV5_CLOCK
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
Enumeration: CPCSTOPSelect
0x0 : 0
Counter clock is not stopped when counter reaches RC.
0x1 : 1
Counter clock is stopped when counter reaches RC.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
Enumeration: CPCDISSelect
0x0 : 0
Counter clock is not disabled when counter reaches RC.
0x1 : 1
Counter clock is disabled when counter reaches RC.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0x0 : TIOB_INPUT
TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
0x1 : XC0_OUTPUT
XC0 output
0x2 : XC1_OUTPUT
XC1 output
0x3 : XC2_OUTPUT
XC2 output
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
Enumeration: ENETRGSelect
0x0 : 0
The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
0x1 : 1
The external event resets the counter and starts the counter clock.
End of enumeration elements list.
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0x0 : UP_NO_AUTO
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN_NO_AUTO
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_AUTO
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_AUTO
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : WAVE
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Waveform Mode is disabled (Capture Mode is enabled).
0x1 : 1
Waveform Mode is enabled.
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
Channel Control Register Channel
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
Status Register Channel
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Channel Control Register Channel
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
Channel Mode Register Channel
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
0x0 : TIMER_DIV1_CLOCK
TIMER_DIV1_CLOCK
0x1 : TIMER_DIV2_CLOCK
TIMER_DIV2_CLOCK
0x2 : TIMER_DIV3_CLOCK
TIMER_DIV3_CLOCK
0x3 : TIMER_DIV4_CLOCK
TIMER_DIV4_CLOCK
0x4 : TIMER_DIV5_CLOCK
TIMER_DIV5_CLOCK
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
Enumeration: CPCSTOPSelect
0x0 : 0
Counter clock is not stopped when counter reaches RC.
0x1 : 1
Counter clock is stopped when counter reaches RC.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
Enumeration: CPCDISSelect
0x0 : 0
Counter clock is not disabled when counter reaches RC.
0x1 : 1
Counter clock is disabled when counter reaches RC.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0x0 : TIOB_INPUT
TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
0x1 : XC0_OUTPUT
XC0 output
0x2 : XC1_OUTPUT
XC1 output
0x3 : XC2_OUTPUT
XC2 output
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
Enumeration: ENETRGSelect
0x0 : 0
The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
0x1 : 1
The external event resets the counter and starts the counter clock.
End of enumeration elements list.
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0x0 : UP_NO_AUTO
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN_NO_AUTO
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_AUTO
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_AUTO
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : WAVE
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Waveform Mode is disabled (Capture Mode is enabled).
0x1 : 1
Waveform Mode is enabled.
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Stepper Motor Mode Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Channel Mode Register Channel
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPTURE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : Wave
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Capture Mode is enabled.
0x1 : 1
Capture Mode is disabled (Waveform Mode is enabled).
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
Interrupt Disable Register Channel
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
Counter Value Channel
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Register A Channel
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Interrupt Mask Register Channel
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
Stepper Motor Mode Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Register B Channel
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Status Register Channel
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Disable Register Channel
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Mask Register Channel
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
Counter Value Channel
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Register A Channel
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Channel Mode Register Channel
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPTURE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : Wave
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Capture Mode is enabled.
0x1 : 1
Capture Mode is disabled (Waveform Mode is enabled).
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
Stepper Motor Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Channel Control Register Channel
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
Channel Mode Register Channel
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
0x0 : TIMER_DIV1_CLOCK
TIMER_DIV1_CLOCK
0x1 : TIMER_DIV2_CLOCK
TIMER_DIV2_CLOCK
0x2 : TIMER_DIV3_CLOCK
TIMER_DIV3_CLOCK
0x3 : TIMER_DIV4_CLOCK
TIMER_DIV4_CLOCK
0x4 : TIMER_DIV5_CLOCK
TIMER_DIV5_CLOCK
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
Enumeration: CPCSTOPSelect
0x0 : 0
Counter clock is not stopped when counter reaches RC.
0x1 : 1
Counter clock is stopped when counter reaches RC.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
Enumeration: CPCDISSelect
0x0 : 0
Counter clock is not disabled when counter reaches RC.
0x1 : 1
Counter clock is disabled when counter reaches RC.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0x0 : TIOB_INPUT
TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
0x1 : XC0_OUTPUT
XC0 output
0x2 : XC1_OUTPUT
XC1 output
0x3 : XC2_OUTPUT
XC2 output
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
Enumeration: ENETRGSelect
0x0 : 0
The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output.
0x1 : 1
The external event resets the counter and starts the counter clock.
End of enumeration elements list.
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0x0 : UP_NO_AUTO
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN_NO_AUTO
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_AUTO
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_AUTO
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : WAVE
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Waveform Mode is disabled (Capture Mode is enabled).
0x1 : 1
Waveform Mode is enabled.
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0x0 : NONE
none
0x1 : SET
set
0x2 : CLEAR
clear
0x3 : TOGGLE
toggle
End of enumeration elements list.
Register B Channel
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Stepper Motor Mode Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Counter Value Channel
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Register A Channel
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 15 (16 bit)
Register B Channel
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 15 (16 bit)
Register C Channel
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 15 (16 bit)
Status Register Channel
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Status Register Channel
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No counter overflow has occurred since the last read of the Status Register.
0x1 : 1
A counter overflow has occurred since the last read of the Status Register.
End of enumeration elements list.
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
Load overrun has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0.
End of enumeration elements list.
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
RA Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RA Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
RB Compare has not occurred since the last read of the Status Register or WAVE:0.
0x1 : 1
RB Compare has occurred since the last read of the Status Register, if WAVE:1.
End of enumeration elements list.
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
RC Compare has not occurred since the last read of the Status Register.
0x1 : 1
RC Compare has occurred since the last read of the Status Register.
End of enumeration elements list.
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
RA Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RA Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
RB Load has not occurred since the last read of the Status Register or WAVE:1.
0x1 : 1
RB Load has occurred since the last read of the Status Register, if WAVE:0.
End of enumeration elements list.
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
External trigger has not occurred since the last read of the Status Register.
0x1 : 1
External trigger has occurred since the last read of the Status Register.
End of enumeration elements list.
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
Enumeration: CLKSTASelect
0x0 : 0
Clock is disabled.
0x1 : 1
Clock is enabled.
End of enumeration elements list.
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
Enumeration: MTIOASelect
0x0 : 0
TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low.
0x1 : 1
TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high.
End of enumeration elements list.
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
Enumeration: MTIOBSelect
0x0 : 0
TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low.
0x1 : 1
TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high.
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Disable Register Channel
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Enable Register Channel
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the Load Overrun Interrupt.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Compare Interrupt.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Compare Interrupt.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RA Load Interrupt.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the RB Load Interrupt.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Enables the External Trigger Interrupt.
End of enumeration elements list.
Interrupt Mask Register Channel
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
Interrupt Disable Register Channel
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Counter Overflow Interrupt.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the Load Overrun Interrupt (if WAVE:0).
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Compare Interrupt (if WAVE:1).
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RC Compare Interrupt.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RA Load Interrupt (if WAVE:0).
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the RB Load Interrupt (if WAVE:0).
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
No effect.
0x1 : 1
Disables the External Trigger Interrupt.
End of enumeration elements list.
TC Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchro Command
bits : 0 - 0 (1 bit)
Enumeration: SYNCSelect
0x0 : 0
No effect.
0x1 : 1
Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
End of enumeration elements list.
Channel Control Register Channel
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
Enumeration: CLKENSelect
0x0 : 0
No effect.
0x1 : 1
Enables the clock if CLKDIS is not 1.
End of enumeration elements list.
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
Enumeration: CLKDISSelect
0x0 : 0
No effect.
0x1 : 1
Disables the clock.
End of enumeration elements list.
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Enumeration: SWTRGSelect
0x0 : 0
No effect.
0x1 : 1
A software trigger is performed:the counter is reset and clock is started.
End of enumeration elements list.
TC Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchro Command
bits : 0 - 0 (1 bit)
Enumeration: SYNCSelect
0x0 : 0
No effect.
0x1 : 1
Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
End of enumeration elements list.
TC Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
Enumeration: TC0XC0SSelect
0x0 : TCLK0
Select TCLK0 as clock signal 0.
0x1 : NO_CLK
Select no clock as clock signal 0.
0x2 : TIOA1
Select TIOA1 as clock signal 0.
0x3 : TIOA2
Select TIOA2 as clock signal 0.
End of enumeration elements list.
TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
Enumeration: TC1XC1SSelect
0x0 : TCLK1
Select TCLK1 as clock signal 1.
0x1 : NO_CLK
Select no clock as clock signal 1.
0x2 : TIOA0
Select TIOA0 as clock signal 1.
0x3 : TIOA2
Select TIOA2 as clock signal 1.
End of enumeration elements list.
TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
Enumeration: TC2XC2SSelect
0x0 : TCLK2
Select TCLK2 as clock signal 2.
0x1 : NO_CLK
Select no clock as clock signal 2.
0x2 : TIOA0
Select TIOA0 as clock signal 2.
0x3 : TIOA1
Select TIOA1 as clock signal 2.
End of enumeration elements list.
Interrupt Mask Register Channel
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
Enumeration: COVFSSelect
0x0 : 0
The Counter Overflow Interrupt is disabled.
0x1 : 1
The Counter Overflow Interrupt is enabled.
End of enumeration elements list.
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
Enumeration: LOVRSSelect
0x0 : 0
The Load Overrun Interrupt is disabled.
0x1 : 1
The Load Overrun Interrupt is enabled.
End of enumeration elements list.
CPAS : RA Compare
bits : 2 - 2 (1 bit)
Enumeration: CPASSelect
0x0 : 0
The RA Compare Interrupt is disabled.
0x1 : 1
The RA Compare Interrupt is enabled.
End of enumeration elements list.
CPBS : RB Compare
bits : 3 - 3 (1 bit)
Enumeration: CPBSSelect
0x0 : 0
The RB Compare Interrupt is disabled.
0x1 : 1
The RB Compare Interrupt is enabled.
End of enumeration elements list.
CPCS : RC Compare
bits : 4 - 4 (1 bit)
Enumeration: CPCSSelect
0x0 : 0
The RC Compare Interrupt is disabled.
0x1 : 1
The RC Compare Interrupt is enabled.
End of enumeration elements list.
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
Enumeration: LDRASSelect
0x0 : 0
The Load RA Interrupt is disabled.
0x1 : 1
The Load RA Interrupt is enabled.
End of enumeration elements list.
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDRBSSelect
0x0 : 0
The Load RB Interrupt is disabled.
0x1 : 1
The Load RB Interrupt is enabled.
End of enumeration elements list.
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Enumeration: ETRGSSelect
0x0 : 0
The External Trigger Interrupt is disabled.
0x1 : 1
The External Trigger Interrupt is enabled.
End of enumeration elements list.
TC Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
Enumeration: TC0XC0SSelect
0x0 : TCLK0
Select TCLK0 as clock signal 0.
0x1 : NO_CLK
Select no clock as clock signal 0.
0x2 : TIOA1
Select TIOA1 as clock signal 0.
0x3 : TIOA2
Select TIOA2 as clock signal 0.
End of enumeration elements list.
TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
Enumeration: TC1XC1SSelect
0x0 : TCLK1
Select TCLK1 as clock signal 1.
0x1 : NO_CLK
Select no clock as clock signal 1.
0x2 : TIOA0
Select TIOA0 as clock signal 1.
0x3 : TIOA2
Select TIOA2 as clock signal 1.
End of enumeration elements list.
TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
Enumeration: TC2XC2SSelect
0x0 : TCLK2
Select TCLK2 as clock signal 2.
0x1 : NO_CLK
Select no clock as clock signal 2.
0x2 : TIOA0
Select TIOA0 as clock signal 2.
0x3 : TIOA1
Select TIOA1 as clock signal 2.
End of enumeration elements list.
Channel Mode Register Channel
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPTURE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
TIMER_CLOCK1
0x1 : TIMER_CLOCK2
TIMER_CLOCK2
0x2 : TIMER_CLOCK3
TIMER_CLOCK3
0x3 : TIMER_CLOCK4
TIMER_CLOCK4
0x4 : TIMER_CLOCK5
TIMER_CLOCK5
0x5 : XC0
XC0
0x6 : XC1
XC1
0x7 : XC2
XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
Enumeration: CLKISelect
0x0 : 0
Counter is incremented on rising edge of the clock.
0x1 : 1
Counter is incremented on falling edge of the clock.
End of enumeration elements list.
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NOT_GATED
The clock is not gated by an external signal.
0x1 : CLK_AND_XC0
XC0 is ANDed with the selected clock.
0x2 : CLK_AND_XC1
XC1 is ANDed with the selected clock.
0x3 : CLK_AND_XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
Enumeration: LDBSTOPSelect
0x0 : 0
Counter clock is not stopped when RB loading occurs.
0x1 : 1
Counter clock is stopped when RB loading occurs.
End of enumeration elements list.
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
Enumeration: LDBDISSelect
0x0 : 0
Counter clock is not disabled when RB loading occurs.
0x1 : 1
Counter clock is disabled when RB loading occurs.
End of enumeration elements list.
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE
rising edge
0x2 : NEG_EDGE
falling edge
0x3 : BOTH_EDGES
each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
Enumeration: ABETRGSelect
0x0 : 0
TIOB is used as an external trigger.
0x1 : 1
TIOA is used as an external trigger.
End of enumeration elements list.
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
Enumeration: CPCTRGSelect
0x0 : 0
RC Compare has no effect on the counter and its clock.
0x1 : 1
RC Compare resets the counter and starts the counter clock.
End of enumeration elements list.
WAVE : Wave
bits : 15 - 15 (1 bit)
Enumeration: WAVESelect
0x0 : 0
Capture Mode is enabled.
0x1 : 1
Capture Mode is disabled (Waveform Mode is enabled).
End of enumeration elements list.
LDRA : RA Loading Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NO_EDGE
none
0x1 : POS_EDGE_TIOA
rising edge of TIOA
0x2 : NEG_EDGE_TIOA
falling edge of TIOA
0x3 : BOTH_EDGES_TIOA
each edge of TIOA
End of enumeration elements list.
Stepper Motor Mode Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
Features Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRSIZE : Counter Size
bits : 0 - 7 (8 bit)
UPDNIMPL : Up Down is Implemented
bits : 8 - 8 (1 bit)
BRPBHSB : Bridge Type is PB to HSB
bits : 9 - 9 (1 bit)
Features Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRSIZE : Counter Size
bits : 0 - 7 (8 bit)
UPDNIMPL : Up Down is Implemented
bits : 8 - 8 (1 bit)
BRPBHSB : Bridge Type is PB to HSB
bits : 9 - 9 (1 bit)
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell.
bits : 0 - 11 (12 bit)
VARIANT : Reserved. Value subject to change. No functionality associated.
bits : 16 - 19 (4 bit)
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell.
bits : 0 - 11 (12 bit)
VARIANT : Reserved. Value subject to change. No functionality associated.
bits : 16 - 19 (4 bit)
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