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SMAP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

LENGTH

DATA

VERSION

SR

SCR

ADDR

CIDR

EXID

IDR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DIS CRC FSPR CE

EN : Enable
bits : 0 - 0 (1 bit)
access : write-only

DIS : Disable
bits : 1 - 1 (1 bit)
access : write-only

CRC : User Page Read
bits : 2 - 2 (1 bit)
access : write-only

FSPR : Flash Supplementary Page Read
bits : 3 - 3 (1 bit)
access : write-only

CE : Chip Erase
bits : 4 - 4 (1 bit)
access : write-only


LENGTH

Length Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENGTH LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH

LENGTH : Length Register
bits : 2 - 31 (30 bit)


DATA

Data Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Generic data register
bits : 0 - 31 (32 bit)


VERSION

VERSION register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant number
bits : 16 - 19 (4 bit)
access : read-only


SR

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE HCR BERR FAIL LCK EN PROT DBGP STATE

DONE : Operation done
bits : 0 - 0 (1 bit)
access : read-only

HCR : Hold Core reset
bits : 1 - 1 (1 bit)
access : read-only

BERR : Bus error
bits : 2 - 2 (1 bit)
access : read-only

FAIL : Failure
bits : 3 - 3 (1 bit)
access : read-only

LCK : Lock
bits : 4 - 4 (1 bit)
access : read-only

EN : Enabled
bits : 8 - 8 (1 bit)
access : read-only

PROT : Protected
bits : 9 - 9 (1 bit)
access : read-only

DBGP : Debugger Present
bits : 10 - 10 (1 bit)
access : read-only

STATE : State
bits : 24 - 26 (3 bit)
access : read-only


SCR

Status Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE HCR BERR FAIL LCK

DONE : Done
bits : 0 - 0 (1 bit)
access : write-only

HCR : Hold Core Register
bits : 1 - 1 (1 bit)
access : write-only

BERR : Bus error
bits : 2 - 2 (1 bit)
access : write-only

FAIL : Failure
bits : 3 - 3 (1 bit)
access : write-only

LCK : Lock error
bits : 4 - 4 (1 bit)
access : write-only


ADDR

Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Address Value
bits : 2 - 31 (30 bit)


CIDR

Chip ID Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR CIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION EPROC NVPSIZ NVPSIZ2 SRAMSIZ ARCH NVPTYP EXT

VERSION : Version of the Device
bits : 0 - 4 (5 bit)
access : read-only

EPROC : Embedded Processor
bits : 5 - 7 (3 bit)
access : read-only

NVPSIZ : Nonvolatile Program Memory Size
bits : 8 - 11 (4 bit)
access : read-only

NVPSIZ2 : Second Nonvolatile Program Memory Size
bits : 12 - 15 (4 bit)
access : read-only

SRAMSIZ : Internal SRAM Size
bits : 16 - 20 (5 bit)
access : read-only

ARCH : Architecture Identifier
bits : 21 - 27 (7 bit)
access : read-only

NVPTYP : Nonvolatile Program Memory Type
bits : 28 - 30 (3 bit)
access : read-only

EXT : Extension Flag
bits : 31 - 31 (1 bit)
access : read-only


EXID

Chip ID Extension Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EXID EXID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXID

EXID : Chip ID Extension
bits : 0 - 31 (32 bit)
access : read-only


IDR

AP Identification register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APIDV APID CLSS IC CC REVISION

APIDV : AP Identification Variant
bits : 0 - 3 (4 bit)
access : read-only

APID : AP Identification
bits : 4 - 7 (4 bit)
access : read-only

CLSS : Class
bits : 16 - 16 (1 bit)
access : read-only

IC : JEP-106 Identity Code
bits : 17 - 23 (7 bit)
access : read-only

CC : JEP-106 Continuation Code
bits : 24 - 27 (4 bit)
access : read-only

REVISION : Revision
bits : 28 - 31 (4 bit)
access : read-only



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