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PDCA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MAR0

TCR0

TCRR2

MAR11

PSR11

TCR11

CR2

MARR11

TCRR11

CR11

MR11

SR11

MR2

IER11

IDR11

IMR11

ISR11

SR2

MAR12

PSR12

TCR12

IER2

MARR12

TCRR12

CR12

MR12

IDR2

SR12

IER12

IDR12

IMR12

ISR12

IMR2

MAR13

PSR13

ISR2

TCR13

MARR13

TCRR13

CR13

MARR0

MAR3

MR13

SR13

IER13

IDR13

IMR13

PSR3

ISR13

MAR14

TCR3

PSR14

TCR14

MARR14

TCRR14

CR14

MARR3

MR14

SR14

IER14

IDR14

IMR14

TCRR3

ISR14

MAR15

CR3

PSR15

TCR15

MARR15

TCRR15

CR15

MR3

MR15

SR15

TCRR0

IER15

IDR15

IMR15

SR3

ISR15

IER3

IDR3

IMR3

ISR3

CR0

MAR4

PSR4

TCR4

MARR4

TCRR4

CR4

MR0

MR4

SR4

IER4

IDR4

IMR4

SR0

ISR4

MAR5

PSR5

TCR5

IER0

MAR1

MARR5

TCRR5

CR5

MR5

IDR0

SR5

IER5

IDR5

PSR1

IMR5

ISR5

IMR0

MAR6

PSR6

ISR0

TCR1

TCR6

MARR6

TCRR6

CR6

MR6

SR6

MARR1

IER6

IDR6

IMR6

ISR6

TCRR1

MAR7

PSR7

TCR7

MARR7

TCRR7

CR7

CR1

MR7

SR7

PSR0

PCONTROL

PRDATA0

PRSTALL0

PRLAT0

PWDATA0

PWSTALL0

PWLAT0

PRDATA1

IER7

PRSTALL1

PRLAT1

PWDATA1

PWSTALL1

PWLAT1

VERSION

IDR7

IMR7

MR1

ISR7

MAR8

PSR8

SR1

TCR8

MARR8

TCRR8

CR8

MR8

IER1

SR8

IER8

IDR8

IMR8

ISR8

IDR1

MAR9

PSR9

IMR1

TCR9

MARR9

TCRR9

MAR2

CR9

ISR1

MR9

SR9

IER9

IDR9

IMR9

PSR2

ISR9

MAR10

PSR10

TCR2

TCR10

MARR10

TCRR10

CR10

MR10

MARR2

SR10

IER10

IDR10

IMR10

ISR10


MAR0

Memory Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR0 MAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


TCR0

Transfer Counter Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR0 TCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


TCRR2

Transfer Counter Reload Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR2 TCRR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


MAR11

Memory Address Register
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR11 MAR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR11

Peripheral Select Register
address_offset : 0x10B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR11 PSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR11

Transfer Counter Register
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR11 TCR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


CR2

Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MARR11

Memory Address Reload Register
address_offset : 0x111C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR11 MARR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR11

Transfer Counter Reload Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR11 TCRR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR11

Control Register
address_offset : 0x1184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR11 CR11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR11

Mode Register
address_offset : 0x11B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR11 MR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR11

Status Register
address_offset : 0x11EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR11 SR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


MR2

Mode Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR2 MR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


IER11

Interrupt Enable Register
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER11 IER11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR11

Interrupt Disable Register
address_offset : 0x1254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR11 IDR11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR11

Interrupt Mask Register
address_offset : 0x1288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR11 IMR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR11

Interrupt Status Register
address_offset : 0x12BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR11 ISR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR2

Status Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


MAR12

Memory Address Register
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR12 MAR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR12

Peripheral Select Register
address_offset : 0x13B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR12 PSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR12

Transfer Counter Register
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR12 TCR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


IER2

Interrupt Enable Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER2 IER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MARR12

Memory Address Reload Register
address_offset : 0x1428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR12 MARR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR12

Transfer Counter Reload Register
address_offset : 0x1460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR12 TCRR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR12

Control Register
address_offset : 0x1498 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR12 CR12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR12

Mode Register
address_offset : 0x14D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR12 MR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


IDR2

Interrupt Disable Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR2 IDR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR12

Status Register
address_offset : 0x1508 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR12 SR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER12

Interrupt Enable Register
address_offset : 0x1540 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER12 IER12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR12

Interrupt Disable Register
address_offset : 0x1578 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR12 IDR12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR12

Interrupt Mask Register
address_offset : 0x15B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR12 IMR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR12

Interrupt Status Register
address_offset : 0x15E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR12 ISR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR2

Interrupt Mask Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR2 IMR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR13

Memory Address Register
address_offset : 0x16C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR13 MAR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR13

Peripheral Select Register
address_offset : 0x16FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR13 PSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


ISR2

Interrupt Status Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR2 ISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


TCR13

Transfer Counter Register
address_offset : 0x1738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR13 TCR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR13

Memory Address Reload Register
address_offset : 0x1774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR13 MARR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR13

Transfer Counter Reload Register
address_offset : 0x17B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR13 TCRR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR13

Control Register
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR13 CR13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MARR0

Memory Address Reload Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR0 MARR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


MAR3

Memory Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR3 MAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


MR13

Mode Register
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR13 MR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR13

Status Register
address_offset : 0x1864 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR13 SR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER13

Interrupt Enable Register
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER13 IER13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR13

Interrupt Disable Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR13 IDR13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR13

Interrupt Mask Register
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR13 IMR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


PSR3

Peripheral Select Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR3 PSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


ISR13

Interrupt Status Register
address_offset : 0x1954 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR13 ISR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR14

Memory Address Register
address_offset : 0x1A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR14 MAR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


TCR3

Transfer Counter Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR3 TCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


PSR14

Peripheral Select Register
address_offset : 0x1A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR14 PSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR14

Transfer Counter Register
address_offset : 0x1AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR14 TCR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR14

Memory Address Reload Register
address_offset : 0x1B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR14 MARR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR14

Transfer Counter Reload Register
address_offset : 0x1B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR14 TCRR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR14

Control Register
address_offset : 0x1B80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR14 CR14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MARR3

Memory Address Reload Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR3 MARR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


MR14

Mode Register
address_offset : 0x1BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR14 MR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR14

Status Register
address_offset : 0x1C00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR14 SR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER14

Interrupt Enable Register
address_offset : 0x1C40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER14 IER14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR14

Interrupt Disable Register
address_offset : 0x1C80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR14 IDR14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR14

Interrupt Mask Register
address_offset : 0x1CC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR14 IMR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


TCRR3

Transfer Counter Reload Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR3 TCRR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


ISR14

Interrupt Status Register
address_offset : 0x1D00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR14 ISR14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR15

Memory Address Register
address_offset : 0x1E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR15 MAR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


CR3

Control Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


PSR15

Peripheral Select Register
address_offset : 0x1E44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR15 PSR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR15

Transfer Counter Register
address_offset : 0x1E88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR15 TCR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR15

Memory Address Reload Register
address_offset : 0x1ECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR15 MARR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR15

Transfer Counter Reload Register
address_offset : 0x1F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR15 TCRR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR15

Control Register
address_offset : 0x1F54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR15 CR15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR3

Mode Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR3 MR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


MR15

Mode Register
address_offset : 0x1F98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR15 MR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR15

Status Register
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR15 SR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


TCRR0

Transfer Counter Reload Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR0 TCRR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


IER15

Interrupt Enable Register
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER15 IER15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR15

Interrupt Disable Register
address_offset : 0x2064 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR15 IDR15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR15

Interrupt Mask Register
address_offset : 0x20A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR15 IMR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR3

Status Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


ISR15

Interrupt Status Register
address_offset : 0x20EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR15 ISR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IER3

Interrupt Enable Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER3 IER3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR3

Interrupt Disable Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR3 IDR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR3

Interrupt Mask Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR3 IMR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR3

Interrupt Status Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR3 ISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


CR0

Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MAR4

Memory Address Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR4 MAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR4

Peripheral Select Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR4 PSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR4

Transfer Counter Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR4 TCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR4

Memory Address Reload Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR4 MARR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR4

Transfer Counter Reload Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR4 TCRR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR4

Control Register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR4 CR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR0

Mode Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0 MR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


MR4

Mode Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR4 MR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR4

Status Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR4 SR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER4

Interrupt Enable Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER4 IER4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR4

Interrupt Disable Register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR4 IDR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR4

Interrupt Mask Register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR4 IMR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR0

Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR0 SR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


ISR4

Interrupt Status Register
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR4 ISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR5

Memory Address Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR5 MAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR5

Peripheral Select Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR5 PSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR5

Transfer Counter Register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR5 TCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


IER0

Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER0 IER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR1

Memory Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR1 MAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


MARR5

Memory Address Reload Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR5 MARR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR5

Transfer Counter Reload Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR5 TCRR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR5

Control Register
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR5 CR5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR5

Mode Register
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR5 MR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


IDR0

Interrupt Disable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR0 IDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR5

Status Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR5 SR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER5

Interrupt Enable Register
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER5 IER5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR5

Interrupt Disable Register
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR5 IDR5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


PSR1

Peripheral Select Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR1 PSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


IMR5

Interrupt Mask Register
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR5 IMR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR5

Interrupt Status Register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR5 ISR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR0

Interrupt Mask Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR0 IMR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR6

Memory Address Register
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR6 MAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR6

Peripheral Select Register
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR6 PSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


ISR0

Interrupt Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR0 ISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


TCR1

Transfer Counter Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR1 TCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


TCR6

Transfer Counter Register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR6 TCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR6

Memory Address Reload Register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR6 MARR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR6

Transfer Counter Reload Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR6 TCRR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR6

Control Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR6 CR6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR6

Mode Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR6 MR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR6

Status Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR6 SR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


MARR1

Memory Address Reload Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR1 MARR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


IER6

Interrupt Enable Register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER6 IER6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR6

Interrupt Disable Register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR6 IDR6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR6

Interrupt Mask Register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR6 IMR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR6

Interrupt Status Register
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR6 ISR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


TCRR1

Transfer Counter Reload Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR1 TCRR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


MAR7

Memory Address Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR7 MAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR7

Peripheral Select Register
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR7 PSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR7

Transfer Counter Register
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR7 TCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR7

Memory Address Reload Register
address_offset : 0x76C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR7 MARR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR7

Transfer Counter Reload Register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR7 TCRR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR7

Control Register
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR7 CR7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


CR1

Control Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR7

Mode Register
address_offset : 0x7D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR7 MR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR7

Status Register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR7 SR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


PSR0

Peripheral Select Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR0 PSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


PCONTROL

Performance Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCONTROL PCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0EN CH1EN CH0OF CH1OF CH0RES CH1RES MON0CH MON1CH

CH0EN : Channel 0 Enabled
bits : 0 - 0 (1 bit)

CH1EN : Channel 1 Enabled.
bits : 1 - 1 (1 bit)

CH0OF : Channel 0 Overflow Freeze
bits : 4 - 4 (1 bit)

CH1OF : Channel 1 overflow freeze
bits : 5 - 5 (1 bit)

CH0RES : Channel 0 counter reset
bits : 8 - 8 (1 bit)

CH1RES : Channel 1 counter reset
bits : 9 - 9 (1 bit)

MON0CH : PDCA Channel to monitor with counter 0
bits : 16 - 21 (6 bit)

MON1CH : PDCA Channel to monitor with counter 1
bits : 24 - 29 (6 bit)


PRDATA0

Channel 0 Read Data Cycles
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRDATA0 PRDATA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data Cycles Counted Since Last reset
bits : 0 - 31 (32 bit)


PRSTALL0

Channel 0 Read Stall Cycles
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRSTALL0 PRSTALL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STALL

STALL : Stall Cycles counted since last reset
bits : 0 - 31 (32 bit)


PRLAT0

Channel 0 Read Max Latency
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRLAT0 PRLAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAT

LAT : Maximum Transfer Initiation cycles counted since last reset
bits : 0 - 15 (16 bit)


PWDATA0

Channel 0 Write Data Cycles
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWDATA0 PWDATA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data Cycles Counted since last Reset
bits : 0 - 31 (32 bit)


PWSTALL0

Channel 0 Write Stall Cycles
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWSTALL0 PWSTALL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STALL

STALL : Stall cycles counted since last reset
bits : 0 - 31 (32 bit)


PWLAT0

Channel0 Write Max Latency
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWLAT0 PWLAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAT

LAT : Maximum transfer initiation cycles counted since last reset
bits : 0 - 15 (16 bit)


PRDATA1

Channel 1 Read Data Cycles
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRDATA1 PRDATA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data Cycles Counted Since Last reset
bits : 0 - 31 (32 bit)


IER7

Interrupt Enable Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER7 IER7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


PRSTALL1

Channel Read Stall Cycles
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRSTALL1 PRSTALL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STALL

STALL : Stall Cycles Counted since last reset
bits : 0 - 31 (32 bit)


PRLAT1

Channel 1 Read Max Latency
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRLAT1 PRLAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAT

LAT : Maximum Transfer initiation cycles counted since last reset
bits : 0 - 15 (16 bit)


PWDATA1

Channel 1 Write Data Cycles
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWDATA1 PWDATA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data cycles Counted Since last reset
bits : 0 - 31 (32 bit)


PWSTALL1

Channel 1 Write stall Cycles
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWSTALL1 PWSTALL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STALL

STALL : Stall cycles counted since last reset
bits : 0 - 31 (32 bit)


PWLAT1

Channel 1 Read Max Latency
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PWLAT1 PWLAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAT

LAT : Maximum transfer initiation cycles counted since last reset
bits : 0 - 15 (16 bit)


VERSION

Version Register
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant Number
bits : 16 - 19 (4 bit)
access : read-only


IDR7

Interrupt Disable Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR7 IDR7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR7

Interrupt Mask Register
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR7 IMR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MR1

Mode Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR1 MR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


ISR7

Interrupt Status Register
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR7 ISR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR8

Memory Address Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR8 MAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR8

Peripheral Select Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR8 PSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


SR1

Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


TCR8

Transfer Counter Register
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR8 TCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR8

Memory Address Reload Register
address_offset : 0x978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR8 MARR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR8

Transfer Counter Reload Register
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR8 TCRR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR8

Control Register
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR8 CR8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR8

Mode Register
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR8 MR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


IER1

Interrupt Enable Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER1 IER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


SR8

Status Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR8 SR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER8

Interrupt Enable Register
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER8 IER8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR8

Interrupt Disable Register
address_offset : 0xA68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR8 IDR8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR8

Interrupt Mask Register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR8 IMR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR8

Interrupt Status Register
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR8 ISR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR1

Interrupt Disable Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR1 IDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR9

Memory Address Register
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR9 MAR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR9

Peripheral Select Register
address_offset : 0xB6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR9 PSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


IMR1

Interrupt Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR1 IMR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


TCR9

Transfer Counter Register
address_offset : 0xB98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR9 TCR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR9

Memory Address Reload Register
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR9 MARR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR9

Transfer Counter Reload Register
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR9 TCRR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


MAR2

Memory Address Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR2 MAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


CR9

Control Register
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR9 CR9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


ISR1

Interrupt Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR1 ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MR9

Mode Register
address_offset : 0xC48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR9 MR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


SR9

Status Register
address_offset : 0xC74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR9 SR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER9

Interrupt Enable Register
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER9 IER9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR9

Interrupt Disable Register
address_offset : 0xCCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR9 IDR9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR9

Interrupt Mask Register
address_offset : 0xCF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR9 IMR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


PSR2

Peripheral Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR2 PSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


ISR9

Interrupt Status Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR9 ISR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


MAR10

Memory Address Register
address_offset : 0xDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR10 MAR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MADDR

MADDR : Memory Address
bits : 0 - 31 (32 bit)


PSR10

Peripheral Select Register
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSR10 PSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : Peripheral Identifier
bits : 0 - 7 (8 bit)


TCR2

Transfer Counter Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR2 TCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


TCR10

Transfer Counter Register
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR10 TCR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCV

TCV : Transfer Counter Value
bits : 0 - 15 (16 bit)


MARR10

Memory Address Reload Register
address_offset : 0xE50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR10 MARR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


TCRR10

Transfer Counter Reload Register
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCRR10 TCRR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCRV

TCRV : Transfer Counter Reload Value
bits : 0 - 15 (16 bit)


CR10

Control Register
address_offset : 0xEB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR10 CR10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN TDIS ECLR

TEN : Transfer Enable
bits : 0 - 0 (1 bit)

TDIS : Transfer Disable
bits : 1 - 1 (1 bit)

ECLR : Error Clear
bits : 8 - 8 (1 bit)


MR10

Mode Register
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR10 MR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE ETRIG RING

SIZE : Transfer size
bits : 0 - 1 (2 bit)

Enumeration: SIZESelect

0x0 : Byte

None

0x1 : Half_Word

None

0x2 : Word

None

End of enumeration elements list.

ETRIG : Event trigger
bits : 2 - 2 (1 bit)

RING : Ring Buffer
bits : 3 - 3 (1 bit)


MARR2

Memory Address Reload Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MARR2 MARR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MARV

MARV : Memory Address Reload Value
bits : 0 - 31 (32 bit)


SR10

Status Register
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR10 SR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEN

TEN : Transfer Enabled
bits : 0 - 0 (1 bit)


IER10

Interrupt Enable Register
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER10 IER10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IDR10

Interrupt Disable Register
address_offset : 0xF70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR10 IDR10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


IMR10

Interrupt Mask Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR10 IMR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)


ISR10

Interrupt Status Register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR10 ISR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCZ TRC TERR

RCZ : Reload Counter Zero
bits : 0 - 0 (1 bit)

TRC : Transfer Complete
bits : 1 - 1 (1 bit)

TERR : Transfer Error
bits : 2 - 2 (1 bit)



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