\n

HCACHE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MAINT0

MAINT1

MCFG

MEN

MCTRL

MSR

CTRL

SR

VERSION


MAINT0

Maintenance Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MAINT0 MAINT0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVALL

INVALL : Cache Controller Invalidate All
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: INVALLSelect

0x0 : NO

No effect

0x1 : YES

Invalidate all cache entries

End of enumeration elements list.


MAINT1

Maintenance Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MAINT1 MAINT1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDEX

INDEX : Invalidate Index
bits : 4 - 7 (4 bit)
access : write-only


MCFG

Monitor Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG MCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : Cache Controller Monitor Counter Mode
bits : 0 - 1 (2 bit)

Enumeration: MODESelect

0x0 : CYCLE

Cycle Counter

0x1 : IHIT

Instruction Hit Counter

0x2 : DHIT

Data Hit Counter

End of enumeration elements list.


MEN

Monitor Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEN MEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MENABLE

MENABLE : Monitor Enable
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: MENABLESelect

0x0 : DIS

Disable Monitor Counter

0x1 : EN

Enable Monitor Counter

End of enumeration elements list.


MCTRL

Monitor Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MCTRL MCTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST

SWRST : Monitor Software Reset
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: SWRSTSelect

0x0 : NO

No effect

0x1 : YES

Reset event counter register

End of enumeration elements list.


MSR

Monitor Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSR MSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTCNT

EVENTCNT : Monitor Event Counter
bits : 0 - 31 (32 bit)
access : read-only


CTRL

Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN

CEN : Cache Enable
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: CENSelect

0x0 : NO

Disable Cache Controller

0x1 : YES

Enable Cache Controller

End of enumeration elements list.


SR

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSTS

CSTS : Cache Controller Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration: CSTSSelect

0x0 : DIS

Cache Controller Disabled

0x1 : EN

Cache Controller Enabled

End of enumeration elements list.


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : VERSION
bits : 0 - 11 (12 bit)
access : read-only

MFN : MFN
bits : 16 - 19 (4 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.