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CATB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

RAW

TIMING

THRESH

PINSEL

DMA

ISR

IER

IDR

IMR

SCR

CNTCR

INTCH1

INTCHCLR1

OUTTCH1

OUTTCHCLR1

IDLE

INTCH0

INTCHCLR0

LEVEL

OUTTCH0

OUTTCHCLR0

PARAMETER

VERSION


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RUN IIDLE ETRIG INTRES CKSEL DIFF DMAEN ESAMPLES CHARGET SWRST

EN : Module Enable
bits : 0 - 0 (1 bit)

RUN : Start Operation
bits : 1 - 1 (1 bit)

IIDLE : Initialize Idle Value
bits : 2 - 2 (1 bit)

ETRIG : Event Triggered Operation
bits : 3 - 3 (1 bit)

INTRES : Internal Resistors
bits : 4 - 4 (1 bit)

CKSEL : Clock Select
bits : 5 - 5 (1 bit)

DIFF : Differential Mode
bits : 6 - 6 (1 bit)

DMAEN : DMA Enable
bits : 7 - 7 (1 bit)

ESAMPLES : Number of Event Samples
bits : 8 - 14 (7 bit)

CHARGET : Charge Time
bits : 16 - 19 (4 bit)

SWRST : Software Reset
bits : 31 - 31 (1 bit)


RAW

Sensor Raw Value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAW RAW read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAWA RAWB

RAWA : Current Sensor Raw Value
bits : 16 - 23 (8 bit)
access : read-only

RAWB : Last Sensor Raw Value
bits : 24 - 31 (8 bit)
access : read-only


TIMING

Filter Timing Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLEVEL TIDLE

TLEVEL : Relative Level Smoothing
bits : 0 - 11 (12 bit)

TIDLE : Idle Smoothening
bits : 16 - 27 (12 bit)


THRESH

Threshold Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THRESH THRESH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTHRESH RTHRESH DIR LENGTH

FTHRESH : Fractional part of Threshold Value
bits : 0 - 11 (12 bit)

RTHRESH : Rational part of Threshold Value
bits : 12 - 19 (8 bit)

DIR : Threshold Direction
bits : 23 - 23 (1 bit)

LENGTH : Threshold Length
bits : 24 - 28 (5 bit)


PINSEL

Pin Selection Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINSEL PINSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINSEL

PINSEL : Pin Select
bits : 0 - 7 (8 bit)


DMA

Direct Memory Access Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA

DMA : Direct Memory Access
bits : 0 - 31 (32 bit)


ISR

Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INTCH OUTTCH

SAMPLE : Sample Ready Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

INTCH : In-touch Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only

OUTTCH : Out-of-Touch Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INTCH OUTTCH

SAMPLE : Sample Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

INTCH : In-touch Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

OUTTCH : Out-of-Touch Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INTCH OUTTCH

SAMPLE : Sample Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

INTCH : In-touch Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

OUTTCH : Out-of-Touch Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INTCH OUTTCH

SAMPLE : Sample Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

INTCH : In-touch Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

OUTTCH : Out-of-Touch Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only


SCR

Status Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE INTCH OUTTCH

SAMPLE : Sample Ready
bits : 0 - 0 (1 bit)
access : write-only

INTCH : In-touch
bits : 1 - 1 (1 bit)
access : write-only

OUTTCH : Out-of-Touch
bits : 2 - 2 (1 bit)
access : write-only


CNTCR

Counter Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCR CNTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP SPREAD REPEAT

TOP : Counter Top Value
bits : 0 - 23 (24 bit)

SPREAD : Spread Spectrum
bits : 24 - 27 (4 bit)

REPEAT : Repeat Measurements
bits : 28 - 30 (3 bit)


INTCH1

In-Touch Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTCH1 INTCH1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCH

INTCH : In-Touch
bits : 0 - 31 (32 bit)
access : read-only


INTCHCLR1

In-Touch Status Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTCHCLR1 INTCHCLR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCHCLR

INTCHCLR : In-Touch Clear
bits : 0 - 31 (32 bit)
access : write-only


OUTTCH1

Out-of-Touch Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OUTTCH1 OUTTCH1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTCH

OUTTCH : Out-of-Touch
bits : 0 - 31 (32 bit)
access : read-only


OUTTCHCLR1

Out-of-Touch Status Clear Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OUTTCHCLR1 OUTTCHCLR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTCHCLR

OUTTCHCLR : Out of Touch
bits : 0 - 31 (32 bit)
access : write-only


IDLE

Sensor Idle Level
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDLE IDLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIDLE RIDLE

FIDLE : Fractional Sensor Idle
bits : 0 - 11 (12 bit)

RIDLE : Integer Sensor Idle
bits : 12 - 27 (16 bit)


INTCH0

In-Touch Status Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTCH0 INTCH0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCH

INTCH : In-Touch
bits : 0 - 31 (32 bit)
access : read-only


INTCHCLR0

In-Touch Status Clear Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTCHCLR0 INTCHCLR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCHCLR

INTCHCLR : In-Touch Clear
bits : 0 - 31 (32 bit)
access : write-only


LEVEL

Sensor Relative Level
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LEVEL LEVEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLEVEL RLEVEL

FLEVEL : Fractional Sensor Level
bits : 0 - 11 (12 bit)
access : read-only

RLEVEL : Integer Sensor Level
bits : 12 - 19 (8 bit)
access : read-only


OUTTCH0

Out-of-Touch Status Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OUTTCH0 OUTTCH0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTCH

OUTTCH : Out-of-Touch
bits : 0 - 31 (32 bit)
access : read-only


OUTTCHCLR0

Out-of-Touch Status Clear Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OUTTCHCLR0 OUTTCHCLR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTCHCLR

OUTTCHCLR : Out of Touch
bits : 0 - 31 (32 bit)
access : write-only


PARAMETER

Parameter Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PARAMETER PARAMETER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPINS NSTATUS FRACTIONAL

NPINS : Number of Pins
bits : 0 - 7 (8 bit)
access : read-only

NSTATUS : Number of Status bits
bits : 8 - 15 (8 bit)
access : read-only

FRACTIONAL : Number of Fractional bits
bits : 16 - 19 (4 bit)
access : read-only


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant number
bits : 16 - 19 (4 bit)
access : read-only



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