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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IMR

RPR

RCR

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

SR

RHR

THR

BRGR

MR

IER

IDR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TXEMPTY TXBUFE RXBUFF

RXRDY : Mask RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : read-only

ENDRX : Mask End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : Mask End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Mask Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Mask Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

PARE : Mask Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only

TXEMPTY : Mask TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE : Mask TXBUFE Interrupt
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : Mask RXBUFF Interrupt
bits : 12 - 12 (1 bit)
access : read-only


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


SR

Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TXEMPTY TXBUFE RXBUFF

RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only

ENDRX : End of Receiver Transfer
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : End of Transmitter Transfer
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE : Transmission Buffer Empty
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full
bits : 12 - 12 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHR

RXCHR : Received Character
bits : 0 - 7 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHR

TXCHR : Character to be Transmitted
bits : 0 - 7 (8 bit)
access : write-only


BRGR

Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRGR BRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD

CD : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAR CHMODE

PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0x0 : EVEN

Even Parity

0x1 : ODD

Odd Parity

0x2 : SPACE

Space: parity forced to 0

0x3 : MARK

Mark: parity forced to 1

0x4 : NO

No Parity

End of enumeration elements list.

CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal Mode

0x1 : AUTOMATIC

Automatic Echo

0x2 : LOCAL_LOOPBACK

Local Loopback

0x3 : REMOTE_LOOPBACK

Remote Loopback

End of enumeration elements list.


IER

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TXEMPTY TXBUFE RXBUFF

RXRDY : Enable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : Enable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only

ENDRX : Enable End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : Enable End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Enable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Enable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only

PARE : Enable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only

TXEMPTY : Enable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE : Enable Buffer Empty Interrupt
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Enable Buffer Full Interrupt
bits : 12 - 12 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TXEMPTY TXBUFE RXBUFF

RXRDY : Disable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only

ENDRX : Disable End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : Disable End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Disable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Disable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only

PARE : Disable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only

TXEMPTY : Disable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE : Disable Buffer Empty Interrupt
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Disable Buffer Full Interrupt
bits : 12 - 12 (1 bit)
access : write-only



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