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SDIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

POWER

RESPCMD

RESPI1

RESP2

RESP3

RESP4

DTIMER

DLEN

DCTRL

DCOUNT

STA

ICR

MASK

CLKCR

FIFOCNT

ARG

FIFO

CMD


POWER

Bits 1:0 = PWRCTRL: Power supply control bits
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRCTRL

PWRCTRL : PWRCTRL
bits : 0 - 1 (2 bit)


RESPCMD

SDIO command register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESPCMD RESPCMD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPCMD

RESPCMD : RESPCMD
bits : 0 - 5 (6 bit)


RESPI1

Bits 31:0 = CARDSTATUS1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESPI1 RESPI1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS1

CARDSTATUS1 : CARDSTATUS1
bits : 0 - 31 (32 bit)


RESP2

Bits 31:0 = CARDSTATUS2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP2 RESP2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS2

CARDSTATUS2 : CARDSTATUS2
bits : 0 - 31 (32 bit)


RESP3

Bits 31:0 = CARDSTATUS3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP3 RESP3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS3

CARDSTATUS3 : CARDSTATUS3
bits : 0 - 31 (32 bit)


RESP4

Bits 31:0 = CARDSTATUS4
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP4 RESP4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS4

CARDSTATUS4 : CARDSTATUS4
bits : 0 - 31 (32 bit)


DTIMER

Bits 31:0 = DATATIME: Data timeout period
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTIMER DTIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATIME

DATATIME : Data timeout period
bits : 0 - 31 (32 bit)


DLEN

Bits 24:0 = DATALENGTH: Data length value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLEN DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATALENGTH

DATALENGTH : Data length value
bits : 0 - 24 (25 bit)


DCTRL

SDIO data control register (SDIO_DCTRL)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTRL DCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTEN DTDIR DTMODE DMAEN DBLOCKSIZE PWSTART PWSTOP RWMOD SDIOEN

DTEN : DTEN
bits : 0 - 0 (1 bit)

DTDIR : DTDIR
bits : 1 - 1 (1 bit)

DTMODE : DTMODE
bits : 2 - 2 (1 bit)

DMAEN : DMAEN
bits : 3 - 3 (1 bit)

DBLOCKSIZE : DBLOCKSIZE
bits : 4 - 7 (4 bit)

PWSTART : PWSTART
bits : 8 - 8 (1 bit)

PWSTOP : PWSTOP
bits : 9 - 9 (1 bit)

RWMOD : RWMOD
bits : 10 - 10 (1 bit)

SDIOEN : SDIOEN
bits : 11 - 11 (1 bit)


DCOUNT

Bits 24:0 = DATACOUNT: Data count value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCOUNT DCOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATACOUNT

DATACOUNT : Data count value
bits : 0 - 24 (25 bit)


STA

SDIO status register (SDIO_STA)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STA STA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAIL DCRCFAIL CTIMEOUT DTIMEOUT TXUNDERR RXOVERR CMDREND CMDSENT DATAEND STBITERR DBCKEND CMDACT TXACT RXACT TXFIFOHE RXFIFOHF TXFIFOF RXFIFOF TXFIFOE RXFIFOE TXDAVL RXDAVL SDIOIT CEATAEND

CCRCFAIL : CCRCFAIL
bits : 0 - 0 (1 bit)

DCRCFAIL : DCRCFAIL
bits : 1 - 1 (1 bit)

CTIMEOUT : CTIMEOUT
bits : 2 - 2 (1 bit)

DTIMEOUT : DTIMEOUT
bits : 3 - 3 (1 bit)

TXUNDERR : TXUNDERR
bits : 4 - 4 (1 bit)

RXOVERR : RXOVERR
bits : 5 - 5 (1 bit)

CMDREND : CMDREND
bits : 6 - 6 (1 bit)

CMDSENT : CMDSENT
bits : 7 - 7 (1 bit)

DATAEND : DATAEND
bits : 8 - 8 (1 bit)

STBITERR : STBITERR
bits : 9 - 9 (1 bit)

DBCKEND : DBCKEND
bits : 10 - 10 (1 bit)

CMDACT : CMDACT
bits : 11 - 11 (1 bit)

TXACT : TXACT
bits : 12 - 12 (1 bit)

RXACT : RXACT
bits : 13 - 13 (1 bit)

TXFIFOHE : TXFIFOHE
bits : 14 - 14 (1 bit)

RXFIFOHF : RXFIFOHF
bits : 15 - 15 (1 bit)

TXFIFOF : TXFIFOF
bits : 16 - 16 (1 bit)

RXFIFOF : RXFIFOF
bits : 17 - 17 (1 bit)

TXFIFOE : TXFIFOE
bits : 18 - 18 (1 bit)

RXFIFOE : RXFIFOE
bits : 19 - 19 (1 bit)

TXDAVL : TXDAVL
bits : 20 - 20 (1 bit)

RXDAVL : RXDAVL
bits : 21 - 21 (1 bit)

SDIOIT : SDIOIT
bits : 22 - 22 (1 bit)

CEATAEND : CEATAEND
bits : 23 - 23 (1 bit)


ICR

SDIO interrupt clear register (SDIO_ICR)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAILC DCRCFAILC CTIMEOUTC DTIMEOUTC TXUNDERRC RXOVERRC CMDRENDC CMDSENTC DATAENDC STBITERRC DBCKENDC SDIOITC CEATAENDC

CCRCFAILC : CCRCFAILC
bits : 0 - 0 (1 bit)

DCRCFAILC : DCRCFAILC
bits : 1 - 1 (1 bit)

CTIMEOUTC : CTIMEOUTC
bits : 2 - 2 (1 bit)

DTIMEOUTC : DTIMEOUTC
bits : 3 - 3 (1 bit)

TXUNDERRC : TXUNDERRC
bits : 4 - 4 (1 bit)

RXOVERRC : RXOVERRC
bits : 5 - 5 (1 bit)

CMDRENDC : CMDRENDC
bits : 6 - 6 (1 bit)

CMDSENTC : CMDSENTC
bits : 7 - 7 (1 bit)

DATAENDC : DATAENDC
bits : 8 - 8 (1 bit)

STBITERRC : STBITERRC
bits : 9 - 9 (1 bit)

DBCKENDC : DBCKENDC
bits : 10 - 10 (1 bit)

SDIOITC : SDIOITC
bits : 22 - 22 (1 bit)

CEATAENDC : CEATAENDC
bits : 23 - 23 (1 bit)


MASK

SDIO mask register (SDIO_MASK)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAILIE DCRCFAILIE CTIMEOUTIE DTIMEOUTIE TXUNDERRIE RXOVERRIE CMDRENDIE CMDSENTIE DATAENDIE STBITERRIE DBACKENDIE CMDACTIE TXACTIE RXACTIE TXFIFOHEIE RXFIFOHFIE TXFIFOFIE RXFIFOFIE TXFIFOEIE RXFIFOEIE TXDAVLIE RXDAVLIE SDIOITIE CEATENDIE

CCRCFAILIE : CCRCFAILIE
bits : 0 - 0 (1 bit)

DCRCFAILIE : DCRCFAILIE
bits : 1 - 1 (1 bit)

CTIMEOUTIE : CTIMEOUTIE
bits : 2 - 2 (1 bit)

DTIMEOUTIE : DTIMEOUTIE
bits : 3 - 3 (1 bit)

TXUNDERRIE : TXUNDERRIE
bits : 4 - 4 (1 bit)

RXOVERRIE : RXOVERRIE
bits : 5 - 5 (1 bit)

CMDRENDIE : CMDRENDIE
bits : 6 - 6 (1 bit)

CMDSENTIE : CMDSENTIE
bits : 7 - 7 (1 bit)

DATAENDIE : DATAENDIE
bits : 8 - 8 (1 bit)

STBITERRIE : STBITERRIE
bits : 9 - 9 (1 bit)

DBACKENDIE : DBACKENDIE
bits : 10 - 10 (1 bit)

CMDACTIE : CMDACTIE
bits : 11 - 11 (1 bit)

TXACTIE : TXACTIE
bits : 12 - 12 (1 bit)

RXACTIE : RXACTIE
bits : 13 - 13 (1 bit)

TXFIFOHEIE : TXFIFOHEIE
bits : 14 - 14 (1 bit)

RXFIFOHFIE : RXFIFOHFIE
bits : 15 - 15 (1 bit)

TXFIFOFIE : TXFIFOFIE
bits : 16 - 16 (1 bit)

RXFIFOFIE : RXFIFOFIE
bits : 17 - 17 (1 bit)

TXFIFOEIE : TXFIFOEIE
bits : 18 - 18 (1 bit)

RXFIFOEIE : RXFIFOEIE
bits : 19 - 19 (1 bit)

TXDAVLIE : TXDAVLIE
bits : 20 - 20 (1 bit)

RXDAVLIE : RXDAVLIE
bits : 21 - 21 (1 bit)

SDIOITIE : SDIOITIE
bits : 22 - 22 (1 bit)

CEATENDIE : CEATENDIE
bits : 23 - 23 (1 bit)


CLKCR

SDI clock control register (SDIO_CLKCR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCR CLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV CLKEN PWRSAV BYPASS WIDBUS NEGEDGE HWFC_EN

CLKDIV : Clock divide factor
bits : 0 - 7 (8 bit)

CLKEN : Clock enable bit
bits : 8 - 8 (1 bit)

PWRSAV : Power saving configuration bit
bits : 9 - 9 (1 bit)

BYPASS : Clock divider bypass enable bit
bits : 10 - 10 (1 bit)

WIDBUS : Wide bus mode enable bit
bits : 11 - 12 (2 bit)

NEGEDGE : SDIO_CK dephasing selection bit
bits : 13 - 13 (1 bit)

HWFC_EN : HW Flow Control enable
bits : 14 - 14 (1 bit)


FIFOCNT

Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFOCNT FIFOCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIF0COUNT

FIF0COUNT : FIF0COUNT
bits : 0 - 23 (24 bit)


ARG

Bits 31:0 = : Command argument
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARG ARG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDARG

CMDARG : Command argument
bits : 0 - 31 (32 bit)


FIFO

bits 31:0 = FIFOData: Receive and transmit FIFO data
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOData

FIFOData : FIFOData
bits : 0 - 31 (32 bit)


CMD

SDIO command register (SDIO_CMD)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDINDEX WAITRESP WAITINT WAITPEND CPSMEN SDIOSuspend ENCMDcompl nIEN CE_ATACMD

CMDINDEX : CMDINDEX
bits : 0 - 5 (6 bit)

WAITRESP : WAITRESP
bits : 6 - 7 (2 bit)

WAITINT : WAITINT
bits : 8 - 8 (1 bit)

WAITPEND : WAITPEND
bits : 9 - 9 (1 bit)

CPSMEN : CPSMEN
bits : 10 - 10 (1 bit)

SDIOSuspend : SDIOSuspend
bits : 11 - 11 (1 bit)

ENCMDcompl : ENCMDcompl
bits : 12 - 12 (1 bit)

nIEN : nIEN
bits : 13 - 13 (1 bit)

CE_ATACMD : CE_ATACMD
bits : 14 - 14 (1 bit)



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