\n
address_offset : 0x0 Bytes (0x0)
size : 0x100000 byte (0x0)
mem_usage : registers
protection : not protected
Cache ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Cache Controller ID
bits : 0 - 31 (32 bit)
access : read-only
Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L2CEN : L2 Cache Enable
bits : 0 - 0 (1 bit)
access : read-write
Auxiliary Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPSO : High Priority for SO and Dev Reads Enable
bits : 10 - 10 (1 bit)
access : read-write
SBDLE : Store Buffer Device Limitation Enable
bits : 11 - 11 (1 bit)
access : read-write
EXCC : Exclusive Cache Configuration
bits : 12 - 12 (1 bit)
access : read-write
SAIE : Shared Attribute Invalidate Enable
bits : 13 - 13 (1 bit)
access : read-write
ASS : Associativity
bits : 16 - 16 (1 bit)
access : read-write
WAYSIZE : Way Size
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
0x1 : 16KB_WAY
16-Kbyte way set associative
End of enumeration elements list.
EMBEN : Event Monitor Bus Enable
bits : 20 - 20 (1 bit)
access : read-write
PEN : Parity Enable
bits : 21 - 21 (1 bit)
access : read-write
SAOEN : Shared Attribute Override Enable
bits : 22 - 22 (1 bit)
access : read-write
FWA : Force Write Allocate
bits : 23 - 24 (2 bit)
access : read-write
CRPOL : Cache Replacement Policy
bits : 25 - 25 (1 bit)
access : read-write
NSLEN : Non-Secure Lockdown Enable
bits : 26 - 26 (1 bit)
access : read-write
NSIAC : Non-Secure Interrupt Access Control
bits : 27 - 27 (1 bit)
access : read-write
DPEN : Data Prefetch Enable
bits : 28 - 28 (1 bit)
access : read-write
IPEN : Instruction Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write
Tag RAM Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSETLAT : Setup Latency
bits : 0 - 2 (3 bit)
access : read-write
TRDLAT : Read Access Latency
bits : 4 - 6 (3 bit)
access : read-write
TWRLAT : Write Access Latency
bits : 8 - 10 (3 bit)
access : read-write
Data RAM Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSETLAT : Setup Latency
bits : 0 - 2 (3 bit)
access : read-write
DRDLAT : Read Access Latency
bits : 4 - 6 (3 bit)
access : read-write
DWRLAT : Write Access Latency
bits : 8 - 10 (3 bit)
access : read-write
Event Counter Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVCEN : Event Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
EVC0RST : Event Counter 0 Reset
bits : 1 - 1 (1 bit)
access : read-write
EVC1RST : Event Counter 1 Reset
bits : 2 - 2 (1 bit)
access : read-write
Event Counter 1 Configuration Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIGEN : Event Counter Interrupt Generation
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : INT_DIS
Disables (default)
0x1 : INT_EN_INCR
Enables with Increment condition
0x2 : INT_EN_OVER
Enables with Overflow condition
0x3 : INT_GEN_DIS
Disables Interrupt generation
End of enumeration elements list.
ESRC : Event Counter Source
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0x0 : CNT_DIS
Counter Disabled
0x1 : SRC_CO
Source is CO
0x2 : SRC_DRHIT
Source is DRHIT
0x3 : SRC_DRREQ
Source is DRREQ
0x4 : SRC_DWHIT
Source is DWHIT
0x5 : SRC_DWREQ
Source is DWREQ
0x6 : SRC_DWTREQ
Source is DWTREQ
0x7 : SRC_IRHIT
Source is IRHIT
0x8 : SRC_IRREQ
Source is IRREQ
0x9 : SRC_WA
Source is WA
0xa : SRC_IPFALLOC
Source is IPFALLOC
0xb : SRC_EPFHIT
Source is EPFHIT
0xc : SRC_EPFALLOC
Source is EPFALLOC
0xd : SRC_SRRCVD
Source is SRRCVD
0xe : SRC_SRCONF
Source is SRCONF
0xf : SRC_EPFRCVD
Source is EPFRCVD
End of enumeration elements list.
Event Counter 0 Configuration Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIGEN : Event Counter Interrupt Generation
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : INT_DIS
Disables (default)
0x1 : INT_EN_INCR
Enables with Increment condition
0x2 : INT_EN_OVER
Enables with Overflow condition
0x3 : INT_GEN_DIS
Disables Interrupt generation
End of enumeration elements list.
ESRC : Event Counter Source
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
0x0 : CNT_DIS
Counter Disabled
0x1 : SRC_CO
Source is CO
0x2 : SRC_DRHIT
Source is DRHIT
0x3 : SRC_DRREQ
Source is DRREQ
0x4 : SRC_DWHIT
Source is DWHIT
0x5 : SRC_DWREQ
Source is DWREQ
0x6 : SRC_DWTREQ
Source is DWTREQ
0x7 : SRC_IRHIT
Source is IRHIT
0x8 : SRC_IRREQ
Source is IRREQ
0x9 : SRC_WA
Source is WA
0xa : SRC_IPFALLOC
Source is IPFALLOC
0xb : SRC_EPFHIT
Source is EPFHIT
0xc : SRC_EPFALLOC
Source is EPFALLOC
0xd : SRC_SRRCVD
Source is SRRCVD
0xe : SRC_SRCONF
Source is SRCONF
0xf : SRC_EPFRCVD
Source is EPFRCVD
End of enumeration elements list.
Event Counter 1 Value Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Event Counter Value
bits : 0 - 31 (32 bit)
access : read-write
Event Counter 0 Value Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Event Counter Value
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECNTR : Event Counter 1/0 Overflow Increment
bits : 0 - 0 (1 bit)
access : read-write
PARRT : Parity Error on L2 Tag RAM, Read
bits : 1 - 1 (1 bit)
access : read-write
PARRD : Parity Error on L2 Data RAM, Read
bits : 2 - 2 (1 bit)
access : read-write
ERRWT : Error on L2 Tag RAM, Write
bits : 3 - 3 (1 bit)
access : read-write
ERRWD : Error on L2 Data RAM, Write
bits : 4 - 4 (1 bit)
access : read-write
ERRRT : Error on L2 Tag RAM, Read
bits : 5 - 5 (1 bit)
access : read-write
ERRRD : Error on L2 Data RAM, Read
bits : 6 - 6 (1 bit)
access : read-write
SLVERR : SLVERR from L3 Memory
bits : 7 - 7 (1 bit)
access : read-write
DECERR : DECERR from L3 Memory
bits : 8 - 8 (1 bit)
access : read-write
Masked Interrupt Status Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECNTR : Event Counter 1/0 Overflow Increment
bits : 0 - 0 (1 bit)
access : read-only
PARRT : Parity Error on L2 Tag RAM, Read
bits : 1 - 1 (1 bit)
access : read-only
PARRD : Parity Error on L2 Data RAM, Read
bits : 2 - 2 (1 bit)
access : read-only
ERRWT : Error on L2 Tag RAM, Write
bits : 3 - 3 (1 bit)
access : read-only
ERRWD : Error on L2 Data RAM, Write
bits : 4 - 4 (1 bit)
access : read-only
ERRRT : Error on L2 Tag RAM, Read
bits : 5 - 5 (1 bit)
access : read-only
ERRRD : Error on L2 Data RAM, Read
bits : 6 - 6 (1 bit)
access : read-only
SLVERR : SLVERR from L3 memory
bits : 7 - 7 (1 bit)
access : read-only
DECERR : DECERR from L3 memory
bits : 8 - 8 (1 bit)
access : read-only
Raw Interrupt Status Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECNTR : Event Counter 1/0 Overflow Increment
bits : 0 - 0 (1 bit)
access : read-only
PARRT : Parity Error on L2 Tag RAM, Read
bits : 1 - 1 (1 bit)
access : read-only
PARRD : Parity Error on L2 Data RAM, Read
bits : 2 - 2 (1 bit)
access : read-only
ERRWT : Error on L2 Tag RAM, Write
bits : 3 - 3 (1 bit)
access : read-only
ERRWD : Error on L2 Data RAM, Write
bits : 4 - 4 (1 bit)
access : read-only
ERRRT : Error on L2 Tag RAM, Read
bits : 5 - 5 (1 bit)
access : read-only
ERRRD : Error on L2 Data RAM, Read
bits : 6 - 6 (1 bit)
access : read-only
SLVERR : SLVERR from L3 memory
bits : 7 - 7 (1 bit)
access : read-only
DECERR : DECERR from L3 memory
bits : 8 - 8 (1 bit)
access : read-only
Interrupt Clear Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECNTR : Event Counter 1/0 Overflow Increment
bits : 0 - 0 (1 bit)
access : read-write
PARRT : Parity Error on L2 Tag RAM, Read
bits : 1 - 1 (1 bit)
access : read-write
PARRD : Parity Error on L2 Data RAM, Read
bits : 2 - 2 (1 bit)
access : read-write
ERRWT : Error on L2 Tag RAM, Write
bits : 3 - 3 (1 bit)
access : read-write
ERRWD : Error on L2 Data RAM, Write
bits : 4 - 4 (1 bit)
access : read-write
ERRRT : Error on L2 Tag RAM, Read
bits : 5 - 5 (1 bit)
access : read-write
ERRRD : Error on L2 Data RAM, Read
bits : 6 - 6 (1 bit)
access : read-write
SLVERR : SLVERR from L3 memory
bits : 7 - 7 (1 bit)
access : read-write
DECERR : DECERR from L3 memory
bits : 8 - 8 (1 bit)
access : read-write
Cache Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IL2ASS : Instruction L2 Cache Associativity
bits : 6 - 6 (1 bit)
access : read-only
IL2WSIZE : Instruction L2 Cache Way Size
bits : 8 - 10 (3 bit)
access : read-only
DL2ASS : Data L2 Cache Associativity
bits : 18 - 18 (1 bit)
access : read-only
DL2WSIZE : Data L2 Cache Way Size
bits : 20 - 22 (3 bit)
access : read-only
Cache Synchronization Register
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
Invalidate Physical Address Line Register
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
IDX : Index Number
bits : 5 - 13 (9 bit)
access : read-write
TAG : Tag Number
bits : 14 - 31 (18 bit)
access : read-write
Invalidate Way Register
address_offset : 0x77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY0 : Invalidate Way Number 0
bits : 0 - 0 (1 bit)
access : read-write
WAY1 : Invalidate Way Number 1
bits : 1 - 1 (1 bit)
access : read-write
WAY2 : Invalidate Way Number 2
bits : 2 - 2 (1 bit)
access : read-write
WAY3 : Invalidate Way Number 3
bits : 3 - 3 (1 bit)
access : read-write
WAY4 : Invalidate Way Number 4
bits : 4 - 4 (1 bit)
access : read-write
WAY5 : Invalidate Way Number 5
bits : 5 - 5 (1 bit)
access : read-write
WAY6 : Invalidate Way Number 6
bits : 6 - 6 (1 bit)
access : read-write
WAY7 : Invalidate Way Number 7
bits : 7 - 7 (1 bit)
access : read-write
Clean Physical Address Line Register
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
IDX : Index number
bits : 5 - 13 (9 bit)
access : read-write
TAG : Tag number
bits : 14 - 31 (18 bit)
access : read-write
Clean Index Register
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
IDX : Index number
bits : 5 - 13 (9 bit)
access : read-write
WAY : Way number
bits : 28 - 30 (3 bit)
access : read-write
Clean Way Register
address_offset : 0x7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY0 : Clean Way Number 0
bits : 0 - 0 (1 bit)
access : read-write
WAY1 : Clean Way Number 1
bits : 1 - 1 (1 bit)
access : read-write
WAY2 : Clean Way Number 2
bits : 2 - 2 (1 bit)
access : read-write
WAY3 : Clean Way Number 3
bits : 3 - 3 (1 bit)
access : read-write
WAY4 : Clean Way Number 4
bits : 4 - 4 (1 bit)
access : read-write
WAY5 : Clean Way Number 5
bits : 5 - 5 (1 bit)
access : read-write
WAY6 : Clean Way Number 6
bits : 6 - 6 (1 bit)
access : read-write
WAY7 : Clean Way Number 7
bits : 7 - 7 (1 bit)
access : read-write
Clean Invalidate Physical Address Line Register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
IDX : Index Number
bits : 5 - 13 (9 bit)
access : read-write
TAG : Tag Number
bits : 14 - 31 (18 bit)
access : read-write
Clean Invalidate Index Register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C : Cache Synchronization Status
bits : 0 - 0 (1 bit)
access : read-write
IDX : Index Number
bits : 5 - 13 (9 bit)
access : read-write
WAY : Way Number
bits : 28 - 30 (3 bit)
access : read-write
Clean Invalidate Way Register
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAY0 : Clean Invalidate Way Number 0
bits : 0 - 0 (1 bit)
access : read-write
WAY1 : Clean Invalidate Way Number 1
bits : 1 - 1 (1 bit)
access : read-write
WAY2 : Clean Invalidate Way Number 2
bits : 2 - 2 (1 bit)
access : read-write
WAY3 : Clean Invalidate Way Number 3
bits : 3 - 3 (1 bit)
access : read-write
WAY4 : Clean Invalidate Way Number 4
bits : 4 - 4 (1 bit)
access : read-write
WAY5 : Clean Invalidate Way Number 5
bits : 5 - 5 (1 bit)
access : read-write
WAY6 : Clean Invalidate Way Number 6
bits : 6 - 6 (1 bit)
access : read-write
WAY7 : Clean Invalidate Way Number 7
bits : 7 - 7 (1 bit)
access : read-write
Data Lockdown Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLK0 : Data Lockdown in Way Number 0
bits : 0 - 0 (1 bit)
access : read-write
DLK1 : Data Lockdown in Way Number 1
bits : 1 - 1 (1 bit)
access : read-write
DLK2 : Data Lockdown in Way Number 2
bits : 2 - 2 (1 bit)
access : read-write
DLK3 : Data Lockdown in Way Number 3
bits : 3 - 3 (1 bit)
access : read-write
DLK4 : Data Lockdown in Way Number 4
bits : 4 - 4 (1 bit)
access : read-write
DLK5 : Data Lockdown in Way Number 5
bits : 5 - 5 (1 bit)
access : read-write
DLK6 : Data Lockdown in Way Number 6
bits : 6 - 6 (1 bit)
access : read-write
DLK7 : Data Lockdown in Way Number 7
bits : 7 - 7 (1 bit)
access : read-write
Instruction Lockdown Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILK0 : Instruction Lockdown in Way Number 0
bits : 0 - 0 (1 bit)
access : read-write
ILK1 : Instruction Lockdown in Way Number 1
bits : 1 - 1 (1 bit)
access : read-write
ILK2 : Instruction Lockdown in Way Number 2
bits : 2 - 2 (1 bit)
access : read-write
ILK3 : Instruction Lockdown in Way Number 3
bits : 3 - 3 (1 bit)
access : read-write
ILK4 : Instruction Lockdown in Way Number 4
bits : 4 - 4 (1 bit)
access : read-write
ILK5 : Instruction Lockdown in Way Number 5
bits : 5 - 5 (1 bit)
access : read-write
ILK6 : Instruction Lockdown in Way Number 6
bits : 6 - 6 (1 bit)
access : read-write
ILK7 : Instruction Lockdown in Way Number 7
bits : 7 - 7 (1 bit)
access : read-write
Debug Control Register
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCL : Disable Cache Linefill
bits : 0 - 0 (1 bit)
access : read-write
DWB : Disable Write-back, Force Write-through
bits : 1 - 1 (1 bit)
access : read-write
SPNIDEN : SPNIDEN Value
bits : 2 - 2 (1 bit)
access : read-write
Prefetch Control Register
address_offset : 0xF60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Prefetch Offset
bits : 0 - 4 (5 bit)
access : read-write
NSIDEN : Not Same ID on Exclusive Sequence Enable
bits : 21 - 21 (1 bit)
access : read-write
IDLEN : INCR Double Linefill Enable
bits : 23 - 23 (1 bit)
access : read-write
PDEN : Prefetch Drop Enable
bits : 24 - 24 (1 bit)
access : read-write
DLFWRDIS : Double Linefill on WRAP Read Disable
bits : 27 - 27 (1 bit)
access : read-write
DATPEN : Data Prefetch Enable
bits : 28 - 28 (1 bit)
access : read-write
INSPEN : Instruction Prefetch Enable
bits : 29 - 29 (1 bit)
access : read-write
DLEN : Double Linefill Enable
bits : 30 - 30 (1 bit)
access : read-write
Power Control Register
address_offset : 0xF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBYEN : Standby Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
DCKGATEN : Dynamic Clock Gating Enable
bits : 1 - 1 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.