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XDMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GTYPE

GID

CSUS2

CDUS2

CIE3

CID3

CIM3

CIS3

CSA3

CDA3

CNDA3

CNDC3

CUBC3

CBC3

CC3

CDS_MSP3

GIM

CSUS3

CDUS3

CIE4

CID4

CIM4

CIS4

CSA4

CDA4

CNDA4

CNDC4

CUBC4

CBC4

CC4

CDS_MSP4

GIS

CSUS4

CDUS4

CIE5

CID5

CIM5

CIS5

CSA5

CDA5

CNDA5

CNDC5

CUBC5

CBC5

CC5

CDS_MSP5

GE

CSUS5

CDUS5

CIE6

CID6

CIM6

CIS6

CSA6

CDA6

CNDA6

CNDC6

CUBC6

CBC6

CC6

CDS_MSP6

GD

CSUS6

CDUS6

CIE7

CID7

CIM7

CIS7

CSA7

CDA7

CNDA7

CNDC7

CUBC7

CBC7

CC7

CDS_MSP7

GS

CSUS7

CDUS7

CIE8

CID8

CIM8

CIS8

CSA8

CDA8

CNDA8

CNDC8

CUBC8

CBC8

CC8

CDS_MSP8

GRS

CSUS8

CDUS8

CIE9

CID9

CIM9

CIS9

CSA9

CDA9

CNDA9

CNDC9

CUBC9

CBC9

CC9

CDS_MSP9

GWS

CSUS9

CDUS9

CIE10

CID10

CIM10

CIS10

CSA10

CDA10

CNDA10

CNDC10

CUBC10

CBC10

CC10

CDS_MSP10

GRWS

CSUS10

CDUS10

CIE11

CID11

CIM11

CIS11

CSA11

CDA11

CNDA11

CNDC11

CUBC11

CBC11

CC11

CDS_MSP11

GRWR

CSUS11

CDUS11

CIE12

CID12

CIM12

CIS12

CSA12

CDA12

CNDA12

CNDC12

CUBC12

CBC12

CC12

CDS_MSP12

GSWR

CSUS12

CDUS12

CIE13

CID13

CIM13

CIS13

CSA13

CDA13

CNDA13

CNDC13

CUBC13

CBC13

CC13

CDS_MSP13

GSWS

CSUS13

CDUS13

CIE14

CID14

CIM14

CIS14

CSA14

CDA14

CNDA14

CNDC14

CUBC14

CBC14

CC14

CDS_MSP14

GCFG

GSWF

CSUS14

CDUS14

CIE15

CID15

CIM15

CIS15

CSA15

CDA15

CNDA15

CNDC15

CUBC15

CBC15

CC15

CDS_MSP15

CSUS15

CDUS15

CIE0

CID0

CIM0

CIS0

CSA0

CDA0

CNDA0

CNDC0

CUBC0

CBC0

CC0

CDS_MSP0

GWAC

CSUS0

CDUS0

CIE1

CID1

CIM1

CIS1

CSA1

CDA1

CNDA1

CNDC1

CUBC1

CBC1

CC1

CDS_MSP1

GIE

CSUS1

CDUS1

CIE2

CID2

CIM2

CIS2

CSA2

CDA2

CNDA2

CNDC2

CUBC2

CBC2

CC2

CDS_MSP2


GTYPE

Global Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GTYPE GTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NB_CH FIFO_SZ NB_REQ

NB_CH : Number of Channels Minus One
bits : 0 - 4 (5 bit)
access : read-only

FIFO_SZ : Number of Bytes
bits : 5 - 15 (11 bit)
access : read-only

NB_REQ : Number of Peripheral Requests Minus One
bits : 16 - 22 (7 bit)
access : read-only


GID

Global Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GID GID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15

ID0 : XDMAC Channel 0 Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

ID1 : XDMAC Channel 1 Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

ID2 : XDMAC Channel 2 Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

ID3 : XDMAC Channel 3 Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

ID4 : XDMAC Channel 4 Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

ID5 : XDMAC Channel 5 Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ID6 : XDMAC Channel 6 Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

ID7 : XDMAC Channel 7 Interrupt Disable Bit
bits : 7 - 7 (1 bit)
access : write-only

ID8 : XDMAC Channel 8 Interrupt Disable Bit
bits : 8 - 8 (1 bit)
access : write-only

ID9 : XDMAC Channel 9 Interrupt Disable Bit
bits : 9 - 9 (1 bit)
access : write-only

ID10 : XDMAC Channel 10 Interrupt Disable Bit
bits : 10 - 10 (1 bit)
access : write-only

ID11 : XDMAC Channel 11 Interrupt Disable Bit
bits : 11 - 11 (1 bit)
access : write-only

ID12 : XDMAC Channel 12 Interrupt Disable Bit
bits : 12 - 12 (1 bit)
access : write-only

ID13 : XDMAC Channel 13 Interrupt Disable Bit
bits : 13 - 13 (1 bit)
access : write-only

ID14 : XDMAC Channel 14 Interrupt Disable Bit
bits : 14 - 14 (1 bit)
access : write-only

ID15 : XDMAC Channel 15 Interrupt Disable Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS2

Channel Source Microblock Stride (chid = 2)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS2 CSUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS2

Channel Destination Microblock Stride (chid = 2)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS2 CDUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE3

Channel Interrupt Enable Register (chid = 3)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE3 CIE3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID3

Channel Interrupt Disable Register (chid = 3)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM3

Channel Interrupt Mask Register (chid = 3)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM3 CIM3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS3

Channel Interrupt Status Register (chid = 3)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS3 CIS3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA3

Channel Source Address Register (chid = 3)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA3 CSA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA3

Channel Destination Address Register (chid = 3)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA3 CDA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA3

Channel Next Descriptor Address Register (chid = 3)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA3 CNDA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC3

Channel Next Descriptor Control Register (chid = 3)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC3 CNDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC3

Channel Microblock Control Register (chid = 3)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC3 CUBC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC3

Channel Block Control Register (chid = 3)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC3 CBC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC3

Channel Configuration Register (chid = 3)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC3 CC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP3

Channel Data Stride Memory Set Pattern (chid = 3)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP3 CDS_MSP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GIM

Global Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIM GIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15

IM0 : XDMAC Channel 0 Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

IM1 : XDMAC Channel 1 Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

IM2 : XDMAC Channel 2 Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

IM3 : XDMAC Channel 3 Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

IM4 : XDMAC Channel 4 Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

IM5 : XDMAC Channel 5 Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

IM6 : XDMAC Channel 6 Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only

IM7 : XDMAC Channel 7 Interrupt Mask Bit
bits : 7 - 7 (1 bit)
access : read-only

IM8 : XDMAC Channel 8 Interrupt Mask Bit
bits : 8 - 8 (1 bit)
access : read-only

IM9 : XDMAC Channel 9 Interrupt Mask Bit
bits : 9 - 9 (1 bit)
access : read-only

IM10 : XDMAC Channel 10 Interrupt Mask Bit
bits : 10 - 10 (1 bit)
access : read-only

IM11 : XDMAC Channel 11 Interrupt Mask Bit
bits : 11 - 11 (1 bit)
access : read-only

IM12 : XDMAC Channel 12 Interrupt Mask Bit
bits : 12 - 12 (1 bit)
access : read-only

IM13 : XDMAC Channel 13 Interrupt Mask Bit
bits : 13 - 13 (1 bit)
access : read-only

IM14 : XDMAC Channel 14 Interrupt Mask Bit
bits : 14 - 14 (1 bit)
access : read-only

IM15 : XDMAC Channel 15 Interrupt Mask Bit
bits : 15 - 15 (1 bit)
access : read-only


CSUS3

Channel Source Microblock Stride (chid = 3)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS3 CSUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS3

Channel Destination Microblock Stride (chid = 3)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS3 CDUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE4

Channel Interrupt Enable Register (chid = 4)
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE4 CIE4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID4

Channel Interrupt Disable Register (chid = 4)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID4 CID4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM4

Channel Interrupt Mask Register (chid = 4)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM4 CIM4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS4

Channel Interrupt Status Register (chid = 4)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS4 CIS4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA4

Channel Source Address Register (chid = 4)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA4 CSA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA4

Channel Destination Address Register (chid = 4)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA4 CDA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA4

Channel Next Descriptor Address Register (chid = 4)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA4 CNDA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC4

Channel Next Descriptor Control Register (chid = 4)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC4 CNDC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC4

Channel Microblock Control Register (chid = 4)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC4 CUBC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC4

Channel Block Control Register (chid = 4)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC4 CBC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC4

Channel Configuration Register (chid = 4)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC4 CC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP4

Channel Data Stride Memory Set Pattern (chid = 4)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP4 CDS_MSP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GIS

Global Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIS GIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IS0 IS1 IS2 IS3 IS4 IS5 IS6 IS7 IS8 IS9 IS10 IS11 IS12 IS13 IS14 IS15

IS0 : XDMAC Channel 0 Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

IS1 : XDMAC Channel 1 Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

IS2 : XDMAC Channel 2 Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

IS3 : XDMAC Channel 3 Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

IS4 : XDMAC Channel 4 Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

IS5 : XDMAC Channel 5 Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

IS6 : XDMAC Channel 6 Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only

IS7 : XDMAC Channel 7 Interrupt Status Bit
bits : 7 - 7 (1 bit)
access : read-only

IS8 : XDMAC Channel 8 Interrupt Status Bit
bits : 8 - 8 (1 bit)
access : read-only

IS9 : XDMAC Channel 9 Interrupt Status Bit
bits : 9 - 9 (1 bit)
access : read-only

IS10 : XDMAC Channel 10 Interrupt Status Bit
bits : 10 - 10 (1 bit)
access : read-only

IS11 : XDMAC Channel 11 Interrupt Status Bit
bits : 11 - 11 (1 bit)
access : read-only

IS12 : XDMAC Channel 12 Interrupt Status Bit
bits : 12 - 12 (1 bit)
access : read-only

IS13 : XDMAC Channel 13 Interrupt Status Bit
bits : 13 - 13 (1 bit)
access : read-only

IS14 : XDMAC Channel 14 Interrupt Status Bit
bits : 14 - 14 (1 bit)
access : read-only

IS15 : XDMAC Channel 15 Interrupt Status Bit
bits : 15 - 15 (1 bit)
access : read-only


CSUS4

Channel Source Microblock Stride (chid = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS4 CSUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS4

Channel Destination Microblock Stride (chid = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS4 CDUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE5

Channel Interrupt Enable Register (chid = 5)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE5 CIE5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID5

Channel Interrupt Disable Register (chid = 5)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID5 CID5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM5

Channel Interrupt Mask Register (chid = 5)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM5 CIM5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS5

Channel Interrupt Status Register (chid = 5)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS5 CIS5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA5

Channel Source Address Register (chid = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA5 CSA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA5

Channel Destination Address Register (chid = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA5 CDA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA5

Channel Next Descriptor Address Register (chid = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA5 CNDA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC5

Channel Next Descriptor Control Register (chid = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC5 CNDC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC5

Channel Microblock Control Register (chid = 5)
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC5 CUBC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC5

Channel Block Control Register (chid = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC5 CBC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC5

Channel Configuration Register (chid = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC5 CC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP5

Channel Data Stride Memory Set Pattern (chid = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP5 CDS_MSP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GE

Global Channel Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GE GE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN9 EN10 EN11 EN12 EN13 EN14 EN15

EN0 : XDMAC Channel 0 Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

EN1 : XDMAC Channel 1 Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

EN2 : XDMAC Channel 2 Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

EN3 : XDMAC Channel 3 Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

EN4 : XDMAC Channel 4 Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

EN5 : XDMAC Channel 5 Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

EN6 : XDMAC Channel 6 Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

EN7 : XDMAC Channel 7 Enable Bit
bits : 7 - 7 (1 bit)
access : write-only

EN8 : XDMAC Channel 8 Enable Bit
bits : 8 - 8 (1 bit)
access : write-only

EN9 : XDMAC Channel 9 Enable Bit
bits : 9 - 9 (1 bit)
access : write-only

EN10 : XDMAC Channel 10 Enable Bit
bits : 10 - 10 (1 bit)
access : write-only

EN11 : XDMAC Channel 11 Enable Bit
bits : 11 - 11 (1 bit)
access : write-only

EN12 : XDMAC Channel 12 Enable Bit
bits : 12 - 12 (1 bit)
access : write-only

EN13 : XDMAC Channel 13 Enable Bit
bits : 13 - 13 (1 bit)
access : write-only

EN14 : XDMAC Channel 14 Enable Bit
bits : 14 - 14 (1 bit)
access : write-only

EN15 : XDMAC Channel 15 Enable Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS5

Channel Source Microblock Stride (chid = 5)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS5 CSUS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS5

Channel Destination Microblock Stride (chid = 5)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS5 CDUS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE6

Channel Interrupt Enable Register (chid = 6)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE6 CIE6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID6

Channel Interrupt Disable Register (chid = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID6 CID6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM6

Channel Interrupt Mask Register (chid = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM6 CIM6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS6

Channel Interrupt Status Register (chid = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS6 CIS6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA6

Channel Source Address Register (chid = 6)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA6 CSA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA6

Channel Destination Address Register (chid = 6)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA6 CDA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA6

Channel Next Descriptor Address Register (chid = 6)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA6 CNDA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC6

Channel Next Descriptor Control Register (chid = 6)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC6 CNDC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC6

Channel Microblock Control Register (chid = 6)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC6 CUBC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC6

Channel Block Control Register (chid = 6)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC6 CBC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC6

Channel Configuration Register (chid = 6)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC6 CC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP6

Channel Data Stride Memory Set Pattern (chid = 6)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP6 CDS_MSP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GD

Global Channel Disable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GD GD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15

DI0 : XDMAC Channel 0 Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

DI1 : XDMAC Channel 1 Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DI2 : XDMAC Channel 2 Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

DI3 : XDMAC Channel 3 Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

DI4 : XDMAC Channel 4 Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

DI5 : XDMAC Channel 5 Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

DI6 : XDMAC Channel 6 Disable Bit
bits : 6 - 6 (1 bit)
access : write-only

DI7 : XDMAC Channel 7 Disable Bit
bits : 7 - 7 (1 bit)
access : write-only

DI8 : XDMAC Channel 8 Disable Bit
bits : 8 - 8 (1 bit)
access : write-only

DI9 : XDMAC Channel 9 Disable Bit
bits : 9 - 9 (1 bit)
access : write-only

DI10 : XDMAC Channel 10 Disable Bit
bits : 10 - 10 (1 bit)
access : write-only

DI11 : XDMAC Channel 11 Disable Bit
bits : 11 - 11 (1 bit)
access : write-only

DI12 : XDMAC Channel 12 Disable Bit
bits : 12 - 12 (1 bit)
access : write-only

DI13 : XDMAC Channel 13 Disable Bit
bits : 13 - 13 (1 bit)
access : write-only

DI14 : XDMAC Channel 14 Disable Bit
bits : 14 - 14 (1 bit)
access : write-only

DI15 : XDMAC Channel 15 Disable Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS6

Channel Source Microblock Stride (chid = 6)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS6 CSUS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS6

Channel Destination Microblock Stride (chid = 6)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS6 CDUS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE7

Channel Interrupt Enable Register (chid = 7)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE7 CIE7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID7

Channel Interrupt Disable Register (chid = 7)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID7 CID7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM7

Channel Interrupt Mask Register (chid = 7)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM7 CIM7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS7

Channel Interrupt Status Register (chid = 7)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS7 CIS7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA7

Channel Source Address Register (chid = 7)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA7 CSA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA7

Channel Destination Address Register (chid = 7)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA7 CDA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA7

Channel Next Descriptor Address Register (chid = 7)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA7 CNDA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC7

Channel Next Descriptor Control Register (chid = 7)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC7 CNDC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC7

Channel Microblock Control Register (chid = 7)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC7 CUBC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC7

Channel Block Control Register (chid = 7)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC7 CBC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC7

Channel Configuration Register (chid = 7)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC7 CC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP7

Channel Data Stride Memory Set Pattern (chid = 7)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP7 CDS_MSP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GS

Global Channel Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GS GS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ST8 ST9 ST10 ST11 ST12 ST13 ST14 ST15

ST0 : XDMAC Channel 0 Status Bit
bits : 0 - 0 (1 bit)
access : read-only

ST1 : XDMAC Channel 1 Status Bit
bits : 1 - 1 (1 bit)
access : read-only

ST2 : XDMAC Channel 2 Status Bit
bits : 2 - 2 (1 bit)
access : read-only

ST3 : XDMAC Channel 3 Status Bit
bits : 3 - 3 (1 bit)
access : read-only

ST4 : XDMAC Channel 4 Status Bit
bits : 4 - 4 (1 bit)
access : read-only

ST5 : XDMAC Channel 5 Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ST6 : XDMAC Channel 6 Status Bit
bits : 6 - 6 (1 bit)
access : read-only

ST7 : XDMAC Channel 7 Status Bit
bits : 7 - 7 (1 bit)
access : read-only

ST8 : XDMAC Channel 8 Status Bit
bits : 8 - 8 (1 bit)
access : read-only

ST9 : XDMAC Channel 9 Status Bit
bits : 9 - 9 (1 bit)
access : read-only

ST10 : XDMAC Channel 10 Status Bit
bits : 10 - 10 (1 bit)
access : read-only

ST11 : XDMAC Channel 11 Status Bit
bits : 11 - 11 (1 bit)
access : read-only

ST12 : XDMAC Channel 12 Status Bit
bits : 12 - 12 (1 bit)
access : read-only

ST13 : XDMAC Channel 13 Status Bit
bits : 13 - 13 (1 bit)
access : read-only

ST14 : XDMAC Channel 14 Status Bit
bits : 14 - 14 (1 bit)
access : read-only

ST15 : XDMAC Channel 15 Status Bit
bits : 15 - 15 (1 bit)
access : read-only


CSUS7

Channel Source Microblock Stride (chid = 7)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS7 CSUS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS7

Channel Destination Microblock Stride (chid = 7)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS7 CDUS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE8

Channel Interrupt Enable Register (chid = 8)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE8 CIE8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID8

Channel Interrupt Disable Register (chid = 8)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID8 CID8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM8

Channel Interrupt Mask Register (chid = 8)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM8 CIM8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS8

Channel Interrupt Status Register (chid = 8)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS8 CIS8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA8

Channel Source Address Register (chid = 8)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA8 CSA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA8

Channel Destination Address Register (chid = 8)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA8 CDA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA8

Channel Next Descriptor Address Register (chid = 8)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA8 CNDA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC8

Channel Next Descriptor Control Register (chid = 8)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC8 CNDC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC8

Channel Microblock Control Register (chid = 8)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC8 CUBC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC8

Channel Block Control Register (chid = 8)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC8 CBC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC8

Channel Configuration Register (chid = 8)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC8 CC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP8

Channel Data Stride Memory Set Pattern (chid = 8)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP8 CDS_MSP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRS

Global Channel Read Suspend Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRS GRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15

RS0 : XDMAC Channel 0 Read Suspend Bit
bits : 0 - 0 (1 bit)
access : read-write

RS1 : XDMAC Channel 1 Read Suspend Bit
bits : 1 - 1 (1 bit)
access : read-write

RS2 : XDMAC Channel 2 Read Suspend Bit
bits : 2 - 2 (1 bit)
access : read-write

RS3 : XDMAC Channel 3 Read Suspend Bit
bits : 3 - 3 (1 bit)
access : read-write

RS4 : XDMAC Channel 4 Read Suspend Bit
bits : 4 - 4 (1 bit)
access : read-write

RS5 : XDMAC Channel 5 Read Suspend Bit
bits : 5 - 5 (1 bit)
access : read-write

RS6 : XDMAC Channel 6 Read Suspend Bit
bits : 6 - 6 (1 bit)
access : read-write

RS7 : XDMAC Channel 7 Read Suspend Bit
bits : 7 - 7 (1 bit)
access : read-write

RS8 : XDMAC Channel 8 Read Suspend Bit
bits : 8 - 8 (1 bit)
access : read-write

RS9 : XDMAC Channel 9 Read Suspend Bit
bits : 9 - 9 (1 bit)
access : read-write

RS10 : XDMAC Channel 10 Read Suspend Bit
bits : 10 - 10 (1 bit)
access : read-write

RS11 : XDMAC Channel 11 Read Suspend Bit
bits : 11 - 11 (1 bit)
access : read-write

RS12 : XDMAC Channel 12 Read Suspend Bit
bits : 12 - 12 (1 bit)
access : read-write

RS13 : XDMAC Channel 13 Read Suspend Bit
bits : 13 - 13 (1 bit)
access : read-write

RS14 : XDMAC Channel 14 Read Suspend Bit
bits : 14 - 14 (1 bit)
access : read-write

RS15 : XDMAC Channel 15 Read Suspend Bit
bits : 15 - 15 (1 bit)
access : read-write


CSUS8

Channel Source Microblock Stride (chid = 8)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS8 CSUS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS8

Channel Destination Microblock Stride (chid = 8)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS8 CDUS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE9

Channel Interrupt Enable Register (chid = 9)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE9 CIE9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID9

Channel Interrupt Disable Register (chid = 9)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID9 CID9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM9

Channel Interrupt Mask Register (chid = 9)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM9 CIM9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS9

Channel Interrupt Status Register (chid = 9)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS9 CIS9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA9

Channel Source Address Register (chid = 9)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA9 CSA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA9

Channel Destination Address Register (chid = 9)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA9 CDA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA9

Channel Next Descriptor Address Register (chid = 9)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA9 CNDA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC9

Channel Next Descriptor Control Register (chid = 9)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC9 CNDC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC9

Channel Microblock Control Register (chid = 9)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC9 CUBC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC9

Channel Block Control Register (chid = 9)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC9 CBC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC9

Channel Configuration Register (chid = 9)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC9 CC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP9

Channel Data Stride Memory Set Pattern (chid = 9)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP9 CDS_MSP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GWS

Global Channel Write Suspend Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWS GWS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WS0 WS1 WS2 WS3 WS4 WS5 WS6 WS7 WS8 WS9 WS10 WS11 WS12 WS13 WS14 WS15

WS0 : XDMAC Channel 0 Write Suspend Bit
bits : 0 - 0 (1 bit)
access : read-write

WS1 : XDMAC Channel 1 Write Suspend Bit
bits : 1 - 1 (1 bit)
access : read-write

WS2 : XDMAC Channel 2 Write Suspend Bit
bits : 2 - 2 (1 bit)
access : read-write

WS3 : XDMAC Channel 3 Write Suspend Bit
bits : 3 - 3 (1 bit)
access : read-write

WS4 : XDMAC Channel 4 Write Suspend Bit
bits : 4 - 4 (1 bit)
access : read-write

WS5 : XDMAC Channel 5 Write Suspend Bit
bits : 5 - 5 (1 bit)
access : read-write

WS6 : XDMAC Channel 6 Write Suspend Bit
bits : 6 - 6 (1 bit)
access : read-write

WS7 : XDMAC Channel 7 Write Suspend Bit
bits : 7 - 7 (1 bit)
access : read-write

WS8 : XDMAC Channel 8 Write Suspend Bit
bits : 8 - 8 (1 bit)
access : read-write

WS9 : XDMAC Channel 9 Write Suspend Bit
bits : 9 - 9 (1 bit)
access : read-write

WS10 : XDMAC Channel 10 Write Suspend Bit
bits : 10 - 10 (1 bit)
access : read-write

WS11 : XDMAC Channel 11 Write Suspend Bit
bits : 11 - 11 (1 bit)
access : read-write

WS12 : XDMAC Channel 12 Write Suspend Bit
bits : 12 - 12 (1 bit)
access : read-write

WS13 : XDMAC Channel 13 Write Suspend Bit
bits : 13 - 13 (1 bit)
access : read-write

WS14 : XDMAC Channel 14 Write Suspend Bit
bits : 14 - 14 (1 bit)
access : read-write

WS15 : XDMAC Channel 15 Write Suspend Bit
bits : 15 - 15 (1 bit)
access : read-write


CSUS9

Channel Source Microblock Stride (chid = 9)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS9 CSUS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS9

Channel Destination Microblock Stride (chid = 9)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS9 CDUS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE10

Channel Interrupt Enable Register (chid = 10)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE10 CIE10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID10

Channel Interrupt Disable Register (chid = 10)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID10 CID10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM10

Channel Interrupt Mask Register (chid = 10)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM10 CIM10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS10

Channel Interrupt Status Register (chid = 10)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS10 CIS10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA10

Channel Source Address Register (chid = 10)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA10 CSA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA10

Channel Destination Address Register (chid = 10)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA10 CDA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA10

Channel Next Descriptor Address Register (chid = 10)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA10 CNDA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC10

Channel Next Descriptor Control Register (chid = 10)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC10 CNDC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC10

Channel Microblock Control Register (chid = 10)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC10 CUBC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC10

Channel Block Control Register (chid = 10)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC10 CBC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC10

Channel Configuration Register (chid = 10)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC10 CC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP10

Channel Data Stride Memory Set Pattern (chid = 10)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP10 CDS_MSP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRWS

Global Channel Read Write Suspend Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWS GRWS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWS0 RWS1 RWS2 RWS3 RWS4 RWS5 RWS6 RWS7 RWS8 RWS9 RWS10 RWS11 RWS12 RWS13 RWS14 RWS15

RWS0 : XDMAC Channel 0 Read Write Suspend Bit
bits : 0 - 0 (1 bit)
access : write-only

RWS1 : XDMAC Channel 1 Read Write Suspend Bit
bits : 1 - 1 (1 bit)
access : write-only

RWS2 : XDMAC Channel 2 Read Write Suspend Bit
bits : 2 - 2 (1 bit)
access : write-only

RWS3 : XDMAC Channel 3 Read Write Suspend Bit
bits : 3 - 3 (1 bit)
access : write-only

RWS4 : XDMAC Channel 4 Read Write Suspend Bit
bits : 4 - 4 (1 bit)
access : write-only

RWS5 : XDMAC Channel 5 Read Write Suspend Bit
bits : 5 - 5 (1 bit)
access : write-only

RWS6 : XDMAC Channel 6 Read Write Suspend Bit
bits : 6 - 6 (1 bit)
access : write-only

RWS7 : XDMAC Channel 7 Read Write Suspend Bit
bits : 7 - 7 (1 bit)
access : write-only

RWS8 : XDMAC Channel 8 Read Write Suspend Bit
bits : 8 - 8 (1 bit)
access : write-only

RWS9 : XDMAC Channel 9 Read Write Suspend Bit
bits : 9 - 9 (1 bit)
access : write-only

RWS10 : XDMAC Channel 10 Read Write Suspend Bit
bits : 10 - 10 (1 bit)
access : write-only

RWS11 : XDMAC Channel 11 Read Write Suspend Bit
bits : 11 - 11 (1 bit)
access : write-only

RWS12 : XDMAC Channel 12 Read Write Suspend Bit
bits : 12 - 12 (1 bit)
access : write-only

RWS13 : XDMAC Channel 13 Read Write Suspend Bit
bits : 13 - 13 (1 bit)
access : write-only

RWS14 : XDMAC Channel 14 Read Write Suspend Bit
bits : 14 - 14 (1 bit)
access : write-only

RWS15 : XDMAC Channel 15 Read Write Suspend Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS10

Channel Source Microblock Stride (chid = 10)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS10 CSUS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS10

Channel Destination Microblock Stride (chid = 10)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS10 CDUS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE11

Channel Interrupt Enable Register (chid = 11)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE11 CIE11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID11

Channel Interrupt Disable Register (chid = 11)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID11 CID11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM11

Channel Interrupt Mask Register (chid = 11)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM11 CIM11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS11

Channel Interrupt Status Register (chid = 11)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS11 CIS11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA11

Channel Source Address Register (chid = 11)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA11 CSA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA11

Channel Destination Address Register (chid = 11)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA11 CDA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA11

Channel Next Descriptor Address Register (chid = 11)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA11 CNDA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC11

Channel Next Descriptor Control Register (chid = 11)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC11 CNDC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC11

Channel Microblock Control Register (chid = 11)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC11 CUBC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC11

Channel Block Control Register (chid = 11)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC11 CBC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC11

Channel Configuration Register (chid = 11)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC11 CC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP11

Channel Data Stride Memory Set Pattern (chid = 11)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP11 CDS_MSP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRWR

Global Channel Read Write Resume Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWR GRWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWR0 RWR1 RWR2 RWR3 RWR4 RWR5 RWR6 RWR7 RWR8 RWR9 RWR10 RWR11 RWR12 RWR13 RWR14 RWR15

RWR0 : XDMAC Channel 0 Read Write Resume Bit
bits : 0 - 0 (1 bit)
access : write-only

RWR1 : XDMAC Channel 1 Read Write Resume Bit
bits : 1 - 1 (1 bit)
access : write-only

RWR2 : XDMAC Channel 2 Read Write Resume Bit
bits : 2 - 2 (1 bit)
access : write-only

RWR3 : XDMAC Channel 3 Read Write Resume Bit
bits : 3 - 3 (1 bit)
access : write-only

RWR4 : XDMAC Channel 4 Read Write Resume Bit
bits : 4 - 4 (1 bit)
access : write-only

RWR5 : XDMAC Channel 5 Read Write Resume Bit
bits : 5 - 5 (1 bit)
access : write-only

RWR6 : XDMAC Channel 6 Read Write Resume Bit
bits : 6 - 6 (1 bit)
access : write-only

RWR7 : XDMAC Channel 7 Read Write Resume Bit
bits : 7 - 7 (1 bit)
access : write-only

RWR8 : XDMAC Channel 8 Read Write Resume Bit
bits : 8 - 8 (1 bit)
access : write-only

RWR9 : XDMAC Channel 9 Read Write Resume Bit
bits : 9 - 9 (1 bit)
access : write-only

RWR10 : XDMAC Channel 10 Read Write Resume Bit
bits : 10 - 10 (1 bit)
access : write-only

RWR11 : XDMAC Channel 11 Read Write Resume Bit
bits : 11 - 11 (1 bit)
access : write-only

RWR12 : XDMAC Channel 12 Read Write Resume Bit
bits : 12 - 12 (1 bit)
access : write-only

RWR13 : XDMAC Channel 13 Read Write Resume Bit
bits : 13 - 13 (1 bit)
access : write-only

RWR14 : XDMAC Channel 14 Read Write Resume Bit
bits : 14 - 14 (1 bit)
access : write-only

RWR15 : XDMAC Channel 15 Read Write Resume Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS11

Channel Source Microblock Stride (chid = 11)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS11 CSUS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS11

Channel Destination Microblock Stride (chid = 11)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS11 CDUS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE12

Channel Interrupt Enable Register (chid = 12)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE12 CIE12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID12

Channel Interrupt Disable Register (chid = 12)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID12 CID12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM12

Channel Interrupt Mask Register (chid = 12)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM12 CIM12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS12

Channel Interrupt Status Register (chid = 12)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS12 CIS12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA12

Channel Source Address Register (chid = 12)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA12 CSA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA12

Channel Destination Address Register (chid = 12)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA12 CDA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA12

Channel Next Descriptor Address Register (chid = 12)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA12 CNDA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC12

Channel Next Descriptor Control Register (chid = 12)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC12 CNDC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC12

Channel Microblock Control Register (chid = 12)
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC12 CUBC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC12

Channel Block Control Register (chid = 12)
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC12 CBC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC12

Channel Configuration Register (chid = 12)
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC12 CC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP12

Channel Data Stride Memory Set Pattern (chid = 12)
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP12 CDS_MSP12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GSWR

Global Channel Software Request Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWR GSWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWREQ0 SWREQ1 SWREQ2 SWREQ3 SWREQ4 SWREQ5 SWREQ6 SWREQ7 SWREQ8 SWREQ9 SWREQ10 SWREQ11 SWREQ12 SWREQ13 SWREQ14 SWREQ15

SWREQ0 : XDMAC Channel 0 Software Request Bit
bits : 0 - 0 (1 bit)
access : write-only

SWREQ1 : XDMAC Channel 1 Software Request Bit
bits : 1 - 1 (1 bit)
access : write-only

SWREQ2 : XDMAC Channel 2 Software Request Bit
bits : 2 - 2 (1 bit)
access : write-only

SWREQ3 : XDMAC Channel 3 Software Request Bit
bits : 3 - 3 (1 bit)
access : write-only

SWREQ4 : XDMAC Channel 4 Software Request Bit
bits : 4 - 4 (1 bit)
access : write-only

SWREQ5 : XDMAC Channel 5 Software Request Bit
bits : 5 - 5 (1 bit)
access : write-only

SWREQ6 : XDMAC Channel 6 Software Request Bit
bits : 6 - 6 (1 bit)
access : write-only

SWREQ7 : XDMAC Channel 7 Software Request Bit
bits : 7 - 7 (1 bit)
access : write-only

SWREQ8 : XDMAC Channel 8 Software Request Bit
bits : 8 - 8 (1 bit)
access : write-only

SWREQ9 : XDMAC Channel 9 Software Request Bit
bits : 9 - 9 (1 bit)
access : write-only

SWREQ10 : XDMAC Channel 10 Software Request Bit
bits : 10 - 10 (1 bit)
access : write-only

SWREQ11 : XDMAC Channel 11 Software Request Bit
bits : 11 - 11 (1 bit)
access : write-only

SWREQ12 : XDMAC Channel 12 Software Request Bit
bits : 12 - 12 (1 bit)
access : write-only

SWREQ13 : XDMAC Channel 13 Software Request Bit
bits : 13 - 13 (1 bit)
access : write-only

SWREQ14 : XDMAC Channel 14 Software Request Bit
bits : 14 - 14 (1 bit)
access : write-only

SWREQ15 : XDMAC Channel 15 Software Request Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS12

Channel Source Microblock Stride (chid = 12)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS12 CSUS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS12

Channel Destination Microblock Stride (chid = 12)
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS12 CDUS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE13

Channel Interrupt Enable Register (chid = 13)
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE13 CIE13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID13

Channel Interrupt Disable Register (chid = 13)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID13 CID13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM13

Channel Interrupt Mask Register (chid = 13)
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM13 CIM13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS13

Channel Interrupt Status Register (chid = 13)
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS13 CIS13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA13

Channel Source Address Register (chid = 13)
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA13 CSA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA13

Channel Destination Address Register (chid = 13)
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA13 CDA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA13

Channel Next Descriptor Address Register (chid = 13)
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA13 CNDA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC13

Channel Next Descriptor Control Register (chid = 13)
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC13 CNDC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC13

Channel Microblock Control Register (chid = 13)
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC13 CUBC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC13

Channel Block Control Register (chid = 13)
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC13 CBC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC13

Channel Configuration Register (chid = 13)
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC13 CC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP13

Channel Data Stride Memory Set Pattern (chid = 13)
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP13 CDS_MSP13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GSWS

Global Channel Software Request Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GSWS GSWS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRS0 SWRS1 SWRS2 SWRS3 SWRS4 SWRS5 SWRS6 SWRS7 SWRS8 SWRS9 SWRS10 SWRS11 SWRS12 SWRS13 SWRS14 SWRS15

SWRS0 : XDMAC Channel 0 Software Request Status Bit
bits : 0 - 0 (1 bit)
access : read-only

SWRS1 : XDMAC Channel 1 Software Request Status Bit
bits : 1 - 1 (1 bit)
access : read-only

SWRS2 : XDMAC Channel 2 Software Request Status Bit
bits : 2 - 2 (1 bit)
access : read-only

SWRS3 : XDMAC Channel 3 Software Request Status Bit
bits : 3 - 3 (1 bit)
access : read-only

SWRS4 : XDMAC Channel 4 Software Request Status Bit
bits : 4 - 4 (1 bit)
access : read-only

SWRS5 : XDMAC Channel 5 Software Request Status Bit
bits : 5 - 5 (1 bit)
access : read-only

SWRS6 : XDMAC Channel 6 Software Request Status Bit
bits : 6 - 6 (1 bit)
access : read-only

SWRS7 : XDMAC Channel 7 Software Request Status Bit
bits : 7 - 7 (1 bit)
access : read-only

SWRS8 : XDMAC Channel 8 Software Request Status Bit
bits : 8 - 8 (1 bit)
access : read-only

SWRS9 : XDMAC Channel 9 Software Request Status Bit
bits : 9 - 9 (1 bit)
access : read-only

SWRS10 : XDMAC Channel 10 Software Request Status Bit
bits : 10 - 10 (1 bit)
access : read-only

SWRS11 : XDMAC Channel 11 Software Request Status Bit
bits : 11 - 11 (1 bit)
access : read-only

SWRS12 : XDMAC Channel 12 Software Request Status Bit
bits : 12 - 12 (1 bit)
access : read-only

SWRS13 : XDMAC Channel 13 Software Request Status Bit
bits : 13 - 13 (1 bit)
access : read-only

SWRS14 : XDMAC Channel 14 Software Request Status Bit
bits : 14 - 14 (1 bit)
access : read-only

SWRS15 : XDMAC Channel 15 Software Request Status Bit
bits : 15 - 15 (1 bit)
access : read-only


CSUS13

Channel Source Microblock Stride (chid = 13)
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS13 CSUS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS13

Channel Destination Microblock Stride (chid = 13)
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS13 CDUS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE14

Channel Interrupt Enable Register (chid = 14)
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE14 CIE14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID14

Channel Interrupt Disable Register (chid = 14)
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID14 CID14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM14

Channel Interrupt Mask Register (chid = 14)
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM14 CIM14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS14

Channel Interrupt Status Register (chid = 14)
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS14 CIS14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA14

Channel Source Address Register (chid = 14)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA14 CSA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA14

Channel Destination Address Register (chid = 14)
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA14 CDA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA14

Channel Next Descriptor Address Register (chid = 14)
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA14 CNDA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC14

Channel Next Descriptor Control Register (chid = 14)
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC14 CNDC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC14

Channel Microblock Control Register (chid = 14)
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC14 CUBC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC14

Channel Block Control Register (chid = 14)
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC14 CBC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC14

Channel Configuration Register (chid = 14)
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC14 CC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP14

Channel Data Stride Memory Set Pattern (chid = 14)
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP14 CDS_MSP14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GCFG

Global Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCFG GCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGDISREG CGDISPIPE CGDISFIFO CGDISIF BXKBEN

CGDISREG : Configuration Registers Clock Gating Disable
bits : 0 - 0 (1 bit)
access : read-write

CGDISPIPE : Pipeline Clock Gating Disable
bits : 1 - 1 (1 bit)
access : read-write

CGDISFIFO : FIFO Clock Gating Disable
bits : 2 - 2 (1 bit)
access : read-write

CGDISIF : Bus Interface Clock Gating Disable
bits : 3 - 3 (1 bit)
access : read-write

BXKBEN : Boundary X Kilobyte Enable
bits : 8 - 8 (1 bit)
access : read-write


GSWF

Global Channel Software Flush Request Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWF GSWF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWF0 SWF1 SWF2 SWF3 SWF4 SWF5 SWF6 SWF7 SWF8 SWF9 SWF10 SWF11 SWF12 SWF13 SWF14 SWF15

SWF0 : XDMAC Channel 0 Software Flush Request Bit
bits : 0 - 0 (1 bit)
access : write-only

SWF1 : XDMAC Channel 1 Software Flush Request Bit
bits : 1 - 1 (1 bit)
access : write-only

SWF2 : XDMAC Channel 2 Software Flush Request Bit
bits : 2 - 2 (1 bit)
access : write-only

SWF3 : XDMAC Channel 3 Software Flush Request Bit
bits : 3 - 3 (1 bit)
access : write-only

SWF4 : XDMAC Channel 4 Software Flush Request Bit
bits : 4 - 4 (1 bit)
access : write-only

SWF5 : XDMAC Channel 5 Software Flush Request Bit
bits : 5 - 5 (1 bit)
access : write-only

SWF6 : XDMAC Channel 6 Software Flush Request Bit
bits : 6 - 6 (1 bit)
access : write-only

SWF7 : XDMAC Channel 7 Software Flush Request Bit
bits : 7 - 7 (1 bit)
access : write-only

SWF8 : XDMAC Channel 8 Software Flush Request Bit
bits : 8 - 8 (1 bit)
access : write-only

SWF9 : XDMAC Channel 9 Software Flush Request Bit
bits : 9 - 9 (1 bit)
access : write-only

SWF10 : XDMAC Channel 10 Software Flush Request Bit
bits : 10 - 10 (1 bit)
access : write-only

SWF11 : XDMAC Channel 11 Software Flush Request Bit
bits : 11 - 11 (1 bit)
access : write-only

SWF12 : XDMAC Channel 12 Software Flush Request Bit
bits : 12 - 12 (1 bit)
access : write-only

SWF13 : XDMAC Channel 13 Software Flush Request Bit
bits : 13 - 13 (1 bit)
access : write-only

SWF14 : XDMAC Channel 14 Software Flush Request Bit
bits : 14 - 14 (1 bit)
access : write-only

SWF15 : XDMAC Channel 15 Software Flush Request Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS14

Channel Source Microblock Stride (chid = 14)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS14 CSUS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS14

Channel Destination Microblock Stride (chid = 14)
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS14 CDUS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE15

Channel Interrupt Enable Register (chid = 15)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE15 CIE15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID15

Channel Interrupt Disable Register (chid = 15)
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID15 CID15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM15

Channel Interrupt Mask Register (chid = 15)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM15 CIM15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS15

Channel Interrupt Status Register (chid = 15)
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS15 CIS15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA15

Channel Source Address Register (chid = 15)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA15 CSA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA15

Channel Destination Address Register (chid = 15)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA15 CDA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA15

Channel Next Descriptor Address Register (chid = 15)
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA15 CNDA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC15

Channel Next Descriptor Control Register (chid = 15)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC15 CNDC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC15

Channel Microblock Control Register (chid = 15)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC15 CUBC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC15

Channel Block Control Register (chid = 15)
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC15 CBC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC15

Channel Configuration Register (chid = 15)
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC15 CC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP15

Channel Data Stride Memory Set Pattern (chid = 15)
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP15 CDS_MSP15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CSUS15

Channel Source Microblock Stride (chid = 15)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS15 CSUS15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS15

Channel Destination Microblock Stride (chid = 15)
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS15 CDUS15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE0

Channel Interrupt Enable Register (chid = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE0 CIE0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID0

Channel Interrupt Disable Register (chid = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM0

Channel Interrupt Mask Register (chid = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM0 CIM0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS0

Channel Interrupt Status Register (chid = 0)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS0 CIS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA0

Channel Source Address Register (chid = 0)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA0 CSA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA0

Channel Destination Address Register (chid = 0)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA0 CDA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA0

Channel Next Descriptor Address Register (chid = 0)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA0 CNDA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC0

Channel Next Descriptor Control Register (chid = 0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC0 CNDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC0

Channel Microblock Control Register (chid = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC0 CUBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC0

Channel Block Control Register (chid = 0)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC0 CBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC0

Channel Configuration Register (chid = 0)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0 CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP0

Channel Data Stride Memory Set Pattern (chid = 0)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP0 CDS_MSP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GWAC

Global Weighted Arbiter Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWAC GWAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW0 PW1 PW2 PW3

PW0 : Pool Weight 0
bits : 0 - 3 (4 bit)
access : read-write

PW1 : Pool Weight 1
bits : 4 - 7 (4 bit)
access : read-write

PW2 : Pool Weight 2
bits : 8 - 11 (4 bit)
access : read-write

PW3 : Pool Weight 3
bits : 12 - 15 (4 bit)
access : read-write


CSUS0

Channel Source Microblock Stride (chid = 0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS0 CSUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS0

Channel Destination Microblock Stride (chid = 0)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS0 CDUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE1

Channel Interrupt Enable Register (chid = 1)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE1 CIE1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID1

Channel Interrupt Disable Register (chid = 1)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM1

Channel Interrupt Mask Register (chid = 1)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM1 CIM1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS1

Channel Interrupt Status Register (chid = 1)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS1 CIS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA1

Channel Source Address Register (chid = 1)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA1 CSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA1

Channel Destination Address Register (chid = 1)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA1 CDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA1

Channel Next Descriptor Address Register (chid = 1)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA1 CNDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC1

Channel Next Descriptor Control Register (chid = 1)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC1 CNDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC1

Channel Microblock Control Register (chid = 1)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC1 CUBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC1

Channel Block Control Register (chid = 1)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC1 CBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC1

Channel Configuration Register (chid = 1)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1 CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP1

Channel Data Stride Memory Set Pattern (chid = 1)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP1 CDS_MSP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GIE

Global Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GIE GIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE1 IE2 IE3 IE4 IE5 IE6 IE7 IE8 IE9 IE10 IE11 IE12 IE13 IE14 IE15

IE0 : XDMAC Channel 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

IE1 : XDMAC Channel 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

IE2 : XDMAC Channel 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

IE3 : XDMAC Channel 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

IE4 : XDMAC Channel 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

IE5 : XDMAC Channel 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

IE6 : XDMAC Channel 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only

IE7 : XDMAC Channel 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : write-only

IE8 : XDMAC Channel 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : write-only

IE9 : XDMAC Channel 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : write-only

IE10 : XDMAC Channel 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : write-only

IE11 : XDMAC Channel 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : write-only

IE12 : XDMAC Channel 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : write-only

IE13 : XDMAC Channel 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : write-only

IE14 : XDMAC Channel 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : write-only

IE15 : XDMAC Channel 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : write-only


CSUS1

Channel Source Microblock Stride (chid = 1)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS1 CSUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS1

Channel Destination Microblock Stride (chid = 1)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS1 CDUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE2

Channel Interrupt Enable Register (chid = 2)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE2 CIE2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID2

Channel Interrupt Disable Register (chid = 2)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM2

Channel Interrupt Mask Register (chid = 2)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM2 CIM2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS2

Channel Interrupt Status Register (chid = 2)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS2 CIS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA2

Channel Source Address Register (chid = 2)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA2 CSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA2

Channel Destination Address Register (chid = 2)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA2 CDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA2

Channel Next Descriptor Address Register (chid = 2)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA2 CNDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC2

Channel Next Descriptor Control Register (chid = 2)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC2 CNDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC2

Channel Microblock Control Register (chid = 2)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC2 CUBC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC2

Channel Block Control Register (chid = 2)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC2 CBC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC2

Channel Configuration Register (chid = 2)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2 CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC PROT SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

0x3 : DWORD

The data size is set to 64 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP2

Channel Data Stride Memory Set Pattern (chid = 2)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP2 CDS_MSP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write



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