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TWIHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CR_FIFO_ENABLED

CWGR

SR

SR_FIFO_ENABLED

IER

IDR

IMR

RHR

RHR_FIFO_ENABLED

THR

THR_FIFO_ENABLED

SMBTR

MMR

ACR

FILTR

SWMR

FMR

FLR

FSR

FIER

FIDR

FIMR

SMR

IADR

WPMR

WPSR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST HSEN HSDIS SMBEN SMBDIS PECEN PECDIS PECRQ CLEAR ACMEN ACMDIS THRCLR LOCKCLR FIFOEN FIFODIS

START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only

MSEN : TWIHS Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only

MSDIS : TWIHS Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only

SVEN : TWIHS Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only

SVDIS : TWIHS Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only

QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only

HSEN : TWIHS High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only

HSDIS : TWIHS High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only

SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)
access : write-only

SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)
access : write-only

PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)
access : write-only

PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)
access : write-only

PECRQ : PEC Request
bits : 14 - 14 (1 bit)
access : write-only

CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only

ACMEN : Alternative Command Mode Enable
bits : 16 - 16 (1 bit)
access : write-only

ACMDIS : Alternative Command Mode Disable
bits : 17 - 17 (1 bit)
access : write-only

THRCLR : Transmit Holding Register Clear
bits : 24 - 24 (1 bit)
access : write-only

LOCKCLR : Lock Clear
bits : 26 - 26 (1 bit)
access : write-only

FIFOEN : FIFO Enable
bits : 28 - 28 (1 bit)
access : write-only

FIFODIS : FIFO Disable
bits : 29 - 29 (1 bit)
access : write-only


CR_FIFO_ENABLED

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0

CR_FIFO_ENABLED CR_FIFO_ENABLED write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST HSEN HSDIS SMBEN SMBDIS PECEN PECDIS PECRQ CLEAR ACMEN ACMDIS TXFCLR RXFCLR TXFLCLR FIFOEN FIFODIS

START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only

MSEN : TWIHS Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only

MSDIS : TWIHS Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only

SVEN : TWIHS Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only

SVDIS : TWIHS Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only

QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only

HSEN : TWIHS High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only

HSDIS : TWIHS High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only

SMBEN :
bits : 10 - 10 (1 bit)
access : write-only

SMBDIS :
bits : 11 - 11 (1 bit)
access : write-only

PECEN :
bits : 12 - 12 (1 bit)
access : write-only

PECDIS :
bits : 13 - 13 (1 bit)
access : write-only

PECRQ :
bits : 14 - 14 (1 bit)
access : write-only

CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only

ACMEN : Alternative Command Mode Enable
bits : 16 - 16 (1 bit)
access : write-only

ACMDIS : Alternative Command Mode Disable
bits : 17 - 17 (1 bit)
access : write-only

TXFCLR : Transmit FIFO Clear
bits : 24 - 24 (1 bit)
access : write-only

RXFCLR : Receive FIFO Clear
bits : 25 - 25 (1 bit)
access : write-only

TXFLCLR : Transmit FIFO Lock CLEAR
bits : 26 - 26 (1 bit)
access : write-only

FIFOEN : FIFO Enable
bits : 28 - 28 (1 bit)
access : write-only

FIFODIS : FIFO Disable
bits : 29 - 29 (1 bit)
access : write-only


CWGR

Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWGR CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDIV CHDIV CKDIV CKSRC HOLD

CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write

CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write

CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write

CKSRC : Transfer Rate Clock Source
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : PERIPH_CK

Peripheral clock is used to generate the TWIHS baud rate.

1 : GCLK

GCLK is used to generate the TWIHS baud rate.

End of enumeration elements list.

HOLD : TWD Hold Time Versus TWCK Falling
bits : 24 - 28 (5 bit)
access : read-write


SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE UNRE NACK ARBLST SCLWS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM LOCK SCL SDA

TXCOMP : Transmission Completed (cleared by writing TWIHS_THR)
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready (cleared by reading TWIHS_RHR)
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready (cleared by writing TWIHS_THR)
bits : 2 - 2 (1 bit)
access : read-only

SVREAD : Slave Read
bits : 3 - 3 (1 bit)
access : read-only

SVACC : Slave Access
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)
access : read-only

SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only

MCACK : Master Code Acknowledge (cleared on read)
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error (cleared on read)
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only

LOCK : TWIHS Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWIHS_CR)
bits : 23 - 23 (1 bit)
access : read-only

SCL : SCL Line Value
bits : 24 - 24 (1 bit)
access : read-only

SDA : SDA Line Value
bits : 25 - 25 (1 bit)
access : read-only


SR_FIFO_ENABLED

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0

SR_FIFO_ENABLED SR_FIFO_ENABLED read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE UNRE NACK ARBLST SCLWS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM TXFLOCK SCL SDA

TXCOMP : Transmission Completed (cleared by writing TWIHS_THR)
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready (cleared by reading TWIHS_RHR)
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready (cleared by writing TWIHS_THR)
bits : 2 - 2 (1 bit)
access : read-only

SVREAD : Slave Read
bits : 3 - 3 (1 bit)
access : read-only

SVACC : Slave Access
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)
access : read-only

SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only

MCACK :
bits : 16 - 16 (1 bit)
access : read-only

TOUT :
bits : 18 - 18 (1 bit)
access : read-only

PECERR :
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM :
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM :
bits : 21 - 21 (1 bit)
access : read-only

TXFLOCK : Transmit FIFO Lock
bits : 23 - 23 (1 bit)
access : read-only

SCL : SCL Line Value
bits : 24 - 24 (1 bit)
access : read-only

SDA : SDA Line Value
bits : 25 - 25 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only

MCACK : Master Code Acknowledge Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only


RHR_FIFO_ENABLED

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0

RHR_FIFO_ENABLED RHR_FIFO_ENABLED read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1 RXDATA2 RXDATA3

RXDATA0 : Master or Slave Receive Holding Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : Master or Slave Receive Holding Data 1
bits : 8 - 15 (8 bit)
access : read-only

RXDATA2 : Master or Slave Receive Holding Data 2
bits : 16 - 23 (8 bit)
access : read-only

RXDATA3 : Master or Slave Receive Holding Data 3
bits : 24 - 31 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only


THR_FIFO_ENABLED

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0

THR_FIFO_ENABLED THR_FIFO_ENABLED write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1 TXDATA2 TXDATA3

TXDATA0 : Master or Slave Transmit Holding Data 02
bits : 0 - 7 (8 bit)
access : write-only

TXDATA1 : Master or Slave Transmit Holding Data 1
bits : 8 - 15 (8 bit)
access : write-only

TXDATA2 : Master or Slave Transmit Holding Data 2
bits : 16 - 23 (8 bit)
access : write-only

TXDATA3 : Master or Slave Transmit Holding Data 3
bits : 24 - 31 (8 bit)
access : write-only


SMBTR

SMBus Timing Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMBTR SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC TLOWS TLOWM THMAX

PRESC : SMBus Clock Prescaler
bits : 0 - 3 (4 bit)
access : read-write

TLOWS : Slave Clock Stretch Maximum Cycles
bits : 8 - 15 (8 bit)
access : read-write

TLOWM : Master Clock Stretch Maximum Cycles
bits : 16 - 23 (8 bit)
access : read-write

THMAX : Clock High Maximum Cycles
bits : 24 - 31 (8 bit)
access : read-write


MMR

Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR MMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADRSZ MREAD DADR

IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No internal device address

0x1 : 1_BYTE

One-byte internal device address

0x2 : 2_BYTE

Two-byte internal device address

0x3 : 3_BYTE

Three-byte internal device address

End of enumeration elements list.

MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write

DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write


ACR

Alternative Command Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAL DIR PEC NDATAL NDIR NPEC

DATAL : Data Length
bits : 0 - 7 (8 bit)
access : read-write

DIR : Transfer Direction
bits : 8 - 8 (1 bit)
access : read-write

PEC : PEC Request (SMBus Mode only)
bits : 9 - 9 (1 bit)
access : read-write

NDATAL : Next Data Length
bits : 16 - 23 (8 bit)
access : read-write

NDIR : Next Transfer Direction
bits : 24 - 24 (1 bit)
access : read-write

NPEC : Next PEC Request (SMBus Mode only)
bits : 25 - 25 (1 bit)
access : read-write


FILTR

Filter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTR FILTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT PADFEN PADFCFG THRES

FILT : RX Digital Filter
bits : 0 - 0 (1 bit)
access : read-write

PADFEN : PAD Filter Enable
bits : 1 - 1 (1 bit)
access : read-write

PADFCFG : PAD Filter Config
bits : 2 - 2 (1 bit)
access : read-write

THRES : Digital Filter Threshold
bits : 8 - 10 (3 bit)
access : read-write


SWMR

SleepWalking Matching Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWMR SWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADR1 SADR2 SADR3 DATAM

SADR1 : Slave Address 1
bits : 0 - 6 (7 bit)
access : read-write

SADR2 : Slave Address 2
bits : 8 - 14 (7 bit)
access : read-write

SADR3 : Slave Address 3
bits : 16 - 22 (7 bit)
access : read-write

DATAM : Data Match
bits : 24 - 31 (8 bit)
access : read-write


FMR

FIFO Mode Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMR FMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDYM RXRDYM TXFTHRES RXFTHRES

TXRDYM : Transmitter Ready Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : ONE_DATA

TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO

0x1 : TWO_DATA

TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO

0x2 : FOUR_DATA

TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO

End of enumeration elements list.

RXRDYM : Receiver Ready Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : ONE_DATA

RXRDY will be at level '1' when at least one unread data is in the Receive FIFO

0x1 : TWO_DATA

RXRDY will be at level '1' when at least two unread data are in the Receive FIFO

0x2 : FOUR_DATA

RXRDY will be at level '1' when at least four unread data are in the Receive FIFO

End of enumeration elements list.

TXFTHRES : Transmit FIFO Threshold
bits : 16 - 21 (6 bit)
access : read-write

RXFTHRES : Receive FIFO Threshold
bits : 24 - 29 (6 bit)
access : read-write


FLR

FIFO Level Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FLR FLR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFL RXFL

TXFL : Transmit FIFO Level
bits : 0 - 5 (6 bit)
access : read-only

RXFL : Receive FIFO Level
bits : 16 - 21 (6 bit)
access : read-only


FSR

FIFO Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSR FSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFEF TXFFF TXFTHF RXFEF RXFFF RXFTHF TXFPTEF RXFPTEF

TXFEF : Transmit FIFO Empty Flag (cleared on read)
bits : 0 - 0 (1 bit)
access : read-only

TXFFF : Transmit FIFO Full Flag (cleared on read)
bits : 1 - 1 (1 bit)
access : read-only

TXFTHF : Transmit FIFO Threshold Flag (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only

RXFEF : Receive FIFO Empty Flag
bits : 3 - 3 (1 bit)
access : read-only

RXFFF : Receive FIFO Full Flag
bits : 4 - 4 (1 bit)
access : read-only

RXFTHF : Receive FIFO Threshold Flag
bits : 5 - 5 (1 bit)
access : read-only

TXFPTEF : Transmit FIFO Pointer Error Flag
bits : 6 - 6 (1 bit)
access : read-only

RXFPTEF : Receive FIFO Pointer Error Flag
bits : 7 - 7 (1 bit)
access : read-only


FIER

FIFO Interrupt Enable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FIER FIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFEF TXFFF TXFTHF RXFEF RXFFF RXFTHF TXFPTEF RXFPTEF

TXFEF : TXFEF Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXFFF : TXFFF Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXFTHF : TXFTHF Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

RXFEF : RXFEF Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

RXFFF : RXFFF Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

RXFTHF : RXFTHF Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

TXFPTEF : TXFPTEF Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

RXFPTEF : RXFPTEF Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only


FIDR

FIFO Interrupt Disable Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FIDR FIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFEF TXFFF TXFTHF RXFEF RXFFF RXFTHF TXFPTEF RXFPTEF

TXFEF : TXFEF Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXFFF : TXFFF Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXFTHF : TXFTHF Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

RXFEF : RXFEF Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

RXFFF : RXFFF Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

RXFTHF : RXFTHF Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

TXFPTEF : TXFPTEF Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

RXFPTEF : RXFPTEF Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only


FIMR

FIFO Interrupt Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIMR FIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFEF TXFFF TXFTHF RXFEF RXFFF RXFTHF TXFPTEF RXFPTEF

TXFEF : TXFEF Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXFFF : TXFFF Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXFTHF : TXFTHF Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

RXFEF : RXFEF Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

RXFFF : RXFFF Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

RXFTHF : RXFTHF Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

TXFPTEF : TXFPTEF Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

RXFPTEF : RXFPTEF Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only


SMR

Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACKEN SMDA SMHH SCLWSDIS MASK SADR SADR1EN SADR2EN SADR3EN DATAMEN

NACKEN : Slave Receiver Data Phase NACK enable
bits : 0 - 0 (1 bit)
access : read-write

SMDA : SMBus Default Address
bits : 2 - 2 (1 bit)
access : read-write

SMHH : SMBus Host Header
bits : 3 - 3 (1 bit)
access : read-write

SCLWSDIS : Clock Wait State Disable
bits : 6 - 6 (1 bit)
access : read-write

MASK : Slave Address Mask
bits : 8 - 14 (7 bit)
access : read-write

SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write

SADR1EN : Slave Address 1 Enable
bits : 28 - 28 (1 bit)
access : read-write

SADR2EN : Slave Address 2 Enable
bits : 29 - 29 (1 bit)
access : read-write

SADR3EN : Slave Address 3 Enable
bits : 30 - 30 (1 bit)
access : read-write

DATAMEN : Data Matching Enable
bits : 31 - 31 (1 bit)
access : read-write


IADR

Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IADR IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADR

IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x545749 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 31 (24 bit)
access : read-only



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