\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
FLEXCOM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : FLEXCOM Operating Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : NO_COM
No communication
0x1 : USART
All UART related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN,)SPI/TWI related registers are not accessible and have no impact on IOs.
0x2 : SPI
SPI operating mode is selected.USART/TWI related registers are not accessible and have no impact on IOs.
0x3 : TWI
All TWI related protocols are selected (TWI, SMBus).USART/SPI related registers are not accessible and have no impact on IOs.
End of enumeration elements list.
FLEXCOM Receive Holding Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data
bits : 0 - 15 (16 bit)
access : read-only
FLEXCOM Transmit Holding Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-write
USART Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only
STTBRK : Start Break
bits : 9 - 9 (1 bit)
access : write-only
STPBRK : Stop Break
bits : 10 - 10 (1 bit)
access : write-only
STTTO : Clear TIMEOUT Flag and Start Timeout After Next Character Received
bits : 11 - 11 (1 bit)
access : write-only
SENDA : Send Address
bits : 12 - 12 (1 bit)
access : write-only
RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)
access : write-only
RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)
access : write-only
RETTO : Start Timeout Immediately
bits : 15 - 15 (1 bit)
access : write-only
RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)
access : write-only
RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)
access : write-only
LINABT : Abort LIN Transmission
bits : 20 - 20 (1 bit)
access : write-only
LINWKUP : Send LIN Wakeup Signal
bits : 21 - 21 (1 bit)
access : write-only
TXFCLR : Transmit FIFO Clear
bits : 24 - 24 (1 bit)
access : write-only
RXFCLR : Receive FIFO Clear
bits : 25 - 25 (1 bit)
access : write-only
TXFLCLR : Transmit FIFO Lock CLEAR
bits : 26 - 26 (1 bit)
access : write-only
REQCLR : Request to Clear the Comparison Trigger
bits : 28 - 28 (1 bit)
access : write-only
FIFOEN : FIFO Enable
bits : 30 - 30 (1 bit)
access : write-only
FIFODIS : FIFO Disable
bits : 31 - 31 (1 bit)
access : write-only
USART Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only
FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)
access : write-only
RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)
access : write-only
USART Mode Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal mode
0x1 : RS485
RS485
0x2 : HW_HANDSHAKING
Hardware handshaking
0x4 : IS07816_T_0
IS07816 Protocol: T = 0
0x6 : IS07816_T_1
IS07816 Protocol: T = 1
0x8 : IRDA
IrDA
0xA : LIN_MASTER
LIN Master mode
0xB : LIN_SLAVE
LIN Slave mode
0xE : SPI_MASTER
SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)
0xF : SPI_SLAVE
SPI Slave mode
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock is selected
0x1 : DIV
Peripheral clock divided (DIV = 8) is selected
0x2 : GCLK
PMC generic clock is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.
0x3 : SCK
External pin SCK is selected
End of enumeration elements list.
CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x0 : 5_BIT
Character length is 5 bits
0x1 : 6_BIT
Character length is 6 bits
0x2 : 7_BIT
Character length is 7 bits
0x3 : 8_BIT
Character length is 8 bits
End of enumeration elements list.
SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)
access : read-write
PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : EVEN
Even parity
0x1 : ODD
Odd parity
0x2 : SPACE
Parity forced to 0 (Space)
0x3 : MARK
Parity forced to 1 (Mark)
0x4 : NO
No parity
0x6 : MULTIDROP
Multidrop mode
End of enumeration elements list.
NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BIT
1 stop bit
0x1 : 1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x2 : 2_BIT
2 stop bits
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal mode
0x1 : AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x2 : LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x3 : REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
End of enumeration elements list.
MSBF : Bit Order
bits : 16 - 16 (1 bit)
access : read-write
MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
access : read-write
CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
access : read-write
OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
access : read-write
INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)
access : read-write
DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)
access : read-write
VAR_SYNC : Variable Synchronization of Command/Data Sync Start Frame Delimiter
bits : 22 - 22 (1 bit)
access : read-write
INVDATA : Inverted Data
bits : 23 - 23 (1 bit)
access : read-write
MAX_ITERATION : Maximum Number of Automatic Iteration
bits : 24 - 26 (3 bit)
access : read-write
FILTER : Receive Line Filter
bits : 28 - 28 (1 bit)
access : read-write
MAN : Manchester Encoder/Decoder Enable
bits : 29 - 29 (1 bit)
access : read-write
MODSYNC : Manchester Synchronization Mode
bits : 30 - 30 (1 bit)
access : read-write
ONEBIT : Start Frame Delimiter Selector
bits : 31 - 31 (1 bit)
access : read-write
USART Mode Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0xE : SPI_MASTER
SPI master
0xF : SPI_SLAVE
SPI slave
End of enumeration elements list.
USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock is selected
0x1 : DIV
Peripheral clock Divided (DIV= 8) is selected
0x2 : GCLK
A PMC generic clock is selected
0x3 : SCK
External pin SCK is selected
End of enumeration elements list.
CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x3 : 8_BIT
Character length is 8 bits
End of enumeration elements list.
CPHA : SPI Clock Phase
bits : 8 - 8 (1 bit)
access : read-write
CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
access : read-write
WRDBT : Wait Read Data Before Transfer
bits : 20 - 20 (1 bit)
access : read-write
USART Interrupt Enable Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Timeout Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
ITER : Max number of Repetitions Reached Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
NACK : Non Acknowledge Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
CMP : Comparison Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
MANE : Manchester Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
USART Interrupt Enable Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
UNRE : SPI Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)
access : write-only
CMP : Comparison Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
USART Interrupt Enable Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Timeout Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
LINBK : LIN Break Sent or LIN Break Received Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
LINTC : LIN Transfer Completed Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
LINBE : LIN Bus Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
LINISFE : LIN Inconsistent Synch Field Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
LINIPE : LIN Identifier Parity Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
LINCE : LIN Checksum Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
LINSNRE : LIN Slave Not Responding Error Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
LINSTE : LIN Synch Tolerance Error Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
LINHTE : LIN Header Timeout Error Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
USART Interrupt Disable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Timeout Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
ITER : Max Number of Repetitions Reached Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
NACK : Non Acknowledge Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
CMP : Comparison Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
MANE : Manchester Error Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
USART Interrupt Disable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)
access : write-only
CMP : Comparison Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
USART Interrupt Disable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
TIMEOUT : Timeout Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
LINBK : LIN Break Sent or LIN Break Received Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
LINTC : LIN Transfer Completed Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
LINBE : LIN Bus Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
LINISFE : LIN Inconsistent Synch Field Error Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
LINIPE : LIN Identifier Parity Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
LINCE : LIN Checksum Error Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
LINSNRE : LIN Slave Not Responding Error Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
LINSTE : LIN Synch Tolerance Error Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
LINHTE : LIN Header Timeout Error Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
USART Interrupt Mask Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Timeout Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
ITER : Max Number of Repetitions Reached Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
NACK : Non Acknowledge Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
CMP : Comparison Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
MANE : Manchester Error Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
USART Interrupt Mask Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event
bits : 19 - 19 (1 bit)
access : read-only
CMP : Comparison Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
USART Interrupt Mask Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Timeout Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
LINBK : LIN Break Sent or LIN Break Received Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
LINTC : LIN Transfer Completed Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
LINBE : LIN Bus Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
LINISFE : LIN Inconsistent Synch Field Error Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
LINIPE : LIN Identifier Parity Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
LINCE : LIN Checksum Error Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
LINSTE : LIN Synch Tolerance Error Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
LINHTE : LIN Header Timeout Error Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
USART Channel Status Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready (cleared by reading FLEX_US_RHR)
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready (cleared by writing FLEX_US_THR)
bits : 1 - 1 (1 bit)
access : read-only
RXBRK : Break Received/End of Break
bits : 2 - 2 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Receiver Timeout
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty (cleared by writing FLEX_US_THR)
bits : 9 - 9 (1 bit)
access : read-only
ITER : Max Number of Repetitions Reached
bits : 10 - 10 (1 bit)
access : read-only
NACK : Non Acknowledge Interrupt
bits : 13 - 13 (1 bit)
access : read-only
CTSIC : Clear to Send Input Change Flag
bits : 19 - 19 (1 bit)
access : read-only
CMP : Comparison Status
bits : 22 - 22 (1 bit)
access : read-only
CTS : Image of CTS Input
bits : 23 - 23 (1 bit)
access : read-only
MANE : Manchester Error
bits : 24 - 24 (1 bit)
access : read-only
USART Channel Status Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready (cleared by reading FLEX_US_RHR)
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready (cleared by writing FLEX_US_THR)
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty (cleared by writing FLEX_US_THR)
bits : 9 - 9 (1 bit)
access : read-only
UNRE : Underrun Error
bits : 10 - 10 (1 bit)
access : read-only
NSSE : NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only
CMP : Comparison Match
bits : 22 - 22 (1 bit)
access : read-only
NSS : NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)
bits : 23 - 23 (1 bit)
access : read-only
USART Channel Status Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0
RXRDY : Receiver Ready (cleared by reading FLEX_US_RHR)
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready (cleared by writing FLEX_US_THR)
bits : 1 - 1 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only
TIMEOUT : Receiver Timeout
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty (cleared by writing FLEX_US_THR)
bits : 9 - 9 (1 bit)
access : read-only
LINBK : LIN Break Sent or LIN Break Received
bits : 13 - 13 (1 bit)
access : read-only
LINID : LIN Identifier Sent or LIN Identifier Received
bits : 14 - 14 (1 bit)
access : read-only
LINTC : LIN Transfer Completed
bits : 15 - 15 (1 bit)
access : read-only
LINBLS : LIN Bus Line Status
bits : 23 - 23 (1 bit)
access : read-only
LINBE : LIN Bit Error
bits : 25 - 25 (1 bit)
access : read-only
LINISFE : LIN Inconsistent Synch Field Error
bits : 26 - 26 (1 bit)
access : read-only
LINIPE : LIN Identifier Parity Error
bits : 27 - 27 (1 bit)
access : read-only
LINCE : LIN Checksum Error
bits : 28 - 28 (1 bit)
access : read-only
LINSNRE : LIN Slave Not Responding Error
bits : 29 - 29 (1 bit)
access : read-only
LINSTE : LIN Synch Tolerance Error
bits : 30 - 30 (1 bit)
access : read-only
LINHTE : LIN Header Timeout Error
bits : 31 - 31 (1 bit)
access : read-only
USART Receive Holding Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 8 (9 bit)
access : read-only
RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
access : read-only
USART Receive Holding Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_MULTI_DATA
reset_Mask : 0x0
RXCHR0 : Received Character
bits : 0 - 7 (8 bit)
access : read-only
RXCHR1 : Received Character
bits : 8 - 15 (8 bit)
access : read-only
RXCHR2 : Received Character
bits : 16 - 23 (8 bit)
access : read-only
RXCHR3 : Received Character
bits : 24 - 31 (8 bit)
access : read-only
USART Transmit Holding Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
access : write-only
TXSYNH : Sync Field to be Transmitted
bits : 15 - 15 (1 bit)
access : write-only
USART Transmit Holding Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_MULTI_DATA
reset_Mask : 0x0
TXCHR0 : Character to be Transmitted
bits : 0 - 7 (8 bit)
access : write-only
TXCHR1 : Character to be Transmitted
bits : 8 - 15 (8 bit)
access : write-only
TXCHR2 : Character to be Transmitted
bits : 16 - 23 (8 bit)
access : write-only
TXCHR3 : Character to be Transmitted
bits : 24 - 31 (8 bit)
access : write-only
USART Baud Rate Generator Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divider
bits : 0 - 15 (16 bit)
access : read-write
FP : Fractional Part
bits : 16 - 18 (3 bit)
access : read-write
USART Receiver Timeout Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Timeout Value
bits : 0 - 16 (17 bit)
access : read-write
USART Transmitter Timeguard Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TG : Timeguard Value
bits : 0 - 7 (8 bit)
access : read-write
USART FI DI Ratio Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 15 (16 bit)
access : read-write
USART Number of Errors Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NB_ERRORS : Number of Errors
bits : 0 - 7 (8 bit)
access : read-only
USART IrDA Filter Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRDA_FILTER : IrDA Filter
bits : 0 - 7 (8 bit)
access : read-write
USART Manchester Configuration Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PL : Transmitter Preamble Length
bits : 0 - 3 (4 bit)
access : read-write
TX_PP : Transmitter Preamble Pattern
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : ALL_ONE
The preamble is composed of '1's
0x1 : ALL_ZERO
The preamble is composed of '0's
0x2 : ZERO_ONE
The preamble is composed of '01's
0x3 : ONE_ZERO
The preamble is composed of '10's
End of enumeration elements list.
TX_MPOL : Transmitter Manchester Polarity
bits : 12 - 12 (1 bit)
access : read-write
RX_PL : Receiver Preamble Length
bits : 16 - 19 (4 bit)
access : read-write
RX_PP : Receiver Preamble Pattern detected
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : ALL_ONE
The preamble is composed of '1's
0x1 : ALL_ZERO
The preamble is composed of '0's
0x2 : ZERO_ONE
The preamble is composed of '01's
0x3 : ONE_ZERO
The preamble is composed of '10's
End of enumeration elements list.
RX_MPOL : Receiver Manchester Polarity
bits : 28 - 28 (1 bit)
access : read-write
ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)
access : read-write
DRIFT : Drift Compensation
bits : 30 - 30 (1 bit)
access : read-write
RXIDLEV : Receiver Idle Value
bits : 31 - 31 (1 bit)
access : read-write
USART LIN Mode Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACT : LIN Node Action
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : PUBLISH
The USART transmits the response.
0x1 : SUBSCRIBE
The USART receives the response.
0x2 : IGNORE
The USART does not transmit and does not receive the response.
End of enumeration elements list.
PARDIS : Parity Disable
bits : 2 - 2 (1 bit)
access : read-write
CHKDIS : Checksum Disable
bits : 3 - 3 (1 bit)
access : read-write
CHKTYP : Checksum Type
bits : 4 - 4 (1 bit)
access : read-write
DLM : Data Length Mode
bits : 5 - 5 (1 bit)
access : read-write
FSDIS : Frame Slot Mode Disable
bits : 6 - 6 (1 bit)
access : read-write
WKUPTYP : Wakeup Signal Type
bits : 7 - 7 (1 bit)
access : read-write
DLC : Data Length Control
bits : 8 - 15 (8 bit)
access : read-write
PDCM : DMAC Mode
bits : 16 - 16 (1 bit)
access : read-write
SYNCDIS : Synchronization Disable
bits : 17 - 17 (1 bit)
access : read-write
USART LIN Identifier Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDCHR : Identifier Character
bits : 0 - 7 (8 bit)
access : read-write
USART LIN Baud Rate Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LINCD : Clock Divider after Synchronization
bits : 0 - 15 (16 bit)
access : read-only
LINFP : Fractional Part after Synchronization
bits : 16 - 18 (3 bit)
access : read-only
USART Comparison Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : First Comparison Value for Received Character
bits : 0 - 8 (9 bit)
access : read-write
CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FLAG_ONLY
Any character is received and comparison function drives CMP flag.
1 : START_CONDITION
Comparison condition must be met to start reception.
End of enumeration elements list.
CMPPAR : Compare Parity
bits : 14 - 14 (1 bit)
access : read-write
VAL2 : Second Comparison Value for Received Character
bits : 16 - 24 (9 bit)
access : read-write
USART FIFO Mode Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRDYM : Transmitter Ready Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : ONE_DATA
TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO
0x1 : TWO_DATA
TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO
0x2 : FOUR_DATA
TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO
End of enumeration elements list.
RXRDYM : Receiver Ready Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : ONE_DATA
RXRDY will be at level '1' when at least one unread data is in the Receive FIFO
0x1 : TWO_DATA
RXRDY will be at level '1' when at least two unread data are in the Receive FIFO
0x2 : FOUR_DATA
RXRDY will be at level '1' when at least four unread data are in the Receive FIFO
End of enumeration elements list.
FRTSC : FIFO RTS Pin Control enable (Hardware Handshaking mode only)
bits : 7 - 7 (1 bit)
access : read-write
TXFTHRES : Transmit FIFO Threshold
bits : 8 - 13 (6 bit)
access : read-write
RXFTHRES : Receive FIFO Threshold
bits : 16 - 21 (6 bit)
access : read-write
RXFTHRES2 : Receive FIFO Threshold 2
bits : 24 - 29 (6 bit)
access : read-write
USART FIFO Level Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFL : Transmit FIFO Level
bits : 0 - 5 (6 bit)
access : read-only
RXFL : Receive FIFO Level
bits : 16 - 21 (6 bit)
access : read-only
USART FIFO Interrupt Enable Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
RXFTHF2 : RXFTHF2 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
USART FIFO Interrupt Disable Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
RXFTHF2 : RXFTHF2 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
USART FIFO Interrupt Mask Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXFFF : TXFFF Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXFTHF : TXFTHF Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
RXFEF : RXFEF Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
RXFFF : RXFFF Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
RXFTHF : RXFTHF Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
TXFPTEF : TXFPTEF Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
RXFPTEF : RXFPTEF Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
RXFTHF2 : RXFTHF2 Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
USART FIFO Event Status Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 0 - 0 (1 bit)
access : read-only
TXFFF : Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 1 - 1 (1 bit)
access : read-only
TXFTHF : Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 2 - 2 (1 bit)
access : read-only
RXFEF : Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 3 - 3 (1 bit)
access : read-only
RXFFF : Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 4 - 4 (1 bit)
access : read-only
RXFTHF : Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 5 - 5 (1 bit)
access : read-only
TXFPTEF : Transmit FIFO Pointer Error Flag
bits : 6 - 6 (1 bit)
access : read-only
RXFPTEF : Receive FIFO Pointer Error Flag
bits : 7 - 7 (1 bit)
access : read-only
TXFLOCK : Transmit FIFO Lock
bits : 8 - 8 (1 bit)
access : read-only
RXFTHF2 : Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)
bits : 9 - 9 (1 bit)
access : read-only
USART Write Protection Mode Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x555341 : PASSWD
Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0.
End of enumeration elements list.
USART Write Protection Status Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
SPI Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : write-only
SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)
access : write-only
SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)
access : write-only
REQCLR : Request to Clear the Comparison Trigger
bits : 12 - 12 (1 bit)
access : write-only
TXFCLR : Transmit FIFO Clear
bits : 16 - 16 (1 bit)
access : write-only
RXFCLR : Receive FIFO Clear
bits : 17 - 17 (1 bit)
access : write-only
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only
FIFOEN : FIFO Enable
bits : 30 - 30 (1 bit)
access : write-only
FIFODIS : FIFO Disable
bits : 31 - 31 (1 bit)
access : write-only
SPI Mode Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)
access : read-write
PS : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write
PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)
access : read-write
BRSRCCLK : Bit Rate Source Clock
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK
The peripheral clock is the source clock for the bit rate generation.
1 : GCLK
GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
End of enumeration elements list.
MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)
access : read-write
WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)
access : read-write
LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write
CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FLAG_ONLY
Any character is received and comparison function drives CMP flag.
1 : START_CONDITION
Comparison condition must be met to start reception of all incoming characters until REQCLR is set.
End of enumeration elements list.
PCS : Peripheral Chip Select
bits : 16 - 17 (2 bit)
access : read-write
DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)
access : read-write
SPI Receive Data Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD : Receive Data
bits : 0 - 15 (16 bit)
access : read-only
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-only
SPI Receive Data Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_MULTI_DATA_8
reset_Mask : 0x0
RD0 : Receive Data
bits : 0 - 7 (8 bit)
access : read-only
RD1 : Receive Data
bits : 8 - 15 (8 bit)
access : read-only
RD2 : Receive Data
bits : 16 - 23 (8 bit)
access : read-only
RD3 : Receive Data
bits : 24 - 31 (8 bit)
access : read-only
SPI Receive Data Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_MULTI_DATA_16
reset_Mask : 0x0
RD0 : Receive Data
bits : 0 - 15 (16 bit)
access : read-only
RD1 : Receive Data
bits : 16 - 31 (16 bit)
access : read-only
SPI Transmit Data Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TD : Transmit Data
bits : 0 - 15 (16 bit)
access : write-only
PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : write-only
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only
SPI Transmit Data Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_MULTI_DATA
reset_Mask : 0x0
TD0 : Transmit Data
bits : 0 - 15 (16 bit)
access : write-only
TD1 : Transmit Data
bits : 16 - 31 (16 bit)
access : write-only
SPI Status Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full (cleared by reading FLEX_SPI_RDR)
bits : 0 - 0 (1 bit)
access : read-only
TDRE : Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)
bits : 1 - 1 (1 bit)
access : read-only
MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only
OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
access : read-only
NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)
bits : 9 - 9 (1 bit)
access : read-only
UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)
access : read-only
CMP : Comparison Status (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only
SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)
access : read-only
TXFEF : Transmit FIFO Empty Flag (cleared on read)
bits : 24 - 24 (1 bit)
access : read-only
TXFFF : Transmit FIFO Full Flag (cleared on read)
bits : 25 - 25 (1 bit)
access : read-only
TXFTHF : Transmit FIFO Threshold Flag (cleared on read)
bits : 26 - 26 (1 bit)
access : read-only
RXFEF : Receive FIFO Empty Flag
bits : 27 - 27 (1 bit)
access : read-only
RXFFF : Receive FIFO Full Flag
bits : 28 - 28 (1 bit)
access : read-only
RXFTHF : Receive FIFO Threshold Flag
bits : 29 - 29 (1 bit)
access : read-only
TXFPTEF : Transmit FIFO Pointer Error Flag
bits : 30 - 30 (1 bit)
access : read-only
RXFPTEF : Receive FIFO Pointer Error Flag
bits : 31 - 31 (1 bit)
access : read-only
SPI Interrupt Enable Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)
access : write-only
UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
CMP : Comparison Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
TXFEF : TXFEF Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
SPI Interrupt Disable Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)
access : write-only
UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
CMP : Comparison Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
TXFEF : TXFEF Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
SPI Interrupt Mask Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)
access : read-only
UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
CMP : Comparison Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
TXFEF : TXFEF Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
TXFFF : TXFFF Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
TXFTHF : TXFTHF Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
RXFEF : RXFEF Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
RXFFF : RXFFF Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
RXFTHF : RXFTHF Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
TXFPTEF : TXFPTEF Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
RXFPTEF : RXFPTEF Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
SPI Chip Select Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
SPI Chip Select Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
SPI FIFO Mode Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRDYM : Transmit Data Register Empty Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ONE_DATA
TDRE will be at level '1' when at least one data can be written in the Transmit FIFO.
1 : TWO_DATA
TDRE will be at level '1' when at least two data can be written in the Transmit FIFO.Cannot be used if FLEX_SPI_MR.PS =1.
End of enumeration elements list.
RXRDYM : Receive Data Register Full Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : ONE_DATA
RDRF will be at level '1' when at least one unread data is in the Receive FIFO.
0x1 : TWO_DATA
RDRF will be at level '1' when at least two unread data are in the Receive FIFO.Cannot be used if FLEX_SPI_MR.PS =1.
0x2 : FOUR_DATA
RDRF will be at level '1' when at least four unread data are in the Receive FIFO.Cannot be used when FLEX_SPI_CSRx.BITS is greater than 0, or if FLEX_SPI_MR.MSTR =1, or if FLEX_SPI_MR.PS =1.
End of enumeration elements list.
TXFTHRES : Transmit FIFO Threshold
bits : 16 - 21 (6 bit)
access : read-write
RXFTHRES : Receive FIFO Threshold
bits : 24 - 29 (6 bit)
access : read-write
SPI FIFO Level Register
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFL : Transmit FIFO Level
bits : 0 - 5 (6 bit)
access : read-only
RXFL : Receive FIFO Level
bits : 16 - 21 (6 bit)
access : read-only
SPI Comparison Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : First Comparison Value for Received Character
bits : 0 - 15 (16 bit)
access : read-write
VAL2 : Second Comparison Value for Received Character
bits : 16 - 31 (16 bit)
access : read-write
SPI Write Protection Mode Register
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x535049 : PASSWD
Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0
End of enumeration elements list.
SPI Write Protection Status Register
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only
TWI Control Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only
STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only
MSEN : TWI Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only
MSDIS : TWI Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only
SVEN : TWI Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only
SVDIS : TWI Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only
QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)
access : write-only
SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only
HSEN : TWI High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only
HSDIS : TWI High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only
SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)
access : write-only
SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)
access : write-only
PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)
access : write-only
PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)
access : write-only
PECRQ : PEC Request
bits : 14 - 14 (1 bit)
access : write-only
CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only
ACMEN : Alternative Command Mode Enable
bits : 16 - 16 (1 bit)
access : write-only
ACMDIS : Alternative Command Mode Disable
bits : 17 - 17 (1 bit)
access : write-only
THRCLR : Transmit Holding Register Clear
bits : 24 - 24 (1 bit)
access : write-only
LOCKCLR : Lock Clear
bits : 26 - 26 (1 bit)
access : write-only
FIFOEN : FIFO Enable
bits : 28 - 28 (1 bit)
access : write-only
FIFODIS : FIFO Disable
bits : 29 - 29 (1 bit)
access : write-only
TWI Control Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0
START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only
STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only
MSEN : TWI Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only
MSDIS : TWI Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only
SVEN : TWI Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only
SVDIS : TWI Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only
QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)
access : write-only
SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only
HSEN : TWI High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only
HSDIS : TWI High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only
SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)
access : write-only
SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)
access : write-only
PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)
access : write-only
PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)
access : write-only
PECRQ : PEC Request
bits : 14 - 14 (1 bit)
access : write-only
CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only
ACMEN : Alternative Command Mode Enable
bits : 16 - 16 (1 bit)
access : write-only
ACMDIS : Alternative Command Mode Disable
bits : 17 - 17 (1 bit)
access : write-only
TXFCLR : Transmit FIFO Clear
bits : 24 - 24 (1 bit)
access : write-only
RXFCLR : Receive FIFO Clear
bits : 25 - 25 (1 bit)
access : write-only
TXFLCLR : Transmit FIFO Lock CLEAR
bits : 26 - 26 (1 bit)
access : write-only
FIFOEN : FIFO Enable
bits : 28 - 28 (1 bit)
access : write-only
FIFODIS : FIFO Disable
bits : 29 - 29 (1 bit)
access : write-only
TWI Master Mode Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No internal device address
0x1 : 1_BYTE
One-byte internal device address
0x2 : 2_BYTE
Two-byte internal device address
0x3 : 3_BYTE
Three-byte internal device address
End of enumeration elements list.
MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write
DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write
TWI Slave Mode Register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NACKEN : Slave Receiver Data Phase NACK Enable
bits : 0 - 0 (1 bit)
access : read-write
SMDA : SMBus Default Address
bits : 2 - 2 (1 bit)
access : read-write
SMHH : SMBus Host Header
bits : 3 - 3 (1 bit)
access : read-write
SCLWSDIS : Clock Wait State Disable
bits : 6 - 6 (1 bit)
access : read-write
MASK : Slave Address Mask
bits : 8 - 14 (7 bit)
access : read-write
SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write
SADR1EN : Slave Address 1 Enable
bits : 28 - 28 (1 bit)
access : read-write
SADR2EN : Slave Address 2 Enable
bits : 29 - 29 (1 bit)
access : read-write
SADR3EN : Slave Address 3 Enable
bits : 30 - 30 (1 bit)
access : read-write
DATAMEN : Data Matching Enable
bits : 31 - 31 (1 bit)
access : read-write
TWI Internal Address Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write
TWI Clock Waveform Generator Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write
CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write
CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write
BRSRCCLK : Bit Rate Source Clock
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK
The peripheral clock is the source clock for the bit rate generation.
1 : GCLK
GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
End of enumeration elements list.
HOLD : TWD Hold Time Versus TWCK Falling
bits : 24 - 28 (5 bit)
access : read-write
TWI Status Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed (cleared by writing FLEX_TWI_THR)
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)
bits : 1 - 1 (1 bit)
access : read-only
TXRDY : Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)
bits : 2 - 2 (1 bit)
access : read-only
SVREAD : Slave Read
bits : 3 - 3 (1 bit)
access : read-only
SVACC : Slave Access
bits : 4 - 4 (1 bit)
access : read-only
GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)
access : read-only
OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)
access : read-only
UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)
access : read-only
NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only
ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)
access : read-only
SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)
access : read-only
EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only
MCACK : Master Code Acknowledge (cleared on read)
bits : 16 - 16 (1 bit)
access : read-only
TOUT : Timeout Error (cleared on read)
bits : 18 - 18 (1 bit)
access : read-only
PECERR : PEC Error (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only
SMBDAM : SMBus Default Address Match (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only
SMBHHM : SMBus Host Header Address Match (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only
LOCK : TWI Lock Due to Frame Errors
bits : 23 - 23 (1 bit)
access : read-only
SCL : SCL Line Value
bits : 24 - 24 (1 bit)
access : read-only
SDA : SDA Line Value
bits : 25 - 25 (1 bit)
access : read-only
TWI Status Register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0
TXCOMP : Transmission Completed (cleared by writing FLEX_TWI_THR)
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)
bits : 1 - 1 (1 bit)
access : read-only
TXRDY : Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)
bits : 2 - 2 (1 bit)
access : read-only
SVREAD : Slave Read
bits : 3 - 3 (1 bit)
access : read-only
SVACC : Slave Access
bits : 4 - 4 (1 bit)
access : read-only
GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)
access : read-only
OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)
access : read-only
UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)
access : read-only
NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only
ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)
access : read-only
SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)
access : read-only
EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only
MCACK : Master Code Acknowledge (cleared on read)
bits : 16 - 16 (1 bit)
access : read-only
TOUT : Timeout Error (cleared on read)
bits : 18 - 18 (1 bit)
access : read-only
PECERR : PEC Error (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only
SMBDAM : SMBus Default Address Match (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only
SMBHHM : SMBus Host Header Address Match (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only
TXFLOCK : Transmit FIFO Lock
bits : 23 - 23 (1 bit)
access : read-only
SCL : SCL Line Value
bits : 24 - 24 (1 bit)
access : read-only
SDA : SDA Line Value
bits : 25 - 25 (1 bit)
access : read-only
TWI Interrupt Enable Register
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
UNRE : Underrun Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
MCACK : Master Code Acknowledge Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
TOUT : Timeout Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
PECERR : PEC Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
SMBDAM : SMBus Default Address Match Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
SMBHHM : SMBus Host Header Address Match Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
TWI Interrupt Disable Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
UNRE : Underrun Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
MCACK : Master Code Acknowledge Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
TOUT : Timeout Error Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
PECERR : PEC Error Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
SMBDAM : SMBus Default Address Match Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
SMBHHM : SMBus Host Header Address Match Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
TWI Interrupt Mask Register
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
UNRE : Underrun Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
ENDRX : End of Receive Buffer Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
ENDTX : End of Transmit Buffer Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
MCACK : Master Code Acknowledge Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
TOUT : Timeout Error Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
PECERR : PEC Error Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
SMBDAM : SMBus Default Address Match Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
SMBHHM : SMBus Host Header Address Match Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
TWI Receive Holding Register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only
TWI Receive Holding Register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0
RXDATA0 : Master or Slave Receive Holding Data 0
bits : 0 - 7 (8 bit)
access : read-only
RXDATA1 : Master or Slave Receive Holding Data 1
bits : 8 - 15 (8 bit)
access : read-only
RXDATA2 : Master or Slave Receive Holding Data 2
bits : 16 - 23 (8 bit)
access : read-only
RXDATA3 : Master or Slave Receive Holding Data 3
bits : 24 - 31 (8 bit)
access : read-only
TWI Transmit Holding Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only
TWI Transmit Holding Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : FIFO_ENABLED
reset_Mask : 0x0
TXDATA0 : Master or Slave Transmit Holding Data 0
bits : 0 - 7 (8 bit)
access : write-only
TXDATA1 : Master or Slave Transmit Holding Data 1
bits : 8 - 15 (8 bit)
access : write-only
TXDATA2 : Master or Slave Transmit Holding Data 2
bits : 16 - 23 (8 bit)
access : write-only
TXDATA3 : Master or Slave Transmit Holding Data 3
bits : 24 - 31 (8 bit)
access : write-only
TWI SMBus Timing Register
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : SMBus Clock Prescaler
bits : 0 - 3 (4 bit)
access : read-write
TLOWS : Slave Clock Stretch Maximum Cycles
bits : 8 - 15 (8 bit)
access : read-write
TLOWM : Master Clock Stretch Maximum Cycles
bits : 16 - 23 (8 bit)
access : read-write
THMAX : Clock High Maximum Cycles
bits : 24 - 31 (8 bit)
access : read-write
TWI Alternative Command Register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAL : Data Length
bits : 0 - 7 (8 bit)
access : read-write
DIR : Transfer Direction
bits : 8 - 8 (1 bit)
access : read-write
PEC : PEC Request (SMBus Mode only)
bits : 9 - 9 (1 bit)
access : read-write
NDATAL : Next Data Length
bits : 16 - 23 (8 bit)
access : read-write
NDIR : Next Transfer Direction
bits : 24 - 24 (1 bit)
access : read-write
NPEC : Next PEC Request (SMBus Mode only)
bits : 25 - 25 (1 bit)
access : read-write
TWI Filter Register
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT : RX Digital Filter
bits : 0 - 0 (1 bit)
access : read-write
PADFEN : PAD Filter Enable
bits : 1 - 1 (1 bit)
access : read-write
PADFCFG : PAD Filter Config
bits : 2 - 2 (1 bit)
access : read-write
THRES : Digital Filter Threshold
bits : 8 - 10 (3 bit)
access : read-write
TWI SleepWalking Matching Register
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR1 : Slave Address 1
bits : 0 - 6 (7 bit)
access : read-write
SADR2 : Slave Address 2
bits : 8 - 14 (7 bit)
access : read-write
SADR3 : Slave Address 3
bits : 16 - 22 (7 bit)
access : read-write
DATAM : Data Match
bits : 24 - 31 (8 bit)
access : read-write
TWI FIFO Mode Register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRDYM : Transmitter Ready Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : ONE_DATA
TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO
0x1 : TWO_DATA
TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO
0x2 : FOUR_DATA
TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO
End of enumeration elements list.
RXRDYM : Receiver Ready Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : ONE_DATA
RXRDY will be at level '1' when at least one unread data is in the Receive FIFO
0x1 : TWO_DATA
RXRDY will be at level '1' when at least two unread data are in the Receive FIFO
0x2 : FOUR_DATA
RXRDY will be at level '1' when at least four unread data are in the Receive FIFO
End of enumeration elements list.
TXFTHRES : Transmit FIFO Threshold
bits : 16 - 21 (6 bit)
access : read-write
RXFTHRES : Receive FIFO Threshold
bits : 24 - 29 (6 bit)
access : read-write
TWI FIFO Level Register
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFL : Transmit FIFO Level
bits : 0 - 5 (6 bit)
access : read-only
RXFL : Receive FIFO Level
bits : 16 - 21 (6 bit)
access : read-only
TWI FIFO Status Register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : Transmit FIFO Empty Flag (cleared on read)
bits : 0 - 0 (1 bit)
access : read-only
TXFFF : Transmit FIFO Full Flag (cleared on read)
bits : 1 - 1 (1 bit)
access : read-only
TXFTHF : Transmit FIFO Threshold Flag (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only
RXFEF : Receive FIFO Empty Flag
bits : 3 - 3 (1 bit)
access : read-only
RXFFF : Receive FIFO Full Flag
bits : 4 - 4 (1 bit)
access : read-only
RXFTHF : Receive FIFO Threshold Flag
bits : 5 - 5 (1 bit)
access : read-only
TXFPTEF : Transmit FIFO Pointer Error Flag
bits : 6 - 6 (1 bit)
access : read-only
RXFPTEF : Receive FIFO Pointer Error Flag
bits : 7 - 7 (1 bit)
access : read-only
TWI FIFO Interrupt Enable Register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
TWI FIFO Interrupt Disable Register
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXFFF : TXFFF Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXFTHF : TXFTHF Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
RXFEF : RXFEF Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
RXFFF : RXFFF Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
RXFTHF : RXFTHF Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
TXFPTEF : TXFPTEF Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
RXFPTEF : RXFPTEF Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
TWI FIFO Interrupt Mask Register
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXFEF : TXFEF Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
TXFFF : TXFFF Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXFTHF : TXFTHF Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
RXFEF : RXFEF Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
RXFFF : RXFFF Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
RXFTHF : RXFTHF Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
TXFPTEF : TXFPTEF Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
RXFPTEF : RXFPTEF Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
TWI Write Protection Mode Register
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x545749 : PASSWD
Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0
End of enumeration elements list.
TWI Write Protection Status Register
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 31 (24 bit)
access : read-only
SPI Chip Select Register
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
SPI Chip Select Register
address_offset : 0xC94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write
NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write
CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write
CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write
BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x0 : 8_BIT
8 bits for transfer
0x1 : 9_BIT
9 bits for transfer
0x2 : 10_BIT
10 bits for transfer
0x3 : 11_BIT
11 bits for transfer
0x4 : 12_BIT
12 bits for transfer
0x5 : 13_BIT
13 bits for transfer
0x6 : 14_BIT
14 bits for transfer
0x7 : 15_BIT
15 bits for transfer
0x8 : 16_BIT
16 bits for transfer
End of enumeration elements list.
SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write
DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write
DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write
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