\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
START : Start Conversion
bits : 1 - 1 (1 bit)
access : write-only
TSCALIB : Touchscreen Calibration
bits : 2 - 2 (1 bit)
access : write-only
CMPRST : Comparison Restart
bits : 4 - 4 (1 bit)
access : write-only
Channel Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
access : write-only
CH2 : Channel 2 Enable
bits : 2 - 2 (1 bit)
access : write-only
CH3 : Channel 3 Enable
bits : 3 - 3 (1 bit)
access : write-only
CH4 : Channel 4 Enable
bits : 4 - 4 (1 bit)
access : write-only
CH5 : Channel 5 Enable
bits : 5 - 5 (1 bit)
access : write-only
CH6 : Channel 6 Enable
bits : 6 - 6 (1 bit)
access : write-only
CH7 : Channel 7 Enable
bits : 7 - 7 (1 bit)
access : write-only
CH8 : Channel 8 Enable
bits : 8 - 8 (1 bit)
access : write-only
CH9 : Channel 9 Enable
bits : 9 - 9 (1 bit)
access : write-only
CH10 : Channel 10 Enable
bits : 10 - 10 (1 bit)
access : write-only
CH11 : Channel 11 Enable
bits : 11 - 11 (1 bit)
access : write-only
Channel Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
access : write-only
CH2 : Channel 2 Disable
bits : 2 - 2 (1 bit)
access : write-only
CH3 : Channel 3 Disable
bits : 3 - 3 (1 bit)
access : write-only
CH4 : Channel 4 Disable
bits : 4 - 4 (1 bit)
access : write-only
CH5 : Channel 5 Disable
bits : 5 - 5 (1 bit)
access : write-only
CH6 : Channel 6 Disable
bits : 6 - 6 (1 bit)
access : write-only
CH7 : Channel 7 Disable
bits : 7 - 7 (1 bit)
access : write-only
CH8 : Channel 8 Disable
bits : 8 - 8 (1 bit)
access : write-only
CH9 : Channel 9 Disable
bits : 9 - 9 (1 bit)
access : write-only
CH10 : Channel 10 Disable
bits : 10 - 10 (1 bit)
access : write-only
CH11 : Channel 11 Disable
bits : 11 - 11 (1 bit)
access : write-only
Channel Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
access : read-only
CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
access : read-only
CH2 : Channel 2 Status
bits : 2 - 2 (1 bit)
access : read-only
CH3 : Channel 3 Status
bits : 3 - 3 (1 bit)
access : read-only
CH4 : Channel 4 Status
bits : 4 - 4 (1 bit)
access : read-only
CH5 : Channel 5 Status
bits : 5 - 5 (1 bit)
access : read-only
CH6 : Channel 6 Status
bits : 6 - 6 (1 bit)
access : read-only
CH7 : Channel 7 Status
bits : 7 - 7 (1 bit)
access : read-only
CH8 : Channel 8 Status
bits : 8 - 8 (1 bit)
access : read-only
CH9 : Channel 9 Status
bits : 9 - 9 (1 bit)
access : read-only
CH10 : Channel 10 Status
bits : 10 - 10 (1 bit)
access : read-only
CH11 : Channel 11 Status
bits : 11 - 11 (1 bit)
access : read-only
Channel Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Last Converted Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LDATA : Last Data Converted
bits : 0 - 15 (16 bit)
access : read-only
CHNBOSR : Channel Number in Oversampling Mode
bits : 24 - 28 (5 bit)
access : read-only
Channel Data Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Enable 0
bits : 0 - 0 (1 bit)
access : write-only
EOC1 : End of Conversion Interrupt Enable 1
bits : 1 - 1 (1 bit)
access : write-only
EOC2 : End of Conversion Interrupt Enable 2
bits : 2 - 2 (1 bit)
access : write-only
EOC3 : End of Conversion Interrupt Enable 3
bits : 3 - 3 (1 bit)
access : write-only
EOC4 : End of Conversion Interrupt Enable 4
bits : 4 - 4 (1 bit)
access : write-only
EOC5 : End of Conversion Interrupt Enable 5
bits : 5 - 5 (1 bit)
access : write-only
EOC6 : End of Conversion Interrupt Enable 6
bits : 6 - 6 (1 bit)
access : write-only
EOC7 : End of Conversion Interrupt Enable 7
bits : 7 - 7 (1 bit)
access : write-only
EOC8 : End of Conversion Interrupt Enable 8
bits : 8 - 8 (1 bit)
access : write-only
EOC9 : End of Conversion Interrupt Enable 9
bits : 9 - 9 (1 bit)
access : write-only
EOC10 : End of Conversion Interrupt Enable 10
bits : 10 - 10 (1 bit)
access : write-only
EOC11 : End of Conversion Interrupt Enable 11
bits : 11 - 11 (1 bit)
access : write-only
LCCHG : Last Channel Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
XRDY : Touchscreen Measure XPOS Ready Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
YRDY : Touchscreen Measure YPOS Ready Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
PRDY : Touchscreen Measure Pressure Ready Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
GOVRE : General Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
COMPE : Comparison Event Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
PEN : Pen Contact Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
NOPEN : No Pen Contact Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
Channel Data Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Disable 0
bits : 0 - 0 (1 bit)
access : write-only
EOC1 : End of Conversion Interrupt Disable 1
bits : 1 - 1 (1 bit)
access : write-only
EOC2 : End of Conversion Interrupt Disable 2
bits : 2 - 2 (1 bit)
access : write-only
EOC3 : End of Conversion Interrupt Disable 3
bits : 3 - 3 (1 bit)
access : write-only
EOC4 : End of Conversion Interrupt Disable 4
bits : 4 - 4 (1 bit)
access : write-only
EOC5 : End of Conversion Interrupt Disable 5
bits : 5 - 5 (1 bit)
access : write-only
EOC6 : End of Conversion Interrupt Disable 6
bits : 6 - 6 (1 bit)
access : write-only
EOC7 : End of Conversion Interrupt Disable 7
bits : 7 - 7 (1 bit)
access : write-only
EOC8 : End of Conversion Interrupt Disable 8
bits : 8 - 8 (1 bit)
access : write-only
EOC9 : End of Conversion Interrupt Disable 9
bits : 9 - 9 (1 bit)
access : write-only
EOC10 : End of Conversion Interrupt Disable 10
bits : 10 - 10 (1 bit)
access : write-only
EOC11 : End of Conversion Interrupt Disable 11
bits : 11 - 11 (1 bit)
access : write-only
LCCHG : Last Channel Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
XRDY : Touchscreen Measure XPOS Ready Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
YRDY : Touchscreen Measure YPOS Ready Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
PRDY : Touchscreen Measure Pressure Ready Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
GOVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
COMPE : Comparison Event Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
PEN : Pen Contact Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
NOPEN : No Pen Contact Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion Interrupt Mask 0
bits : 0 - 0 (1 bit)
access : read-only
EOC1 : End of Conversion Interrupt Mask 1
bits : 1 - 1 (1 bit)
access : read-only
EOC2 : End of Conversion Interrupt Mask 2
bits : 2 - 2 (1 bit)
access : read-only
EOC3 : End of Conversion Interrupt Mask 3
bits : 3 - 3 (1 bit)
access : read-only
EOC4 : End of Conversion Interrupt Mask 4
bits : 4 - 4 (1 bit)
access : read-only
EOC5 : End of Conversion Interrupt Mask 5
bits : 5 - 5 (1 bit)
access : read-only
EOC6 : End of Conversion Interrupt Mask 6
bits : 6 - 6 (1 bit)
access : read-only
EOC7 : End of Conversion Interrupt Mask 7
bits : 7 - 7 (1 bit)
access : read-only
EOC8 : End of Conversion Interrupt Mask 8
bits : 8 - 8 (1 bit)
access : read-only
EOC9 : End of Conversion Interrupt Mask 9
bits : 9 - 9 (1 bit)
access : read-only
EOC10 : End of Conversion Interrupt Mask 10
bits : 10 - 10 (1 bit)
access : read-only
EOC11 : End of Conversion Interrupt Mask 11
bits : 11 - 11 (1 bit)
access : read-only
LCCHG : Last Channel Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : read-only
XRDY : Touchscreen Measure XPOS Ready Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
YRDY : Touchscreen Measure YPOS Ready Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
PRDY : Touchscreen Measure Pressure Ready Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
GOVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
COMPE : Comparison Event Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
PEN : Pen Contact Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
NOPEN : No Pen Contact Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
Channel Data Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EOC0 : End of Conversion 0 (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only
EOC1 : End of Conversion 1 (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only
EOC2 : End of Conversion 2 (automatically set / cleared)
bits : 2 - 2 (1 bit)
access : read-only
EOC3 : End of Conversion 3 (automatically set / cleared)
bits : 3 - 3 (1 bit)
access : read-only
EOC4 : End of Conversion 4 (automatically set / cleared)
bits : 4 - 4 (1 bit)
access : read-only
EOC5 : End of Conversion 5 (automatically set / cleared)
bits : 5 - 5 (1 bit)
access : read-only
EOC6 : End of Conversion 6 (automatically set / cleared)
bits : 6 - 6 (1 bit)
access : read-only
EOC7 : End of Conversion 7 (automatically set / cleared)
bits : 7 - 7 (1 bit)
access : read-only
EOC8 : End of Conversion 8 (automatically set / cleared)
bits : 8 - 8 (1 bit)
access : read-only
EOC9 : End of Conversion 9 (automatically set / cleared)
bits : 9 - 9 (1 bit)
access : read-only
EOC10 : End of Conversion 10 (automatically set / cleared)
bits : 10 - 10 (1 bit)
access : read-only
EOC11 : End of Conversion 11 (automatically set / cleared)
bits : 11 - 11 (1 bit)
access : read-only
LCCHG : Last Channel Change (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only
XRDY : Touchscreen XPOS Measure Ready (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only
YRDY : Touchscreen YPOS Measure Ready (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only
PRDY : Touchscreen Pressure Measure Ready (cleared on read)
bits : 22 - 22 (1 bit)
access : read-only
DRDY : Data Ready (automatically set / cleared)
bits : 24 - 24 (1 bit)
access : read-only
GOVRE : General Overrun Error (cleared on read)
bits : 25 - 25 (1 bit)
access : read-only
COMPE : Comparison Event (cleared on read)
bits : 26 - 26 (1 bit)
access : read-only
PEN : Pen contact (cleared on read)
bits : 29 - 29 (1 bit)
access : read-only
NOPEN : No Pen Contact (cleared on read)
bits : 30 - 30 (1 bit)
access : read-only
PENS : Pen Detect Status
bits : 31 - 31 (1 bit)
access : read-only
Last Channel Trigger Mode Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUALTRIG : Dual Trigger ON
bits : 0 - 0 (1 bit)
access : read-write
CMPMOD : Last Channel Comparison Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : LOW
Generates the LCCHG flag in ADC_ISR when the converted data is lower than the low threshold of the window.
0x1 : HIGH
Generates the LCCHG flag in ADC_ISR when the converted data is higher than the high threshold of the window.
0x2 : IN
Generates the LCCHG flag in ADC_ISR when the converted data is in the comparison window.
0x3 : OUT
Generates the LCCHG flag in ADC_ISR when the converted data is out of the comparison window.
End of enumeration elements list.
Channel Data Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Last Channel Compare Window Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWTHRES : Low Threshold
bits : 0 - 11 (12 bit)
access : read-write
HIGHTHRES : High Threshold
bits : 16 - 27 (12 bit)
access : read-write
Channel Data Register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Overrun Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVRE0 : Overrun Error 0
bits : 0 - 0 (1 bit)
access : read-only
OVRE1 : Overrun Error 1
bits : 1 - 1 (1 bit)
access : read-only
OVRE2 : Overrun Error 2
bits : 2 - 2 (1 bit)
access : read-only
OVRE3 : Overrun Error 3
bits : 3 - 3 (1 bit)
access : read-only
OVRE4 : Overrun Error 4
bits : 4 - 4 (1 bit)
access : read-only
OVRE5 : Overrun Error 5
bits : 5 - 5 (1 bit)
access : read-only
OVRE6 : Overrun Error 6
bits : 6 - 6 (1 bit)
access : read-only
OVRE7 : Overrun Error 7
bits : 7 - 7 (1 bit)
access : read-only
OVRE8 : Overrun Error 8
bits : 8 - 8 (1 bit)
access : read-only
OVRE9 : Overrun Error 9
bits : 9 - 9 (1 bit)
access : read-only
OVRE10 : Overrun Error 10
bits : 10 - 10 (1 bit)
access : read-only
OVRE11 : Overrun Error 11
bits : 11 - 11 (1 bit)
access : read-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0x0 : ADC_TRIG0
ADTRG
0x1 : ADC_TRIG1
TIOA0
0x2 : ADC_TRIG2
TIOA1
0x3 : ADC_TRIG3
TIOA2
0x4 : ADC_TRIG4
PWM event line 0
0x5 : ADC_TRIG5
PWM event line 1
0x6 : ADC_TRIG6
TIOA3
0x7 : ADC_TRIG7
RTCOUT0
End of enumeration elements list.
SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions.
1 : SLEEP
Sleep Mode: The wakeup time can be modified by programming the FWUP bit.
End of enumeration elements list.
FWUP : Fast Wakeup
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : OFF
If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions
1 : ON
If SLEEP is 1, then Fast Wakeup Sleep mode: The voltage reference is ON between conversions and ADC core is OFF
End of enumeration elements list.
PRESCAL : Prescaler Rate Selection
bits : 8 - 15 (8 bit)
access : read-write
STARTUP : Startup Time
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : SUT0
0 periods of ADCCLK
0x1 : SUT8
8 periods of ADCCLK
0x2 : SUT16
16 periods of ADCCLK
0x3 : SUT24
24 periods of ADCCLK
0x4 : SUT64
64 periods of ADCCLK
0x5 : SUT80
80 periods of ADCCLK
0x6 : SUT96
96 periods of ADCCLK
0x7 : SUT112
112 periods of ADCCLK
0x8 : SUT512
512 periods of ADCCLK
0x9 : SUT576
576 periods of ADCCLK
0xA : SUT640
640 periods of ADCCLK
0xB : SUT704
704 periods of ADCCLK
0xC : SUT768
768 periods of ADCCLK
0xD : SUT832
832 periods of ADCCLK
0xE : SUT896
896 periods of ADCCLK
0xF : SUT960
960 periods of ADCCLK
End of enumeration elements list.
ANACH : Analog Change
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NONE
No analog change on channel switching: DIFF0 is used for all channels.
1 : ALLOWED
Allows different analog settings for each channel. See ADC Channel Offset RegisterChannel Configuration Register.
End of enumeration elements list.
TRACKTIM : Tracking Time
bits : 24 - 27 (4 bit)
access : read-write
TRANSFER : Transfer Time
bits : 28 - 29 (2 bit)
access : read-write
MAXSPEED : Maximum Sampling Rate Enable in Freerun Mode
bits : 30 - 30 (1 bit)
access : read-write
USEQ : Use Sequence Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NUM_ORDER
Normal mode: The controller converts channels in a simple numeric order depending only on the channel index.
1 : REG_ORDER
User Sequence mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times.
End of enumeration elements list.
Extended Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPMODE : Comparison Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : LOW
When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode.
0x1 : HIGH
When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode.
0x2 : IN
When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode.
0x3 : OUT
When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR or, in Partial Wakeup mode, defines the conditions to exit system from Wait mode.
End of enumeration elements list.
CMPTYPE : Comparison Type
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FLAG_ONLY
Any conversion is performed and comparison function drives the COMPE flag.
1 : START_CONDITION
Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set.
End of enumeration elements list.
CMPSEL : Comparison Selected Channel
bits : 4 - 7 (4 bit)
access : read-write
CMPALL : Compare All Channels
bits : 9 - 9 (1 bit)
access : read-write
CMPFILTER : Compare Event Filtering
bits : 12 - 13 (2 bit)
access : read-write
OSR : Over Sampling Rate
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NO_AVERAGE
No averaging. ADC sample rate is maximum.
0x1 : OSR4
1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
0x2 : OSR16
2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
End of enumeration elements list.
ASTE : Averaging on Single Trigger Event
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : MULTI_TRIG_AVERAGE
The average requests several trigger events.
1 : SINGLE_TRIG_AVERAGE
The average requests only one trigger event.
End of enumeration elements list.
SRCCLK : External Clock Selection
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : PERIPH_CLK
The peripheral clock is the source for the ADC prescaler.
1 : GCLK
GCLK is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock.
End of enumeration elements list.
TAG : Tag of ADC_LCDR
bits : 24 - 24 (1 bit)
access : read-write
SIGNMODE : Sign Mode
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0x0 : SE_UNSG_DF_SIGN
Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions.
0x1 : SE_SIGN_DF_UNSG
Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions.
0x2 : ALL_UNSIGNED
All channels: Unsigned conversions.
0x3 : ALL_SIGNED
All channels: Signed conversions.
End of enumeration elements list.
ADCMODE : ADC Running Mode
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal mode of operation.
0x1 : OFFSET_ERROR
Offset Error mode to measure the offset error. See Table 7-6.
0x2 : GAIN_ERROR_HIGH
Gain Error mode to measure the gain error. See Table 7-6.
0x3 : GAIN_ERROR_LOW
Gain Error mode to measure the gain error. See Table 7-6.
End of enumeration elements list.
Channel Data Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Compare Window Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWTHRES : Low Threshold
bits : 0 - 13 (14 bit)
access : read-write
HIGHTHRES : High Threshold
bits : 16 - 29 (14 bit)
access : read-write
Channel Data Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Offset Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFF0 : Differential Inputs for Channel 0
bits : 16 - 16 (1 bit)
access : read-write
DIFF1 : Differential Inputs for Channel 1
bits : 17 - 17 (1 bit)
access : read-write
DIFF2 : Differential Inputs for Channel 2
bits : 18 - 18 (1 bit)
access : read-write
DIFF3 : Differential Inputs for Channel 3
bits : 19 - 19 (1 bit)
access : read-write
DIFF4 : Differential Inputs for Channel 4
bits : 20 - 20 (1 bit)
access : read-write
DIFF5 : Differential Inputs for Channel 5
bits : 21 - 21 (1 bit)
access : read-write
DIFF6 : Differential Inputs for Channel 6
bits : 22 - 22 (1 bit)
access : read-write
DIFF7 : Differential Inputs for Channel 7
bits : 23 - 23 (1 bit)
access : read-write
DIFF8 : Differential Inputs for Channel 8
bits : 24 - 24 (1 bit)
access : read-write
DIFF9 : Differential Inputs for Channel 9
bits : 25 - 25 (1 bit)
access : read-write
DIFF10 : Differential Inputs for Channel 10
bits : 26 - 26 (1 bit)
access : read-write
DIFF11 : Differential Inputs for Channel 11
bits : 27 - 27 (1 bit)
access : read-write
Channel Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Data Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Channel Sequence Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCH1 : User Sequence Number 1
bits : 0 - 3 (4 bit)
access : read-write
USCH2 : User Sequence Number 2
bits : 4 - 7 (4 bit)
access : read-write
USCH3 : User Sequence Number 3
bits : 8 - 11 (4 bit)
access : read-write
USCH4 : User Sequence Number 4
bits : 12 - 15 (4 bit)
access : read-write
USCH5 : User Sequence Number 5
bits : 16 - 19 (4 bit)
access : read-write
USCH6 : User Sequence Number 6
bits : 20 - 23 (4 bit)
access : read-write
USCH7 : User Sequence Number 7
bits : 24 - 27 (4 bit)
access : read-write
USCH8 : User Sequence Number 8
bits : 28 - 31 (4 bit)
access : read-write
Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PENDETSENS : Pen Detection Sensitivity
bits : 0 - 1 (2 bit)
access : read-write
IBCTL : ADC Bias Current Control
bits : 8 - 9 (2 bit)
access : read-write
Channel Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
Touchscreen Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSMODE : Touchscreen Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Touchscreen
0x1 : 4_WIRE_NO_PM
4-wire Touchscreen without pressure measurement
0x2 : 4_WIRE
4-wire Touchscreen with pressure measurement
0x3 : 5_WIRE
5-wire Touchscreen
End of enumeration elements list.
TSAV : Touchscreen Average
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NO_FILTER
No Filtering. Only one ADC conversion per measure
0x1 : AVG2CONV
Averages 2 ADC conversions
0x2 : AVG4CONV
Averages 4 ADC conversions
0x3 : AVG8CONV
Averages 8 ADC conversions
End of enumeration elements list.
TSFREQ : Touchscreen Frequency
bits : 8 - 11 (4 bit)
access : read-write
TSSCTIM : Touchscreen Switches Closure Time
bits : 16 - 19 (4 bit)
access : read-write
NOTSDMA : No TouchScreen DMA
bits : 22 - 22 (1 bit)
access : read-write
PENDET : Pen Contact Detection Enable
bits : 24 - 24 (1 bit)
access : read-write
PENDBC : Pen Detect Debouncing Period
bits : 28 - 31 (4 bit)
access : read-write
Touchscreen X Position Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XPOS : X Position
bits : 0 - 11 (12 bit)
access : read-only
XSCALE : Scale of XPOS
bits : 16 - 27 (12 bit)
access : read-only
Touchscreen Y Position Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
YPOS : Y Position
bits : 0 - 11 (12 bit)
access : read-only
YSCALE : Scale of YPOS
bits : 16 - 27 (12 bit)
access : read-only
Touchscreen Pressure Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Z1 : Data of Z1 Measurement
bits : 0 - 11 (12 bit)
access : read-only
Z2 : Data of Z2 Measurement
bits : 16 - 27 (12 bit)
access : read-only
Channel Sequence Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCH9 : User Sequence Number 9
bits : 0 - 3 (4 bit)
access : read-write
USCH10 : User Sequence Number 10
bits : 4 - 7 (4 bit)
access : read-write
USCH11 : User Sequence Number 11
bits : 8 - 11 (4 bit)
access : read-write
Trigger Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGMOD : Trigger Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : NO_TRIGGER
No trigger, only software trigger can start conversions
0x1 : EXT_TRIG_RISE
External trigger rising edge
0x2 : EXT_TRIG_FALL
External trigger falling edge
0x3 : EXT_TRIG_ANY
External trigger any edge
0x4 : PEN_TRIG
Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode)
0x5 : PERIOD_TRIG
ADC internal periodic trigger (see field TRGPER)
0x6 : CONTINUOUS
Continuous mode
End of enumeration elements list.
TRGPER : Trigger Period
bits : 16 - 31 (16 bit)
access : read-write
Correction Values Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETCORR : Offset Correction
bits : 0 - 15 (16 bit)
access : read-write
GAINCORR : Gain Correction
bits : 16 - 31 (16 bit)
access : read-write
Channel Error Correction Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECORR0 : Error Correction Enable for channel 0
bits : 0 - 0 (1 bit)
access : read-write
ECORR1 : Error Correction Enable for channel 1
bits : 1 - 1 (1 bit)
access : read-write
ECORR2 : Error Correction Enable for channel 2
bits : 2 - 2 (1 bit)
access : read-write
ECORR3 : Error Correction Enable for channel 3
bits : 3 - 3 (1 bit)
access : read-write
ECORR4 : Error Correction Enable for channel 4
bits : 4 - 4 (1 bit)
access : read-write
ECORR5 : Error Correction Enable for channel 5
bits : 5 - 5 (1 bit)
access : read-write
ECORR6 : Error Correction Enable for channel 6
bits : 6 - 6 (1 bit)
access : read-write
ECORR7 : Error Correction Enable for channel 7
bits : 7 - 7 (1 bit)
access : read-write
ECORR8 : Error Correction Enable for channel 8
bits : 8 - 8 (1 bit)
access : read-write
ECORR9 : Error Correction Enable for channel 9
bits : 9 - 9 (1 bit)
access : read-write
ECORR10 : Error Correction Enable for channel 10
bits : 10 - 10 (1 bit)
access : read-write
ECORR11 : Error Correction Enable for channel 11
bits : 11 - 11 (1 bit)
access : read-write
Touchscreen Correction Values Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSOFFSETCORR : Touchscreen Offset Correction
bits : 0 - 15 (16 bit)
access : read-write
TSGAINCORR : Touchscreen Gain Correction
bits : 16 - 31 (16 bit)
access : read-write
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x414443 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Channel Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted Data
bits : 0 - 13 (14 bit)
access : read-only
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