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SFR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OHCIICR

OHCIISR

SECURE

UTMICKTRIM

UTMIHSTRIM

UTMIFSTRIM

UTMISWAP

DDRCFG

CAN

SN0

SN1

AICREDIR

L2CC_HRAMC

I2SCLKSEL

QSPICLK_REG


OHCIICR

OHCI Interrupt Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OHCIICR OHCIICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES0 RES1 RES2 ARIE APPSTART SUSPEND_A SUSPEND_B SUSPEND_C UDPPUDIS HSIC_SEL

RES0 : USB PORTx RESET
bits : 0 - 0 (1 bit)
access : read-write

RES1 : USB PORTx RESET
bits : 1 - 1 (1 bit)
access : read-write

RES2 : USB PORTx RESET
bits : 2 - 2 (1 bit)
access : read-write

ARIE : OHCI Asynchronous Resume Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

APPSTART : Reserved
bits : 5 - 5 (1 bit)
access : read-write

SUSPEND_A : USB PORT A
bits : 8 - 8 (1 bit)
access : read-write

SUSPEND_B : USB PORT B
bits : 9 - 9 (1 bit)
access : read-write

SUSPEND_C : USB PORT C
bits : 10 - 10 (1 bit)
access : read-write

UDPPUDIS : USB DEVICE PULLUP DISABLE
bits : 23 - 23 (1 bit)
access : read-write

HSIC_SEL : Reserved
bits : 27 - 27 (1 bit)
access : read-write


OHCIISR

OHCI Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OHCIISR OHCIISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIS0 RIS1 RIS2

RIS0 : OHCI Resume Interrupt Status Port 0
bits : 0 - 0 (1 bit)
access : read-only

RIS1 : OHCI Resume Interrupt Status Port 1
bits : 1 - 1 (1 bit)
access : read-only

RIS2 : OHCI Resume Interrupt Status Port 2
bits : 2 - 2 (1 bit)
access : read-only


SECURE

Security Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECURE SECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM FUSE

ROM : Disable Access to ROM Code
bits : 0 - 0 (1 bit)
access : read-write

FUSE : Disable Access to Fuse Controller
bits : 8 - 8 (1 bit)
access : read-write


UTMICKTRIM

UTMI Clock Trimming Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UTMICKTRIM UTMICKTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ VBG

FREQ : UTMI Reference Clock Frequency
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 12

12 MHz reference clock

0x1 : 16

16 MHz reference clock

0x2 : 24

24 MHz reference clock

End of enumeration elements list.

VBG : UTMI Band Gap Voltage Trimming
bits : 16 - 17 (2 bit)
access : read-write


UTMIHSTRIM

UTMI High-Speed Trimming Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UTMIHSTRIM UTMIHSTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQUELCH DISC SLOPE0 SLOPE1 SLOPE2

SQUELCH : UTMI HS SQUELCH Voltage Trimming
bits : 0 - 2 (3 bit)
access : read-write

DISC : UTMI Disconnect Voltage Trimming
bits : 4 - 6 (3 bit)
access : read-write

SLOPE0 : UTMI HS PORTx Transceiver Slope Trimming
bits : 8 - 10 (3 bit)
access : read-write

SLOPE1 : UTMI HS PORTx Transceiver Slope Trimming
bits : 12 - 14 (3 bit)
access : read-write

SLOPE2 : UTMI HS PORTx Transceiver Slope Trimming
bits : 16 - 18 (3 bit)
access : read-write


UTMIFSTRIM

UTMI Full-Speed Trimming Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UTMIFSTRIM UTMIFSTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RISE FALL XCVR ZN ZP

RISE : FS Transceiver Output Rising Slope Trimming
bits : 0 - 2 (3 bit)
access : read-write

FALL : FS Transceiver Output Falling Slope Trimming
bits : 4 - 6 (3 bit)
access : read-write

XCVR : FS Transceiver Crossover Voltage Trimming
bits : 8 - 9 (2 bit)
access : read-write

ZN : FS Transceiver NMOS Impedance Trimming
bits : 16 - 18 (3 bit)
access : read-write

ZP : FS Transceiver PMOS Impedance Trimming
bits : 20 - 22 (3 bit)
access : read-write


UTMISWAP

UTMI DP/DM Pin Swapping Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UTMISWAP UTMISWAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT0 PORT1 PORT2

PORT0 : PORT 0 DP/DM Pin Swapping
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

DP/DM normal pinout.

1 : SWAPPED

DP/DM swapped pinout.

End of enumeration elements list.

PORT1 : PORT 1 DP/DM Pin Swapping
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

DP/DM normal pinout.

1 : SWAPPED

DP/DM swapped pinout.

End of enumeration elements list.

PORT2 : PORT 2 DP/DM Pin Swapping
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

DP/DM normal pinout.

1 : SWAPPED

DP/DM swapped pinout.

End of enumeration elements list.


DDRCFG

DDR Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRCFG DDRCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDQIEN FDQSIEN

FDQIEN : Force DDR_DQ Input Buffer Always On
bits : 16 - 16 (1 bit)
access : read-write

FDQSIEN : Force DDR_DQS Input Buffer Always On
bits : 17 - 17 (1 bit)
access : read-write


CAN

CAN Memories Address-based Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAN CAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXT_MEM_CAN0_ADDR EXT_MEM_CAN1_ADDR

EXT_MEM_CAN0_ADDR : MSB CAN0 DMA Base Address
bits : 0 - 15 (16 bit)
access : read-write

EXT_MEM_CAN1_ADDR : MSB CAN1 DMA Base Address
bits : 16 - 31 (16 bit)
access : read-write


SN0

Serial Number 0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SN0 SN0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SN0

SN0 : Serial Number 0
bits : 0 - 31 (32 bit)
access : read-only


SN1

Serial Number 1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SN1 SN1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SN1

SN1 : Serial Number 1
bits : 0 - 31 (32 bit)
access : read-only


AICREDIR

AIC Interrupt Redirection Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AICREDIR AICREDIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSAIC AICREDIRKEY

NSAIC : Interrupt Redirection to Non-Secure AIC
bits : 0 - 0 (1 bit)
access : read-write

AICREDIRKEY : Unlock Key
bits : 1 - 31 (31 bit)
access : read-write


L2CC_HRAMC

L2CC_HRAMC1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CC_HRAMC L2CC_HRAMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM_SEL

SRAM_SEL : SRAM Selector
bits : 0 - 0 (1 bit)
access : read-write


I2SCLKSEL

I2SC Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCLKSEL I2SCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL0 CLKSEL1

CLKSEL0 : Clock Selection 0
bits : 0 - 0 (1 bit)
access : read-write

CLKSEL1 : Clock Selection 1
bits : 1 - 1 (1 bit)
access : read-write


QSPICLK_REG

QSPI Clock Pad Supply Select Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSPICLK_REG QSPICLK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUP_SEL

SUP_SEL : Supply Selection
bits : 0 - 0 (1 bit)
access : read-write



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