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UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IMR

SR

RHR

THR

BRGR

CMPR

RTOR

MR

IER

IDR

WPMR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA RETTO STTTO REQCLR

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status
bits : 8 - 8 (1 bit)
access : write-only

RETTO : Rearm Time-out
bits : 10 - 10 (1 bit)
access : write-only

STTTO : Start Time-out
bits : 11 - 11 (1 bit)
access : write-only

REQCLR : Request Clear
bits : 12 - 12 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY CMP

RXRDY : Mask RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : read-only

OVRE : Mask Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Mask Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

PARE : Mask Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Mask Time-out Interrupt
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Mask TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : read-only

CMP : Mask Comparison Interrupt
bits : 15 - 15 (1 bit)
access : read-only


SR

Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY CMP

RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only

OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Receiver Time-out
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only

CMP : Comparison Match
bits : 15 - 15 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHR

RXCHR : Received Character
bits : 0 - 7 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHR

TXCHR : Character to be Transmitted
bits : 0 - 7 (8 bit)
access : write-only


BRGR

Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRGR BRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD

CD : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write


CMPR

Comparison Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPR CMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL1 CMPMODE CMPPAR VAL2

VAL1 : First Comparison Value for Received Character
bits : 0 - 7 (8 bit)
access : read-write

CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : FLAG_ONLY

Any character is received and comparison function drives CMP flag.

1 : START_CONDITION

Comparison condition must be met to start reception.

End of enumeration elements list.

CMPPAR : Compare Parity
bits : 14 - 14 (1 bit)
access : read-write

VAL2 : Second Comparison Value for Received Character
bits : 16 - 23 (8 bit)
access : read-write


RTOR

Receiver Time-out Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTOR RTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Time-out Value
bits : 0 - 7 (8 bit)
access : read-write


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER PAR BRSRCCK CHMODE

FILTER : Receiver Digital Filter
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

UART does not filter the receive line.

1 : ENABLED

UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).

End of enumeration elements list.

PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0x0 : EVEN

Even Parity

0x1 : ODD

Odd Parity

0x2 : SPACE

Space: parity forced to 0

0x3 : MARK

Mark: parity forced to 1

0x4 : NO

No parity

End of enumeration elements list.

BRSRCCK : Baud Rate Source Clock
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : PERIPH_CLK

The baud rate is driven by the peripheral clock

1 : GCLK

The baud rate is driven by a PMC-programmable clock GCLK (see section Power Management Controller (PMC)).

End of enumeration elements list.

CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal mode

0x1 : AUTOMATIC

Automatic echo

0x2 : LOCAL_LOOPBACK

Local loopback

0x3 : REMOTE_LOOPBACK

Remote loopback

End of enumeration elements list.


IER

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY CMP

RXRDY : Enable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : Enable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only

OVRE : Enable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Enable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only

PARE : Enable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Enable Time-out Interrupt
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Enable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only

CMP : Enable Comparison Interrupt
bits : 15 - 15 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY OVRE FRAME PARE TIMEOUT TXEMPTY CMP

RXRDY : Disable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only

OVRE : Disable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Disable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only

PARE : Disable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Disable Time-out Interrupt
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Disable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only

CMP : Disable Comparison Interrupt
bits : 15 - 15 (1 bit)
access : write-only


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x554152 : PASSWD

Writing any other value in this field aborts the write operation.Always reads as 0.

End of enumeration elements list.



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