\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
PIO Mask Register (io_group = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
PIO Set Output Data Register (io_group = 0)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Mask Register (io_group = 0)
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
Secure PIO Configuration Register (io_group = 0)
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR :
bits : 16 - 17 (2 bit)
access : read-write
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
Secure PIO Pin Data Status Register (io_group = 0)
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Lock Status Register (io_group = 0)
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set Output Data Register (io_group = 0)
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Clear Output Data Register (io_group = 0)
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Output Data Status Register (io_group = 0)
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
Secure PIO Interrupt Enable Register (io_group = 0)
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Disable Register (io_group = 0)
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Mask Register (io_group = 0)
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Interrupt Status Register (io_group = 0)
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set I/O Non-Secure Register (io_group = 0)
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Non-Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Non-Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Non-Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Non-Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Non-Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Non-Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Non-Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Non-Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Non-Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Non-Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Non-Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Non-Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Non-Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Non-Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Non-Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Non-Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Non-Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Non-Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Non-Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Non-Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Non-Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Non-Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Non-Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Non-Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Non-Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Non-Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Non-Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Non-Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Non-Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Non-Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Non-Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Non-Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Set I/O Secure Register (io_group = 0)
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO I/O Security Status Register (io_group = 0)
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : I/O Security Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P1 : I/O Security Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P2 : I/O Security Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P3 : I/O Security Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P4 : I/O Security Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P5 : I/O Security Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P6 : I/O Security Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P7 : I/O Security Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P8 : I/O Security Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P9 : I/O Security Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P10 : I/O Security Status
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P11 : I/O Security Status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P12 : I/O Security Status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P13 : I/O Security Status
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P14 : I/O Security Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P15 : I/O Security Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P16 : I/O Security Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P17 : I/O Security Status
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P18 : I/O Security Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P19 : I/O Security Status
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P20 : I/O Security Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P21 : I/O Security Status
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P22 : I/O Security Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P23 : I/O Security Status
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P24 : I/O Security Status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P25 : I/O Security Status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P26 : I/O Security Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P27 : I/O Security Status
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P28 : I/O Security Status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P29 : I/O Security Status
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P30 : I/O Security Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P31 : I/O Security Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
Secure PIO I/O Freeze Configuration Register (io_group = 0)
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
Secure PIO Mask Register (io_group = 1)
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
Secure PIO Configuration Register (io_group = 1)
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR :
bits : 16 - 17 (2 bit)
access : read-write
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
Secure PIO Pin Data Status Register (io_group = 1)
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Lock Status Register (io_group = 1)
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set Output Data Register (io_group = 1)
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Clear Output Data Register (io_group = 1)
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Output Data Status Register (io_group = 1)
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
Secure PIO Interrupt Enable Register (io_group = 1)
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Disable Register (io_group = 1)
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Mask Register (io_group = 1)
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Interrupt Status Register (io_group = 1)
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set I/O Non-Secure Register (io_group = 1)
address_offset : 0x1070 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Non-Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Non-Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Non-Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Non-Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Non-Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Non-Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Non-Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Non-Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Non-Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Non-Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Non-Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Non-Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Non-Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Non-Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Non-Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Non-Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Non-Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Non-Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Non-Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Non-Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Non-Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Non-Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Non-Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Non-Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Non-Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Non-Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Non-Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Non-Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Non-Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Non-Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Non-Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Non-Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Set I/O Secure Register (io_group = 1)
address_offset : 0x1074 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO I/O Security Status Register (io_group = 1)
address_offset : 0x1078 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : I/O Security Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P1 : I/O Security Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P2 : I/O Security Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P3 : I/O Security Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P4 : I/O Security Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P5 : I/O Security Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P6 : I/O Security Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P7 : I/O Security Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P8 : I/O Security Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P9 : I/O Security Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P10 : I/O Security Status
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P11 : I/O Security Status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P12 : I/O Security Status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P13 : I/O Security Status
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P14 : I/O Security Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P15 : I/O Security Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P16 : I/O Security Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P17 : I/O Security Status
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P18 : I/O Security Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P19 : I/O Security Status
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P20 : I/O Security Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P21 : I/O Security Status
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P22 : I/O Security Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P23 : I/O Security Status
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P24 : I/O Security Status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P25 : I/O Security Status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P26 : I/O Security Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P27 : I/O Security Status
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P28 : I/O Security Status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P29 : I/O Security Status
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P30 : I/O Security Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P31 : I/O Security Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
Secure PIO I/O Freeze Configuration Register (io_group = 1)
address_offset : 0x107C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
Secure PIO Mask Register (io_group = 2)
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
Secure PIO Configuration Register (io_group = 2)
address_offset : 0x1084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR :
bits : 16 - 17 (2 bit)
access : read-write
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
Secure PIO Pin Data Status Register (io_group = 2)
address_offset : 0x1088 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Lock Status Register (io_group = 2)
address_offset : 0x108C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set Output Data Register (io_group = 2)
address_offset : 0x1090 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Clear Output Data Register (io_group = 2)
address_offset : 0x1094 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Output Data Status Register (io_group = 2)
address_offset : 0x1098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
Secure PIO Interrupt Enable Register (io_group = 2)
address_offset : 0x10A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Disable Register (io_group = 2)
address_offset : 0x10A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Mask Register (io_group = 2)
address_offset : 0x10A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Interrupt Status Register (io_group = 2)
address_offset : 0x10AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set I/O Non-Secure Register (io_group = 2)
address_offset : 0x10B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Non-Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Non-Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Non-Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Non-Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Non-Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Non-Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Non-Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Non-Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Non-Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Non-Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Non-Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Non-Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Non-Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Non-Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Non-Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Non-Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Non-Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Non-Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Non-Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Non-Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Non-Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Non-Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Non-Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Non-Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Non-Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Non-Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Non-Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Non-Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Non-Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Non-Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Non-Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Non-Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Set I/O Secure Register (io_group = 2)
address_offset : 0x10B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO I/O Security Status Register (io_group = 2)
address_offset : 0x10B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : I/O Security Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P1 : I/O Security Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P2 : I/O Security Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P3 : I/O Security Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P4 : I/O Security Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P5 : I/O Security Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P6 : I/O Security Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P7 : I/O Security Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P8 : I/O Security Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P9 : I/O Security Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P10 : I/O Security Status
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P11 : I/O Security Status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P12 : I/O Security Status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P13 : I/O Security Status
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P14 : I/O Security Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P15 : I/O Security Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P16 : I/O Security Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P17 : I/O Security Status
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P18 : I/O Security Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P19 : I/O Security Status
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P20 : I/O Security Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P21 : I/O Security Status
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P22 : I/O Security Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P23 : I/O Security Status
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P24 : I/O Security Status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P25 : I/O Security Status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P26 : I/O Security Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P27 : I/O Security Status
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P28 : I/O Security Status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P29 : I/O Security Status
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P30 : I/O Security Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P31 : I/O Security Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
Secure PIO I/O Freeze Configuration Register (io_group = 2)
address_offset : 0x10BC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
Secure PIO Mask Register (io_group = 3)
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration.
End of enumeration elements list.
Secure PIO Configuration Register (io_group = 3)
address_offset : 0x10C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR :
bits : 16 - 17 (2 bit)
access : read-write
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
Secure PIO Pin Data Status Register (io_group = 3)
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Lock Status Register (io_group = 3)
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set Output Data Register (io_group = 3)
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Clear Output Data Register (io_group = 3)
address_offset : 0x10D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Output Data Status Register (io_group = 3)
address_offset : 0x10D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
Secure PIO Interrupt Enable Register (io_group = 3)
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Disable Register (io_group = 3)
address_offset : 0x10E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Interrupt Mask Register (io_group = 3)
address_offset : 0x10E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Interrupt Status Register (io_group = 3)
address_offset : 0x10EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
Secure PIO Set I/O Non-Secure Register (io_group = 3)
address_offset : 0x10F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Non-Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Non-Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Non-Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Non-Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Non-Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Non-Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Non-Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Non-Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Non-Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Non-Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Non-Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Non-Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Non-Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Non-Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Non-Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Non-Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Non-Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Non-Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Non-Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Non-Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Non-Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Non-Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Non-Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Non-Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Non-Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Non-Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Non-Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Non-Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Non-Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Non-Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Non-Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Non-Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Set I/O Secure Register (io_group = 3)
address_offset : 0x10F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set I/O Secure
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set I/O Secure
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set I/O Secure
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set I/O Secure
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set I/O Secure
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set I/O Secure
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set I/O Secure
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set I/O Secure
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set I/O Secure
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set I/O Secure
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set I/O Secure
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set I/O Secure
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set I/O Secure
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set I/O Secure
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set I/O Secure
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set I/O Secure
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set I/O Secure
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set I/O Secure
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set I/O Secure
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set I/O Secure
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set I/O Secure
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set I/O Secure
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set I/O Secure
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set I/O Secure
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set I/O Secure
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set I/O Secure
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set I/O Secure
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set I/O Secure
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set I/O Secure
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set I/O Secure
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set I/O Secure
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set I/O Secure
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO I/O Security Status Register (io_group = 3)
address_offset : 0x10F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : I/O Security Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P1 : I/O Security Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P2 : I/O Security Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P3 : I/O Security Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P4 : I/O Security Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P5 : I/O Security Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P6 : I/O Security Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P7 : I/O Security Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P8 : I/O Security Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P9 : I/O Security Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P10 : I/O Security Status
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P11 : I/O Security Status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P12 : I/O Security Status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P13 : I/O Security Status
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P14 : I/O Security Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P15 : I/O Security Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P16 : I/O Security Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P17 : I/O Security Status
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P18 : I/O Security Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P19 : I/O Security Status
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P20 : I/O Security Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P21 : I/O Security Status
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P22 : I/O Security Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P23 : I/O Security Status
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P24 : I/O Security Status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P25 : I/O Security Status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P26 : I/O Security Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P27 : I/O Security Status
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P28 : I/O Security Status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P29 : I/O Security Status
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P30 : I/O Security Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
P31 : I/O Security Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : SECURE
The I/O line of the I/O group x is in Secure mode.
1 : NON_SECURE
The I/O line of the I/O group x is in Non-Secure mode.
End of enumeration elements list.
Secure PIO I/O Freeze Configuration Register (io_group = 3)
address_offset : 0x10FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
PIO Clear Output Data Register (io_group = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
Secure PIO Slow Clock Divider Debouncing Register
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Slow Clock Divider Selection for Debouncing
bits : 0 - 13 (14 bit)
access : read-write
Secure PIO Write Protection Mode Register
address_offset : 0x15E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x50494F : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
Secure PIO Write Protection Status Register
address_offset : 0x15E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
PIO Output Data Status Register (io_group = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
PIO Interrupt Enable Register (io_group = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Disable Register (io_group = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Mask Register (io_group = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
PIO Interrupt Status Register (io_group = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
PIO I/O Freeze Configuration Register (io_group = 0)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
PIO Configuration Register (io_group = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines.
1 : ENABLED
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines.
End of enumeration elements list.
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR : Drive Strength
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : LO
Low drive
0x2 : ME
Medium drive
0x3 : HI
High drive
End of enumeration elements list.
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
PIO Mask Register (io_group = 1)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
PIO Configuration Register (io_group = 1)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines.
1 : ENABLED
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines.
End of enumeration elements list.
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR : Drive Strength
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : LO
Low drive
0x2 : ME
Medium drive
0x3 : HI
High drive
End of enumeration elements list.
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
PIO Pin Data Status Register (io_group = 1)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Lock Status Register (io_group = 1)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Set Output Data Register (io_group = 1)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Clear Output Data Register (io_group = 1)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Output Data Status Register (io_group = 1)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
PIO Write Protection Mode Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x50494F : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
PIO Write Protection Status Register
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
PIO Interrupt Enable Register (io_group = 1)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Disable Register (io_group = 1)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Mask Register (io_group = 1)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
PIO Interrupt Status Register (io_group = 1)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
PIO I/O Freeze Configuration Register (io_group = 1)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
PIO Pin Data Status Register (io_group = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Mask Register (io_group = 2)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
PIO Configuration Register (io_group = 2)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines.
1 : ENABLED
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines.
End of enumeration elements list.
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR : Drive Strength
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : LO
Low drive
0x2 : ME
Medium drive
0x3 : HI
High drive
End of enumeration elements list.
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
PIO Pin Data Status Register (io_group = 2)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Lock Status Register (io_group = 2)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Set Output Data Register (io_group = 2)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Clear Output Data Register (io_group = 2)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Output Data Status Register (io_group = 2)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
PIO Interrupt Enable Register (io_group = 2)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Disable Register (io_group = 2)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Mask Register (io_group = 2)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
PIO Interrupt Status Register (io_group = 2)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
PIO I/O Freeze Configuration Register (io_group = 2)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
PIO Lock Status Register (io_group = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Mask Register (io_group = 3)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSK0 : PIO Line 0 Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK1 : PIO Line 1 Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK2 : PIO Line 2 Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK3 : PIO Line 3 Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK4 : PIO Line 4 Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK5 : PIO Line 5 Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK6 : PIO Line 6 Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK7 : PIO Line 7 Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK8 : PIO Line 8 Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK9 : PIO Line 9 Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK10 : PIO Line 10 Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK11 : PIO Line 11 Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK12 : PIO Line 12 Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK13 : PIO Line 13 Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK14 : PIO Line 14 Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK15 : PIO Line 15 Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK16 : PIO Line 16 Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK17 : PIO Line 17 Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK18 : PIO Line 18 Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK19 : PIO Line 19 Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK20 : PIO Line 20 Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK21 : PIO Line 21 Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK22 : PIO Line 22 Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK23 : PIO Line 23 Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK24 : PIO Line 24 Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK25 : PIO Line 25 Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK26 : PIO Line 26 Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK27 : PIO Line 27 Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK28 : PIO Line 28 Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK29 : PIO Line 29 Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK30 : PIO Line 30 Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
MSK31 : PIO Line 31 Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration.
1 : ENABLED
Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration.
End of enumeration elements list.
PIO Configuration Register (io_group = 3)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC : I/O Line Function
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : GPIO
Select the PIO mode for the selected I/O lines.
0x1 : PERIPH_A
Select the peripheral A for the selected I/O lines.
0x2 : PERIPH_B
Select the peripheral B for the selected I/O lines.
0x3 : PERIPH_C
Select the peripheral C for the selected I/O lines.
0x4 : PERIPH_D
Select the peripheral D for the selected I/O lines.
0x5 : PERIPH_E
Select the peripheral E for the selected I/O lines.
0x6 : PERIPH_F
Select the peripheral F for the selected I/O lines.
0x7 : PERIPH_G
Select the peripheral G for the selected I/O lines.
End of enumeration elements list.
DIR : Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INPUT
The selected I/O lines are pure inputs.
1 : OUTPUT
The selected I/O lines are enabled in output.
End of enumeration elements list.
PUEN : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Up is disabled for the selected I/O lines.
1 : ENABLED
Pull-Up is enabled for the selected I/O lines.
End of enumeration elements list.
PDEN : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Pull-Down is disabled for the selected I/O lines.
1 : ENABLED
Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1).
End of enumeration elements list.
IFEN : Input Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The input filter is disabled for the selected I/O lines.
1 : ENABLED
The input filter is enabled for the selected I/O lines.
End of enumeration elements list.
IFSCEN : Input Filter Slow Clock Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines.
1 : ENABLED
The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines.
End of enumeration elements list.
OPD : Open-Drain
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level.
1 : ENABLED
The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only.
End of enumeration elements list.
SCHMITT : Schmitt Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Schmitt trigger is enabled for the selected I/O lines.
1 : DISABLED
Schmitt trigger is disabled for the selected I/O lines.
End of enumeration elements list.
DRVSTR : Drive Strength
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : LO
Low drive
0x2 : ME
Medium drive
0x3 : HI
High drive
End of enumeration elements list.
EVTSEL : Event Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : FALLING
Event detection on input falling edge
0x1 : RISING
Event detection on input rising edge
0x2 : BOTH
Event detection on input both edge
0x3 : LOW
Event detection on low level input
0x4 : HIGH
Event detection on high level input
End of enumeration elements list.
PCFS : Physical Configuration Freeze Status (read-only)
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
ICFS : Interrupt Configuration Freeze Status (read-only)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_FROZEN
The fields are not frozen and can be written for this I/O line.
1 : FROZEN
The fields are frozen and cannot be written for this I/O line. Only a hardware reset can release these fields.
End of enumeration elements list.
PIO Pin Data Status Register (io_group = 3)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Data Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Data Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Data Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Data Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Data Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Data Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Data Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Data Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Data Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Data Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Data Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Data Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Data Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Data Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Data Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Data Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Data Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Data Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Data Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Data Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Data Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Data Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Data Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Data Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Data Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Data Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Data Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Data Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Data Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Data Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Data Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Data Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Lock Status Register (io_group = 3)
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only
PIO Set Output Data Register (io_group = 3)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Clear Output Data Register (io_group = 3)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only
P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only
P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only
P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only
P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only
P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only
P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only
P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only
P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only
P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only
P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only
P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only
P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only
P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only
P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only
P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only
P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only
P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only
P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only
P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only
P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only
P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only
P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only
P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only
P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only
P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only
P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only
P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only
P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only
P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only
P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only
P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only
PIO Output Data Status Register (io_group = 3)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write
P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write
P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write
P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write
P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write
P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write
P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write
P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write
P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write
P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write
P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write
P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write
P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write
P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write
P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write
P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write
P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write
P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write
P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write
P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write
P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write
P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write
P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write
P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write
P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write
P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write
P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write
P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write
P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write
P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write
P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write
P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write
PIO Interrupt Enable Register (io_group = 3)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Disable Register (io_group = 3)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only
P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only
P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only
PIO Interrupt Mask Register (io_group = 3)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only
PIO Interrupt Status Register (io_group = 3)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only
P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only
P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only
P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only
P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only
P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only
P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only
P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only
P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only
P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only
P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only
P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only
P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only
P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only
P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only
P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only
P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only
P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only
P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only
P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only
P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only
P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only
P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only
P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only
P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only
P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only
P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only
P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only
P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only
P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only
P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only
P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only
PIO I/O Freeze Configuration Register (io_group = 3)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPHY : Freeze Physical Configuration
bits : 0 - 0 (1 bit)
access : write-only
FINT : Freeze Interrupt Configuration
bits : 1 - 1 (1 bit)
access : write-only
FRZKEY : Freeze Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration:
0x494F46 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
End of enumeration elements list.
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