\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Slave 0 Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Master Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Region Top Slave 1 Register
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x1254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x12E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Region Top Slave 1 Register
address_offset : 0x1474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x14B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Master Error Interrupt Enable Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : write-only
MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : write-only
MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : write-only
MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : write-only
MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : write-only
MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : write-only
MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : write-only
MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : write-only
MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : write-only
MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : write-only
MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : write-only
MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : write-only
Master Error Interrupt Disable Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : write-only
MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : write-only
MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : write-only
MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : write-only
MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : write-only
MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : write-only
MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : write-only
MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : write-only
MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : write-only
MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : write-only
MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : write-only
MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : write-only
Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Error Interrupt Mask Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : read-only
MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : read-only
MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : read-only
MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : read-only
MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : read-only
MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : read-only
MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : read-only
MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : read-only
MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : read-only
MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : read-only
MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : read-only
MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : read-only
Master Error Status Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : read-only
MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : read-only
MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : read-only
MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : read-only
MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : read-only
MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : read-only
MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : read-only
MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : read-only
MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : read-only
MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : read-only
MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : read-only
MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Slave 0 Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Areas Split Slave 0 Register
address_offset : 0x1710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x1714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master 0 Error Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master 0 Error Address Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Slave 0 Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x1974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x19B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x1BDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Region Top Slave 1 Register
address_offset : 0x1C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protection Key (Write-only)
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x4D4154 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Security Areas Split Slave 0 Register
address_offset : 0x1E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Security Region Top Slave 1 Register
address_offset : 0x1F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Slave 0 Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x20B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x21BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x232C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Master Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Areas Split Slave 0 Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x25A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Security Region Top Slave 1 Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master 0 Error Address Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Peripheral Select 1 Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Security Peripheral Select 1 Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Security Peripheral Select 1 Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Peripheral Select 1 Register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Slave Configuration Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Master Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Slave 0 Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Priority Register B for Slave 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Security Peripheral Select 1 Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Priority Register B for Slave 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 3
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Slave 0 Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0xA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Priority Register B for Slave 4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Peripheral Select 1 Register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write
NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write
NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write
NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write
NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write
NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write
NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write
NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write
NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write
NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write
NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write
NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write
NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write
NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write
NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write
NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write
NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write
NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write
NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write
NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write
NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write
NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write
NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write
NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write
NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write
NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write
NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write
NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write
NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write
NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write
NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write
NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write
Master Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Priority Register B for Slave 6
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Areas Split Slave 0 Register
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Priority Register A for Slave 7
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 7
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Priority Register A for Slave 8
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Slave 0 Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register B for Slave 8
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 9
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Priority Register B for Slave 9
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Priority Register A for Slave 10
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 10
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 11
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Areas Split Slave 0 Register
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLIMITED
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE
Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4_BEAT
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.
0x3 : 8_BEAT
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.
0x4 : 16_BEAT
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.
0x5 : 32_BEAT
32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.
0x6 : 64_BEAT
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.
0x7 : 128_BEAT
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.
End of enumeration elements list.
Priority Register B for Slave 11
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 12
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Security Slave 0 Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write
LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write
LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write
LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write
LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write
LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write
LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write
LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write
RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write
RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write
RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write
RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write
RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write
RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write
RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write
RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write
WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write
WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write
WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write
WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write
WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write
WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write
WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write
WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write
Priority Register B for Slave 12
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0xE50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Priority Register A for Slave 13
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 13
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 14
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register B for Slave 14
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Security Region Top Slave 1 Register
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write
SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write
SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write
SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write
SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write
SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write
SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write
SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write
Master 0 Error Address Register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only
Security Areas Split Slave 0 Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write
SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write
SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write
SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write
SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write
SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write
SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write
SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write
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