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MATRIX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCFG[0]

MCFG0

MCFG4

SSR[6]

MCFG[11]

SCFG[2]

MEAR[10]

SRTSR[5]

SASSR[6]

SSR[7]

MEAR[11]

MCFG5

SRTSR[6]

SSR[8]

SASSR[7]

MEIER

MEIDR

SCFG[3]

MEIMR

MESR

MEAR0

MEAR1

MEAR2

SSR[9]

MEAR3

MEAR4

SASSR[8]

SRTSR[7]

MEAR5

MEAR6

MEAR7

MCFG[3]

MCFG6

MEAR8

MEAR9

MEAR10

MEAR11

SSR[10]

SASSR[9]

SRTSR[8]

SCFG[4]

SSR[11]

SASSR[10]

MCFG7

SRTSR[9]

SSR[12]

WPMR

SASSR[11]

WPSR

SRTSR[10]

SSR[13]

SCFG[5]

MCFG8

SSR0

SSR1

SSR2

SASSR[12]

SSR3

SSR4

SSR5

SSR6

SSR[14]

SRTSR[11]

SSR7

SSR8

SSR9

SSR10

SSR11

SSR12

SASSR[13]

SSR13

SSR14

MCFG9

SASSR0

SASSR1

SRTSR[12]

SASSR2

SASSR3

SASSR4

SCFG[6]

SASSR5

SASSR6

SASSR[14]

SASSR7

SASSR8

SASSR9

SASSR10

SASSR11

SASSR12

SRTSR[13]

SASSR13

SASSR14

MCFG[4]

MCFG10

SRTSR0

SRTSR1

SRTSR2

SRTSR3

SRTSR4

SRTSR5

SRTSR6

SRTSR7

SRTSR8

SRTSR9

SRTSR10

SCFG[7]

SRTSR11

SRTSR12

SRTSR13

MCFG11

MEAR[0]

SPSELR0

SPSELR1

SPSELR2

SCFG[8]

SCFG[9]

MCFG[5]

SCFG[10]

MCFG[1]

MCFG1

SCFG0

SSR[0]

MEAR[1]

SCFG1

SCFG[11]

SCFG2

SASSR[0]

SCFG[12]

SCFG3

SCFG4

SRTSR[0]

SCFG[13]

MCFG[6]

SCFG5

SCFG6

SPSELR[0]

MEAR[2]

SCFG[14]

SCFG7

SCFG8

SSR[1]

SCFG9

SCFG10

SCFG11

SASSR[1]

MEAR[3]

MCFG[7]

SCFG12

SCFG13

SCFG14

SRTSR[1]

MCFG2

SCFG[0]

PRAS0

SSR[2]

PRBS0

SPSELR[1]

MEAR[4]

PRAS1

PRBS1

MCFG[8]

PRAS2

SASSR[2]

PRBS2

PRAS3

PRBS3

MEAR[5]

PRAS4

SSR[3]

SRTSR[2]

PRBS4

PRAS5

PRBS5

PRAS6

SPSELR[2]

MCFG[9]

PRBS6

MEAR[6]

SASSR[3]

PRAS7

PRBS7

MCFG[2]

MCFG3

PRAS8

SSR[4]

SCFG[1]

PRBS8

PRAS9

SRTSR[3]

PRBS9

MEAR[7]

PRAS10

PRBS10

PRAS11

SASSR[4]

MCFG[10]

PRBS11

PRAS12

SSR[5]

PRBS12

MEAR[8]

PRAS13

PRBS13

PRAS14

PRBS14

SRTSR[4]

MEAR[9]

SASSR[5]


MCFG[0]

Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[0] MCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG0

Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG0 MCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG4

Master Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG4 MCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SSR[6]

Security Slave 0 Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[6] SSR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


MCFG[11]

Master Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[11] MCFG[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG[2]

Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[2] SCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MEAR[10]

Master 0 Error Address Register
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[10] MEAR[10] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SRTSR[5]

Security Region Top Slave 1 Register
address_offset : 0x11D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[5] SRTSR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SASSR[6]

Security Areas Split Slave 0 Register
address_offset : 0x1254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[6] SASSR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SSR[7]

Security Slave 0 Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[7] SSR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


MEAR[11]

Master 0 Error Address Register
address_offset : 0x12E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[11] MEAR[11] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MCFG5

Master Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG5 MCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SRTSR[6]

Security Region Top Slave 1 Register
address_offset : 0x1474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[6] SRTSR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SSR[8]

Security Slave 0 Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[8] SSR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SASSR[7]

Security Areas Split Slave 0 Register
address_offset : 0x14B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[7] SASSR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


MEIER

Master Error Interrupt Enable Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MEIER MEIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MERR0 MERR1 MERR2 MERR3 MERR4 MERR5 MERR6 MERR7 MERR8 MERR9 MERR10 MERR11

MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : write-only

MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : write-only

MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : write-only

MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : write-only

MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : write-only

MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : write-only

MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : write-only

MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : write-only

MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : write-only

MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : write-only

MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : write-only

MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : write-only


MEIDR

Master Error Interrupt Disable Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MEIDR MEIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MERR0 MERR1 MERR2 MERR3 MERR4 MERR5 MERR6 MERR7 MERR8 MERR9 MERR10 MERR11

MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : write-only

MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : write-only

MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : write-only

MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : write-only

MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : write-only

MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : write-only

MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : write-only

MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : write-only

MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : write-only

MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : write-only

MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : write-only

MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : write-only


SCFG[3]

Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[3] SCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MEIMR

Master Error Interrupt Mask Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEIMR MEIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MERR0 MERR1 MERR2 MERR3 MERR4 MERR5 MERR6 MERR7 MERR8 MERR9 MERR10 MERR11

MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : read-only

MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : read-only

MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : read-only

MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : read-only

MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : read-only

MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : read-only

MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : read-only

MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : read-only

MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : read-only

MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : read-only

MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : read-only

MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : read-only


MESR

Master Error Status Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MESR MESR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MERR0 MERR1 MERR2 MERR3 MERR4 MERR5 MERR6 MERR7 MERR8 MERR9 MERR10 MERR11

MERR0 : Master 0 Access Error
bits : 0 - 0 (1 bit)
access : read-only

MERR1 : Master 1 Access Error
bits : 1 - 1 (1 bit)
access : read-only

MERR2 : Master 2 Access Error
bits : 2 - 2 (1 bit)
access : read-only

MERR3 : Master 3 Access Error
bits : 3 - 3 (1 bit)
access : read-only

MERR4 : Master 4 Access Error
bits : 4 - 4 (1 bit)
access : read-only

MERR5 : Master 5 Access Error
bits : 5 - 5 (1 bit)
access : read-only

MERR6 : Master 6 Access Error
bits : 6 - 6 (1 bit)
access : read-only

MERR7 : Master 7 Access Error
bits : 7 - 7 (1 bit)
access : read-only

MERR8 : Master 8 Access Error
bits : 8 - 8 (1 bit)
access : read-only

MERR9 : Master 9 Access Error
bits : 9 - 9 (1 bit)
access : read-only

MERR10 : Master 10 Access Error
bits : 10 - 10 (1 bit)
access : read-only

MERR11 : Master 11 Access Error
bits : 11 - 11 (1 bit)
access : read-only


MEAR0

Master 0 Error Address Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR0 MEAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR1

Master 0 Error Address Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR1 MEAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR2

Master 0 Error Address Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR2 MEAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SSR[9]

Security Slave 0 Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[9] SSR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


MEAR3

Master 0 Error Address Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR3 MEAR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR4

Master 0 Error Address Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR4 MEAR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SASSR[8]

Security Areas Split Slave 0 Register
address_offset : 0x1710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[8] SASSR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SRTSR[7]

Security Region Top Slave 1 Register
address_offset : 0x1714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[7] SRTSR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


MEAR5

Master 0 Error Address Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR5 MEAR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR6

Master 0 Error Address Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR6 MEAR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR7

Master 0 Error Address Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR7 MEAR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MCFG[3]

Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[3] MCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG6

Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG6 MCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MEAR8

Master 0 Error Address Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR8 MEAR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR9

Master 0 Error Address Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR9 MEAR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR10

Master 0 Error Address Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR10 MEAR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MEAR11

Master 0 Error Address Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

MEAR11 MEAR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SSR[10]

Security Slave 0 Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[10] SSR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SASSR[9]

Security Areas Split Slave 0 Register
address_offset : 0x1974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[9] SASSR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SRTSR[8]

Security Region Top Slave 1 Register
address_offset : 0x19B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[8] SRTSR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SCFG[4]

Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[4] SCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SSR[11]

Security Slave 0 Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[11] SSR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SASSR[10]

Security Areas Split Slave 0 Register
address_offset : 0x1BDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[10] SASSR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


MCFG7

Master Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG7 MCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SRTSR[9]

Security Region Top Slave 1 Register
address_offset : 0x1C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[9] SRTSR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SSR[12]

Security Slave 0 Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[12] SSR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key (Write-only)
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x4D4154 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


SASSR[11]

Security Areas Split Slave 0 Register
address_offset : 0x1E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[11] SASSR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


WPSR

Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only


SRTSR[10]

Security Region Top Slave 1 Register
address_offset : 0x1F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[10] SRTSR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SSR[13]

Security Slave 0 Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[13] SSR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SCFG[5]

Slave Configuration Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[5] SCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG8

Master Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG8 MCFG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SSR0

Security Slave 0 Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR0 SSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR1

Security Slave 0 Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR1 SSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR2

Security Slave 0 Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR2 SSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SASSR[12]

Security Areas Split Slave 0 Register
address_offset : 0x20B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[12] SASSR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SSR3

Security Slave 0 Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR3 SSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR4

Security Slave 0 Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR4 SSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR5

Security Slave 0 Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR5 SSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR6

Security Slave 0 Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR6 SSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR[14]

Security Slave 0 Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[14] SSR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SRTSR[11]

Security Region Top Slave 1 Register
address_offset : 0x21BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[11] SRTSR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SSR7

Security Slave 0 Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR7 SSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR8

Security Slave 0 Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR8 SSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR9

Security Slave 0 Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR9 SSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR10

Security Slave 0 Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR10 SSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR11

Security Slave 0 Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR11 SSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR12

Security Slave 0 Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR12 SSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SASSR[13]

Security Areas Split Slave 0 Register
address_offset : 0x232C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[13] SASSR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SSR13

Security Slave 0 Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR13 SSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SSR14

Security Slave 0 Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SSR14 SSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


MCFG9

Master Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG9 MCFG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SASSR0

Security Areas Split Slave 0 Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR0 SASSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR1

Security Areas Split Slave 0 Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR1 SASSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SRTSR[12]

Security Region Top Slave 1 Register
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[12] SRTSR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SASSR2

Security Areas Split Slave 0 Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR2 SASSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR3

Security Areas Split Slave 0 Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR3 SASSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR4

Security Areas Split Slave 0 Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR4 SASSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SCFG[6]

Slave Configuration Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[6] SCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SASSR5

Security Areas Split Slave 0 Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR5 SASSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR6

Security Areas Split Slave 0 Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR6 SASSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR[14]

Security Areas Split Slave 0 Register
address_offset : 0x25A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[14] SASSR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR7

Security Areas Split Slave 0 Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR7 SASSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR8

Security Areas Split Slave 0 Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR8 SASSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR9

Security Areas Split Slave 0 Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR9 SASSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR10

Security Areas Split Slave 0 Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR10 SASSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR11

Security Areas Split Slave 0 Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR11 SASSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR12

Security Areas Split Slave 0 Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR12 SASSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SRTSR[13]

Security Region Top Slave 1 Register
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[13] SRTSR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SASSR13

Security Areas Split Slave 0 Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR13 SASSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SASSR14

Security Areas Split Slave 0 Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SASSR14 SASSR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


MCFG[4]

Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[4] MCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG10

Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG10 MCFG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SRTSR0

Security Region Top Slave 1 Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR0 SRTSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR1

Security Region Top Slave 1 Register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR1 SRTSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR2

Security Region Top Slave 1 Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR2 SRTSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR3

Security Region Top Slave 1 Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR3 SRTSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR4

Security Region Top Slave 1 Register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR4 SRTSR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR5

Security Region Top Slave 1 Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR5 SRTSR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR6

Security Region Top Slave 1 Register
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR6 SRTSR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR7

Security Region Top Slave 1 Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR7 SRTSR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR8

Security Region Top Slave 1 Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR8 SRTSR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR9

Security Region Top Slave 1 Register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR9 SRTSR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR10

Security Region Top Slave 1 Register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR10 SRTSR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SCFG[7]

Slave Configuration Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[7] SCFG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SRTSR11

Security Region Top Slave 1 Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR11 SRTSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR12

Security Region Top Slave 1 Register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR12 SRTSR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SRTSR13

Security Region Top Slave 1 Register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SRTSR13 SRTSR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


MCFG11

Master Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG11 MCFG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MEAR[0]

Master 0 Error Address Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[0] MEAR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SPSELR0

Security Peripheral Select 1 Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SPSELR0 SPSELR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


SPSELR1

Security Peripheral Select 1 Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SPSELR1 SPSELR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


SPSELR2

Security Peripheral Select 1 Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SPSELR2 SPSELR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


SCFG[8]

Slave Configuration Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[8] SCFG[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG[9]

Slave Configuration Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[9] SCFG[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[5]

Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[5] MCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG[10]

Slave Configuration Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[10] SCFG[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[1]

Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[1] MCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG1

Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG1 MCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG0

Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG0 SCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SSR[0]

Security Slave 0 Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[0] SSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


MEAR[1]

Master 0 Error Address Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[1] MEAR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SCFG1

Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG1 SCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG[11]

Slave Configuration Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[11] SCFG[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG2

Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG2 SCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SASSR[0]

Security Areas Split Slave 0 Register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[0] SASSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


SCFG[12]

Slave Configuration Register
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[12] SCFG[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG3

Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG3 SCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG4

Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG4 SCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SRTSR[0]

Security Region Top Slave 1 Register
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[0] SRTSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


SCFG[13]

Slave Configuration Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[13] SCFG[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[6]

Master Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[6] MCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG5

Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG5 SCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG6

Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG6 SCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SPSELR[0]

Security Peripheral Select 1 Register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSELR[0] SPSELR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


MEAR[2]

Master 0 Error Address Register
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[2] MEAR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SCFG[14]

Slave Configuration Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[14] SCFG[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG7

Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG7 SCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG8

Slave Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG8 SCFG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SSR[1]

Security Slave 0 Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[1] SSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SCFG9

Slave Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG9 SCFG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG10

Slave Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG10 SCFG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG11

Slave Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG11 SCFG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SASSR[1]

Security Areas Split Slave 0 Register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[1] SASSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


MEAR[3]

Master 0 Error Address Register
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[3] MEAR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


MCFG[7]

Master Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[7] MCFG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG12

Slave Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG12 SCFG12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG13

Slave Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG13 SCFG13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG14

Slave Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG14 SCFG14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SRTSR[1]

Security Region Top Slave 1 Register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[1] SRTSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


MCFG2

Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG2 MCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


SCFG[0]

Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[0] SCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


PRAS0

Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS0 PRAS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SSR[2]

Security Slave 0 Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[2] SSR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


PRBS0

Priority Register B for Slave 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS0 PRBS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


SPSELR[1]

Security Peripheral Select 1 Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSELR[1] SPSELR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


MEAR[4]

Master 0 Error Address Register
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[4] MEAR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


PRAS1

Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS1 PRAS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS1

Priority Register B for Slave 1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS1 PRBS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MCFG[8]

Master Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[8] MCFG[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


PRAS2

Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS2 PRAS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SASSR[2]

Security Areas Split Slave 0 Register
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[2] SASSR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


PRBS2

Priority Register B for Slave 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS2 PRBS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS3

Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS3 PRAS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS3

Priority Register B for Slave 3
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS3 PRBS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MEAR[5]

Master 0 Error Address Register
address_offset : 0x9DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[5] MEAR[5] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


PRAS4

Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS4 PRAS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SSR[3]

Security Slave 0 Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[3] SSR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SRTSR[2]

Security Region Top Slave 1 Register
address_offset : 0xA1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[2] SRTSR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


PRBS4

Priority Register B for Slave 4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS4 PRBS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS5

Priority Register A for Slave 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS5 PRAS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS5

Priority Register B for Slave 5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS5 PRBS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS6

Priority Register A for Slave 6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS6 PRAS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SPSELR[2]

Security Peripheral Select 1 Register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSELR[2] SPSELR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NSECP0 NSECP1 NSECP2 NSECP3 NSECP4 NSECP5 NSECP6 NSECP7 NSECP8 NSECP9 NSECP10 NSECP11 NSECP12 NSECP13 NSECP14 NSECP15 NSECP16 NSECP17 NSECP18 NSECP19 NSECP20 NSECP21 NSECP22 NSECP23 NSECP24 NSECP25 NSECP26 NSECP27 NSECP28 NSECP29 NSECP30 NSECP31

NSECP0 : Non-secured Peripheral
bits : 0 - 0 (1 bit)
access : read-write

NSECP1 : Non-secured Peripheral
bits : 1 - 1 (1 bit)
access : read-write

NSECP2 : Non-secured Peripheral
bits : 2 - 2 (1 bit)
access : read-write

NSECP3 : Non-secured Peripheral
bits : 3 - 3 (1 bit)
access : read-write

NSECP4 : Non-secured Peripheral
bits : 4 - 4 (1 bit)
access : read-write

NSECP5 : Non-secured Peripheral
bits : 5 - 5 (1 bit)
access : read-write

NSECP6 : Non-secured Peripheral
bits : 6 - 6 (1 bit)
access : read-write

NSECP7 : Non-secured Peripheral
bits : 7 - 7 (1 bit)
access : read-write

NSECP8 : Non-secured Peripheral
bits : 8 - 8 (1 bit)
access : read-write

NSECP9 : Non-secured Peripheral
bits : 9 - 9 (1 bit)
access : read-write

NSECP10 : Non-secured Peripheral
bits : 10 - 10 (1 bit)
access : read-write

NSECP11 : Non-secured Peripheral
bits : 11 - 11 (1 bit)
access : read-write

NSECP12 : Non-secured Peripheral
bits : 12 - 12 (1 bit)
access : read-write

NSECP13 : Non-secured Peripheral
bits : 13 - 13 (1 bit)
access : read-write

NSECP14 : Non-secured Peripheral
bits : 14 - 14 (1 bit)
access : read-write

NSECP15 : Non-secured Peripheral
bits : 15 - 15 (1 bit)
access : read-write

NSECP16 : Non-secured Peripheral
bits : 16 - 16 (1 bit)
access : read-write

NSECP17 : Non-secured Peripheral
bits : 17 - 17 (1 bit)
access : read-write

NSECP18 : Non-secured Peripheral
bits : 18 - 18 (1 bit)
access : read-write

NSECP19 : Non-secured Peripheral
bits : 19 - 19 (1 bit)
access : read-write

NSECP20 : Non-secured Peripheral
bits : 20 - 20 (1 bit)
access : read-write

NSECP21 : Non-secured Peripheral
bits : 21 - 21 (1 bit)
access : read-write

NSECP22 : Non-secured Peripheral
bits : 22 - 22 (1 bit)
access : read-write

NSECP23 : Non-secured Peripheral
bits : 23 - 23 (1 bit)
access : read-write

NSECP24 : Non-secured Peripheral
bits : 24 - 24 (1 bit)
access : read-write

NSECP25 : Non-secured Peripheral
bits : 25 - 25 (1 bit)
access : read-write

NSECP26 : Non-secured Peripheral
bits : 26 - 26 (1 bit)
access : read-write

NSECP27 : Non-secured Peripheral
bits : 27 - 27 (1 bit)
access : read-write

NSECP28 : Non-secured Peripheral
bits : 28 - 28 (1 bit)
access : read-write

NSECP29 : Non-secured Peripheral
bits : 29 - 29 (1 bit)
access : read-write

NSECP30 : Non-secured Peripheral
bits : 30 - 30 (1 bit)
access : read-write

NSECP31 : Non-secured Peripheral
bits : 31 - 31 (1 bit)
access : read-write


MCFG[9]

Master Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[9] MCFG[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


PRBS6

Priority Register B for Slave 6
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS6 PRBS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MEAR[6]

Master 0 Error Address Register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[6] MEAR[6] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SASSR[3]

Security Areas Split Slave 0 Register
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[3] SASSR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


PRAS7

Priority Register A for Slave 7
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS7 PRAS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS7

Priority Register B for Slave 7
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS7 PRBS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MCFG[2]

Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[2] MCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


MCFG3

Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG3 MCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


PRAS8

Priority Register A for Slave 8
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS8 PRAS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SSR[4]

Security Slave 0 Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[4] SSR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


SCFG[1]

Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[1] SCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.

0x1 : LAST

Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.

0x2 : FIXED

Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.

End of enumeration elements list.

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


PRBS8

Priority Register B for Slave 8
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS8 PRBS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS9

Priority Register A for Slave 9
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS9 PRAS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SRTSR[3]

Security Region Top Slave 1 Register
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[3] SRTSR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


PRBS9

Priority Register B for Slave 9
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS9 PRBS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MEAR[7]

Master 0 Error Address Register
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[7] MEAR[7] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


PRAS10

Priority Register A for Slave 10
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS10 PRAS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS10

Priority Register B for Slave 10
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS10 PRBS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS11

Priority Register A for Slave 11
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS11 PRAS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SASSR[4]

Security Areas Split Slave 0 Register
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[4] SASSR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write


MCFG[10]

Master Configuration Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[10] MCFG[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : UNLIMITED

Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.

0x1 : SINGLE

Single Access-The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst or bursts sequence.

0x2 : 4_BEAT

4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing rearbitration every 4 beats.

0x3 : 8_BEAT

8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing rearbitration every 8 beats.

0x4 : 16_BEAT

16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing rearbitration every 16 beats.

0x5 : 32_BEAT

32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing rearbitration every 32 beats.

0x6 : 64_BEAT

64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing rearbitration every 64 beats.

0x7 : 128_BEAT

128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing rearbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving.

End of enumeration elements list.


PRBS11

Priority Register B for Slave 11
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS11 PRBS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS12

Priority Register A for Slave 12
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS12 PRAS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


SSR[5]

Security Slave 0 Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR[5] SSR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LANSECH0 LANSECH1 LANSECH2 LANSECH3 LANSECH4 LANSECH5 LANSECH6 LANSECH7 RDNSECH0 RDNSECH1 RDNSECH2 RDNSECH3 RDNSECH4 RDNSECH5 RDNSECH6 RDNSECH7 WRNSECH0 WRNSECH1 WRNSECH2 WRNSECH3 WRNSECH4 WRNSECH5 WRNSECH6 WRNSECH7

LANSECH0 : Low Area Non-secured in HSELx Security Region
bits : 0 - 0 (1 bit)
access : read-write

LANSECH1 : Low Area Non-secured in HSELx Security Region
bits : 1 - 1 (1 bit)
access : read-write

LANSECH2 : Low Area Non-secured in HSELx Security Region
bits : 2 - 2 (1 bit)
access : read-write

LANSECH3 : Low Area Non-secured in HSELx Security Region
bits : 3 - 3 (1 bit)
access : read-write

LANSECH4 : Low Area Non-secured in HSELx Security Region
bits : 4 - 4 (1 bit)
access : read-write

LANSECH5 : Low Area Non-secured in HSELx Security Region
bits : 5 - 5 (1 bit)
access : read-write

LANSECH6 : Low Area Non-secured in HSELx Security Region
bits : 6 - 6 (1 bit)
access : read-write

LANSECH7 : Low Area Non-secured in HSELx Security Region
bits : 7 - 7 (1 bit)
access : read-write

RDNSECH0 : Read Non-secured for HSELx Security Region
bits : 8 - 8 (1 bit)
access : read-write

RDNSECH1 : Read Non-secured for HSELx Security Region
bits : 9 - 9 (1 bit)
access : read-write

RDNSECH2 : Read Non-secured for HSELx Security Region
bits : 10 - 10 (1 bit)
access : read-write

RDNSECH3 : Read Non-secured for HSELx Security Region
bits : 11 - 11 (1 bit)
access : read-write

RDNSECH4 : Read Non-secured for HSELx Security Region
bits : 12 - 12 (1 bit)
access : read-write

RDNSECH5 : Read Non-secured for HSELx Security Region
bits : 13 - 13 (1 bit)
access : read-write

RDNSECH6 : Read Non-secured for HSELx Security Region
bits : 14 - 14 (1 bit)
access : read-write

RDNSECH7 : Read Non-secured for HSELx Security Region
bits : 15 - 15 (1 bit)
access : read-write

WRNSECH0 : Write Non-secured for HSELx Security Region
bits : 16 - 16 (1 bit)
access : read-write

WRNSECH1 : Write Non-secured for HSELx Security Region
bits : 17 - 17 (1 bit)
access : read-write

WRNSECH2 : Write Non-secured for HSELx Security Region
bits : 18 - 18 (1 bit)
access : read-write

WRNSECH3 : Write Non-secured for HSELx Security Region
bits : 19 - 19 (1 bit)
access : read-write

WRNSECH4 : Write Non-secured for HSELx Security Region
bits : 20 - 20 (1 bit)
access : read-write

WRNSECH5 : Write Non-secured for HSELx Security Region
bits : 21 - 21 (1 bit)
access : read-write

WRNSECH6 : Write Non-secured for HSELx Security Region
bits : 22 - 22 (1 bit)
access : read-write

WRNSECH7 : Write Non-secured for HSELx Security Region
bits : 23 - 23 (1 bit)
access : read-write


PRBS12

Priority Register B for Slave 12
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS12 PRBS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


MEAR[8]

Master 0 Error Address Register
address_offset : 0xE50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[8] MEAR[8] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


PRAS13

Priority Register A for Slave 13
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS13 PRAS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS13

Priority Register B for Slave 13
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS13 PRBS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


PRAS14

Priority Register A for Slave 14
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS14 PRAS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRBS14

Priority Register B for Slave 14
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRBS14 PRBS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M8PR M9PR M10PR M11PR

M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write

M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write

M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write

M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write


SRTSR[4]

Security Region Top Slave 1 Register
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRTSR[4] SRTSR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRTOP0 SRTOP1 SRTOP2 SRTOP3 SRTOP4 SRTOP5 SRTOP6 SRTOP7

SRTOP0 : HSELx Security Region Top
bits : 0 - 3 (4 bit)
access : read-write

SRTOP1 : HSELx Security Region Top
bits : 4 - 7 (4 bit)
access : read-write

SRTOP2 : HSELx Security Region Top
bits : 8 - 11 (4 bit)
access : read-write

SRTOP3 : HSELx Security Region Top
bits : 12 - 15 (4 bit)
access : read-write

SRTOP4 : HSELx Security Region Top
bits : 16 - 19 (4 bit)
access : read-write

SRTOP5 : HSELx Security Region Top
bits : 20 - 23 (4 bit)
access : read-write

SRTOP6 : HSELx Security Region Top
bits : 24 - 27 (4 bit)
access : read-write

SRTOP7 : HSELx Security Region Top
bits : 28 - 31 (4 bit)
access : read-write


MEAR[9]

Master 0 Error Address Register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MEAR[9] MEAR[9] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADD

ERRADD : Master Error Address
bits : 0 - 31 (32 bit)
access : read-only


SASSR[5]

Security Areas Split Slave 0 Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SASSR[5] SASSR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SASPLIT0 SASPLIT1 SASPLIT2 SASPLIT3 SASPLIT4 SASPLIT5 SASPLIT6 SASPLIT7

SASPLIT0 : Security Areas Split for HSELx Security Region
bits : 0 - 3 (4 bit)
access : read-write

SASPLIT1 : Security Areas Split for HSELx Security Region
bits : 4 - 7 (4 bit)
access : read-write

SASPLIT2 : Security Areas Split for HSELx Security Region
bits : 8 - 11 (4 bit)
access : read-write

SASPLIT3 : Security Areas Split for HSELx Security Region
bits : 12 - 15 (4 bit)
access : read-write

SASPLIT4 : Security Areas Split for HSELx Security Region
bits : 16 - 19 (4 bit)
access : read-write

SASPLIT5 : Security Areas Split for HSELx Security Region
bits : 20 - 23 (4 bit)
access : read-write

SASPLIT6 : Security Areas Split for HSELx Security Region
bits : 24 - 27 (4 bit)
access : read-write

SASPLIT7 : Security Areas Split for HSELx Security Region
bits : 28 - 31 (4 bit)
access : read-write



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