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SECUMOD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

SCR

PIOBU[6]

RAMRDY

PIOBU[7]

PIOBU0

PIOBU1

PIOBU2

PIOBU3

PIOBU4

PIOBU5

PIOBU[0]

PIOBU6

PIOBU7

SYSR

PIOBU[1]

JTAGCR

PIOBU[2]

SCRKEY

RAMACC

RAMACCSR

BMPR

SR

NMPR

NIEPR

NIDPR

NIMPR

PIOBU[3]

WKPR

PIOBU[4]

PIOBU[5]


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BACKUP NORMAL SWPROT SCRAMB KEY

BACKUP : Backup Mode
bits : 0 - 0 (1 bit)
access : write-only

NORMAL : Normal Mode
bits : 1 - 1 (1 bit)
access : write-only

SWPROT : Software Protection
bits : 2 - 2 (1 bit)
access : write-only

SCRAMB : Memory Scrambling Enable
bits : 9 - 10 (2 bit)
access : write-only

KEY : Password
bits : 16 - 31 (16 bit)
access : write-only


SCR

Status Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector
bits : 16 - 16 (1 bit)
access : write-only

DET1 : PIOBU Intrusion Detector
bits : 17 - 17 (1 bit)
access : write-only

DET2 : PIOBU Intrusion Detector
bits : 18 - 18 (1 bit)
access : write-only

DET3 : PIOBU Intrusion Detector
bits : 19 - 19 (1 bit)
access : write-only

DET4 : PIOBU Intrusion Detector
bits : 20 - 20 (1 bit)
access : write-only

DET5 : PIOBU Intrusion Detector
bits : 21 - 21 (1 bit)
access : write-only

DET6 : PIOBU Intrusion Detector
bits : 22 - 22 (1 bit)
access : write-only

DET7 : PIOBU Intrusion Detector
bits : 23 - 23 (1 bit)
access : write-only


PIOBU[6]

PIO Backup Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[6] PIOBU[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


RAMRDY

RAM Access Ready Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMRDY RAMRDY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY

READY : Ready for system access flag
bits : 0 - 0 (1 bit)
access : read-only


PIOBU[7]

PIO Backup Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[7] PIOBU[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU0

PIO Backup Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU0 PIOBU0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU1

PIO Backup Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU1 PIOBU1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU2

PIO Backup Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU2 PIOBU2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU3

PIO Backup Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU3 PIOBU3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU4

PIO Backup Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU4 PIOBU4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU5

PIO Backup Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU5 PIOBU5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU[0]

PIO Backup Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[0] PIOBU[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU6

PIO Backup Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU6 PIOBU6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU7

PIO Backup Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PIOBU7 PIOBU7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


SYSR

System Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSR SYSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE_DONE ERASE_ON BACKUP SWKUP AUTOBKP SCRAMB

ERASE_DONE : Erasable Memories State (RW)
bits : 0 - 0 (1 bit)
access : read-write

ERASE_ON : Erase Process Ongoing (RO)
bits : 1 - 1 (1 bit)
access : read-write

BACKUP : Backup Mode (RO)
bits : 2 - 2 (1 bit)
access : read-write

SWKUP : SWKUP State (RO)
bits : 3 - 3 (1 bit)
access : read-write

AUTOBKP : Automatic Backup Mode Enabled (RO)
bits : 6 - 6 (1 bit)
access : read-write

SCRAMB : Scrambling Enabled (RO)
bits : 7 - 7 (1 bit)
access : read-write


PIOBU[1]

PIO Backup Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[1] PIOBU[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


JTAGCR

JTAG Protection Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JTAGCR JTAGCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNTRST CA5_DEBUG_MODE WZO

FNTRST : Force NTRST
bits : 0 - 0 (1 bit)
access : read-write

CA5_DEBUG_MODE : Cortex-A5 Invasive/Non-Invasive Secure/Non-Secure Debug Permissions
bits : 1 - 3 (3 bit)
access : read-write

WZO : Write ZERO
bits : 4 - 4 (1 bit)
access : read-write


PIOBU[2]

PIO Backup Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[2] PIOBU[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


SCRKEY

Scrambling Key Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRKEY SCRKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRKEY

SCRKEY : Scrambling Key Value
bits : 0 - 31 (32 bit)
access : read-write


RAMACC

RAM Access Rights Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMACC RAMACC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW0 RW1 RW2 RW3 RW4 RW5

RW0 : Access right for RAM region [0; 1 Kbyte]
bits : 0 - 1 (2 bit)
access : read-write

RW1 : Access right for RAM region [1 Kbyte; 2 Kbytes]
bits : 2 - 3 (2 bit)
access : read-write

RW2 : Access right for RAM region [2 Kbytes; 3 Kbytes]
bits : 4 - 5 (2 bit)
access : read-write

RW3 : Access right for RAM region [3 Kbytes; 4 Kbytes]
bits : 6 - 7 (2 bit)
access : read-write

RW4 : Access right for RAM region [4 Kbytes; 5 Kbytes]
bits : 8 - 9 (2 bit)
access : read-write

RW5 : Access right for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)
bits : 10 - 11 (2 bit)
access : read-write


RAMACCSR

RAM Access Rights Status Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAMACCSR RAMACCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW0 RW1 RW2 RW3 RW4 RW5

RW0 : Access right status for RAM region [0; 1 Kbyte]
bits : 0 - 1 (2 bit)
access : read-write

RW1 : Access right status for RAM region [1 Kbytes; 2 Kbytes]
bits : 2 - 3 (2 bit)
access : read-write

RW2 : Access right status for RAM region [2 Kbytes; 3 Kbytes]
bits : 4 - 5 (2 bit)
access : read-write

RW3 : Access right status for RAM region [3 Kbytes; 4 Kbytes]
bits : 6 - 7 (2 bit)
access : read-write

RW4 : Access right status for RAM region [4 Kbytes; 5 Kbytes]
bits : 8 - 9 (2 bit)
access : read-write

RW5 : Access right status for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)
bits : 10 - 11 (2 bit)
access : read-write


BMPR

Backup Mode Protection Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMPR BMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection
bits : 16 - 16 (1 bit)
access : read-write

DET1 : PIOBU Intrusion Detector Protection
bits : 17 - 17 (1 bit)
access : read-write

DET2 : PIOBU Intrusion Detector Protection
bits : 18 - 18 (1 bit)
access : read-write

DET3 : PIOBU Intrusion Detector Protection
bits : 19 - 19 (1 bit)
access : read-write

DET4 : PIOBU Intrusion Detector Protection
bits : 20 - 20 (1 bit)
access : read-write

DET5 : PIOBU Intrusion Detector Protection
bits : 21 - 21 (1 bit)
access : read-write

DET6 : PIOBU Intrusion Detector Protection
bits : 22 - 22 (1 bit)
access : read-write

DET7 : PIOBU Intrusion Detector Protection
bits : 23 - 23 (1 bit)
access : read-write


SR

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector
bits : 16 - 16 (1 bit)
access : read-only

DET1 : PIOBU Intrusion Detector
bits : 17 - 17 (1 bit)
access : read-only

DET2 : PIOBU Intrusion Detector
bits : 18 - 18 (1 bit)
access : read-only

DET3 : PIOBU Intrusion Detector
bits : 19 - 19 (1 bit)
access : read-only

DET4 : PIOBU Intrusion Detector
bits : 20 - 20 (1 bit)
access : read-only

DET5 : PIOBU Intrusion Detector
bits : 21 - 21 (1 bit)
access : read-only

DET6 : PIOBU Intrusion Detector
bits : 22 - 22 (1 bit)
access : read-only

DET7 : PIOBU Intrusion Detector
bits : 23 - 23 (1 bit)
access : read-only


NMPR

Normal Mode Protection Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMPR NMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection
bits : 16 - 16 (1 bit)
access : read-write

DET1 : PIOBU Intrusion Detector Protection
bits : 17 - 17 (1 bit)
access : read-write

DET2 : PIOBU Intrusion Detector Protection
bits : 18 - 18 (1 bit)
access : read-write

DET3 : PIOBU Intrusion Detector Protection
bits : 19 - 19 (1 bit)
access : read-write

DET4 : PIOBU Intrusion Detector Protection
bits : 20 - 20 (1 bit)
access : read-write

DET5 : PIOBU Intrusion Detector Protection
bits : 21 - 21 (1 bit)
access : read-write

DET6 : PIOBU Intrusion Detector Protection
bits : 22 - 22 (1 bit)
access : read-write

DET7 : PIOBU Intrusion Detector Protection
bits : 23 - 23 (1 bit)
access : read-write


NIEPR

Normal Interrupt Enable Protection Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

NIEPR NIEPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

DET1 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

DET2 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

DET3 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

DET4 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

DET5 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

DET6 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

DET7 : PIOBU Intrusion Detector Protection Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only


NIDPR

Normal Interrupt Disable Protection Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

NIDPR NIDPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

DET1 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

DET2 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

DET3 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

DET4 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

DET5 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

DET6 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

DET7 : PIOBU Intrusion Detector Protection Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only


NIMPR

Normal Interrupt Mask Protection Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NIMPR NIMPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

DET1 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

DET2 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

DET3 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

DET4 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

DET5 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

DET6 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

DET7 : PIOBU Intrusion Detector Protection Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only


PIOBU[3]

PIO Backup Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[3] PIOBU[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


WKPR

Wakeup Protection Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKPR WKPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET4 DET5 DET6 DET7

DET0 : PIOBU Intrusion Detector Protection
bits : 16 - 16 (1 bit)
access : read-write

DET1 : PIOBU Intrusion Detector Protection
bits : 17 - 17 (1 bit)
access : read-write

DET2 : PIOBU Intrusion Detector Protection
bits : 18 - 18 (1 bit)
access : read-write

DET3 : PIOBU Intrusion Detector Protection
bits : 19 - 19 (1 bit)
access : read-write

DET4 : PIOBU Intrusion Detector Protection
bits : 20 - 20 (1 bit)
access : read-write

DET5 : PIOBU Intrusion Detector Protection
bits : 21 - 21 (1 bit)
access : read-write

DET6 : PIOBU Intrusion Detector Protection
bits : 22 - 22 (1 bit)
access : read-write

DET7 : PIOBU Intrusion Detector Protection
bits : 23 - 23 (1 bit)
access : read-write


PIOBU[4]

PIO Backup Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[4] PIOBU[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write


PIOBU[5]

PIO Backup Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOBU[5] PIOBU[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOBU_AFV PIOBU_RFV OUTPUT PIO_SOD PIO_PDS PULLUP SCHEDULE SWITCH

PIOBU_AFV : PIOBU Alarm Filter Value
bits : 0 - 3 (4 bit)
access : read-write

PIOBU_RFV : PIOBUx Reset Filter Value
bits : 4 - 7 (4 bit)
access : read-write

OUTPUT : Configure I/O Line in Input/Output
bits : 8 - 8 (1 bit)
access : read-write

PIO_SOD : Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)
bits : 9 - 9 (1 bit)
access : read-write

PIO_PDS : Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)
bits : 10 - 10 (1 bit)
access : read-write

PULLUP : Programmable Pull-up State
bits : 12 - 13 (2 bit)
access : read-write

SCHEDULE : Pull-up/Down Scheduled
bits : 14 - 14 (1 bit)
access : read-write

SWITCH : Switch State for Intrusion Detection
bits : 15 - 15 (1 bit)
access : read-write



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