\n

SYSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR


CR

Slow Clock Controller Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSCSEL

OSCSEL : Slow Clock Selector
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : RC

Slow clock is the embedded 64 kHz (typical) RC oscillator.

1 : XTAL

Slow clock is the 32.768 kHz crystal oscillator.

End of enumeration elements list.



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