\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only
CKEN : Clocks Enable
bits : 2 - 2 (1 bit)
access : write-only
CKDIS : Clocks Disable
bits : 3 - 3 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 4 - 4 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 5 - 5 (1 bit)
access : write-only
SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only
Status Set Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXOR : Receive Overrun Status Set
bits : 2 - 2 (1 bit)
access : write-only
TXUR : Transmit Underrun Status Set
bits : 6 - 6 (1 bit)
access : write-only
RXORCH : Receive Overrun Per Channel Status Set
bits : 8 - 9 (2 bit)
access : write-only
TXURCH : Transmit Underrun Per Channel Status Set
bits : 20 - 21 (2 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXOR : Receiver Overrun Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
TXRDY : Transmit Ready Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
TXUR : Transmit Underflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
RXOR : Receiver Overrun Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
TXRDY : Transmit Ready Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
TXUR : Transmit Underflow Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : read-only
RXOR : Receiver Overrun Interrupt Disable
bits : 2 - 2 (1 bit)
access : read-only
TXRDY : Transmit Ready Interrupt Disable
bits : 5 - 5 (1 bit)
access : read-only
TXUR : Transmit Underflow Interrupt Disable
bits : 6 - 6 (1 bit)
access : read-only
Receiver Holding Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RHR : Receiver Holding Register
bits : 0 - 31 (32 bit)
access : read-only
Transmitter Holding Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
THR : Transmitter Holding Register
bits : 0 - 31 (32 bit)
access : write-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Inter-IC Sound Controller Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SLAVE
I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization.
1 : MASTER
Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set.
End of enumeration elements list.
DATALENGTH : Data Word Length
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0x0 : 32_BITS
Data length is set to 32 bits
0x1 : 24_BITS
Data length is set to 24 bits
0x2 : 20_BITS
Data length is set to 20 bits
0x3 : 18_BITS
Data length is set to 18 bits
0x4 : 16_BITS
Data length is set to 16 bits
0x5 : 16_BITS_COMPACT
Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word.
0x6 : 8_BITS
Data length is set to 8 bits
0x7 : 8_BITS_COMPACT
Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word.
End of enumeration elements list.
FORMAT : Data Format
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : I2S
I2S format, stereo with I2SC_WS low for left channel, and MSB of sample starting one I2SC_CK period after I2SC_WS edge
1 : LJ
Left-justified format, stereo with I2SC_WS high for left channel, and MSB of sample starting on I2SC_WS edge
End of enumeration elements list.
RXMONO : Receive Mono
bits : 8 - 8 (1 bit)
access : read-write
RXLOOP : Loopback Test Mode
bits : 10 - 10 (1 bit)
access : read-write
TXMONO : Transmit Mono
bits : 12 - 12 (1 bit)
access : read-write
TXSAME : Transmit Data when Underrun
bits : 14 - 14 (1 bit)
access : read-write
IMCKDIV : Selected Clock to I2SC Master Clock Ratio
bits : 16 - 21 (6 bit)
access : read-write
IMCKFS : Master Clock to fs Ratio
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0x0 : M2SF32
Sample frequency ratio set to 32
0x1 : M2SF64
Sample frequency ratio set to 64
0x2 : M2SF96
Sample frequency ratio set to 96
0x3 : M2SF128
Sample frequency ratio set to 128
0x5 : M2SF192
Sample frequency ratio set to 192
0x7 : M2SF256
Sample frequency ratio set to 256
0xB : M2SF384
Sample frequency ratio set to 384
0xF : M2SF512
Sample frequency ratio set to 512
0x17 : M2SF768
Sample frequency ratio set to 768
0x1F : M2SF1024
Sample frequency ratio set to 1024
0x2F : M2SF1536
Sample frequency ratio set to 1536
0x3F : M2SF2048
Sample frequency ratio set to 2048
End of enumeration elements list.
IMCKMODE : Master Clock Mode
bits : 30 - 30 (1 bit)
access : read-write
IWS : I2SC_WS Slot Width
bits : 31 - 31 (1 bit)
access : read-write
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receiver Enabled
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Ready
bits : 1 - 1 (1 bit)
access : read-only
RXOR : Receive Overrun
bits : 2 - 2 (1 bit)
access : read-only
TXEN : Transmitter Enabled
bits : 4 - 4 (1 bit)
access : read-only
TXRDY : Transmit Ready
bits : 5 - 5 (1 bit)
access : read-only
TXUR : Transmit Underrun
bits : 6 - 6 (1 bit)
access : read-only
RXORCH : Receive Overrun Channel
bits : 8 - 9 (2 bit)
access : read-only
TXURCH : Transmit Underrun Channel
bits : 20 - 21 (2 bit)
access : read-only
Status Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXOR : Receive Overrun Status Clear
bits : 2 - 2 (1 bit)
access : write-only
TXUR : Transmit Underrun Status Clear
bits : 6 - 6 (1 bit)
access : write-only
RXORCH : Receive Overrun Per Channel Status Clear
bits : 8 - 9 (2 bit)
access : write-only
TXURCH : Transmit Underrun Per Channel Status Clear
bits : 20 - 21 (2 bit)
access : write-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.