\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Global Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NB_CH : Number of Channels Minus One
bits : 0 - 4 (5 bit)
access : read-only
FIFO_SZ : Number of Bytes
bits : 5 - 15 (11 bit)
access : read-only
NB_REQ : Number of Peripheral Requests Minus One
bits : 16 - 22 (7 bit)
access : read-only
Global Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ID0 : XDMAC Channel 0 Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
ID1 : XDMAC Channel 1 Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
ID2 : XDMAC Channel 2 Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
ID3 : XDMAC Channel 3 Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
ID4 : XDMAC Channel 4 Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
ID5 : XDMAC Channel 5 Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ID6 : XDMAC Channel 6 Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
ID7 : XDMAC Channel 7 Interrupt Disable Bit
bits : 7 - 7 (1 bit)
access : write-only
ID8 : XDMAC Channel 8 Interrupt Disable Bit
bits : 8 - 8 (1 bit)
access : write-only
ID9 : XDMAC Channel 9 Interrupt Disable Bit
bits : 9 - 9 (1 bit)
access : write-only
ID10 : XDMAC Channel 10 Interrupt Disable Bit
bits : 10 - 10 (1 bit)
access : write-only
ID11 : XDMAC Channel 11 Interrupt Disable Bit
bits : 11 - 11 (1 bit)
access : write-only
ID12 : XDMAC Channel 12 Interrupt Disable Bit
bits : 12 - 12 (1 bit)
access : write-only
ID13 : XDMAC Channel 13 Interrupt Disable Bit
bits : 13 - 13 (1 bit)
access : write-only
ID14 : XDMAC Channel 14 Interrupt Disable Bit
bits : 14 - 14 (1 bit)
access : write-only
ID15 : XDMAC Channel 15 Interrupt Disable Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 2)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 2)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 3)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 3)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 3)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 3)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 3)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 3)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 3)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 3)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 3)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 3)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 3)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 3)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IM0 : XDMAC Channel 0 Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
IM1 : XDMAC Channel 1 Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
IM2 : XDMAC Channel 2 Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
IM3 : XDMAC Channel 3 Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
IM4 : XDMAC Channel 4 Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
IM5 : XDMAC Channel 5 Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
IM6 : XDMAC Channel 6 Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
IM7 : XDMAC Channel 7 Interrupt Mask Bit
bits : 7 - 7 (1 bit)
access : read-only
IM8 : XDMAC Channel 8 Interrupt Mask Bit
bits : 8 - 8 (1 bit)
access : read-only
IM9 : XDMAC Channel 9 Interrupt Mask Bit
bits : 9 - 9 (1 bit)
access : read-only
IM10 : XDMAC Channel 10 Interrupt Mask Bit
bits : 10 - 10 (1 bit)
access : read-only
IM11 : XDMAC Channel 11 Interrupt Mask Bit
bits : 11 - 11 (1 bit)
access : read-only
IM12 : XDMAC Channel 12 Interrupt Mask Bit
bits : 12 - 12 (1 bit)
access : read-only
IM13 : XDMAC Channel 13 Interrupt Mask Bit
bits : 13 - 13 (1 bit)
access : read-only
IM14 : XDMAC Channel 14 Interrupt Mask Bit
bits : 14 - 14 (1 bit)
access : read-only
IM15 : XDMAC Channel 15 Interrupt Mask Bit
bits : 15 - 15 (1 bit)
access : read-only
Channel Source Microblock Stride (chid = 3)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 3)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 4)
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 4)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 4)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 4)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 4)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 4)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 4)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 4)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 4)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 4)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 4)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 4)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IS0 : XDMAC Channel 0 Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
IS1 : XDMAC Channel 1 Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
IS2 : XDMAC Channel 2 Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
IS3 : XDMAC Channel 3 Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
IS4 : XDMAC Channel 4 Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
IS5 : XDMAC Channel 5 Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
IS6 : XDMAC Channel 6 Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
IS7 : XDMAC Channel 7 Interrupt Status Bit
bits : 7 - 7 (1 bit)
access : read-only
IS8 : XDMAC Channel 8 Interrupt Status Bit
bits : 8 - 8 (1 bit)
access : read-only
IS9 : XDMAC Channel 9 Interrupt Status Bit
bits : 9 - 9 (1 bit)
access : read-only
IS10 : XDMAC Channel 10 Interrupt Status Bit
bits : 10 - 10 (1 bit)
access : read-only
IS11 : XDMAC Channel 11 Interrupt Status Bit
bits : 11 - 11 (1 bit)
access : read-only
IS12 : XDMAC Channel 12 Interrupt Status Bit
bits : 12 - 12 (1 bit)
access : read-only
IS13 : XDMAC Channel 13 Interrupt Status Bit
bits : 13 - 13 (1 bit)
access : read-only
IS14 : XDMAC Channel 14 Interrupt Status Bit
bits : 14 - 14 (1 bit)
access : read-only
IS15 : XDMAC Channel 15 Interrupt Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Channel Source Microblock Stride (chid = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 5)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 5)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 5)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 5)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 5)
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EN0 : XDMAC Channel 0 Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
EN1 : XDMAC Channel 1 Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
EN2 : XDMAC Channel 2 Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
EN3 : XDMAC Channel 3 Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
EN4 : XDMAC Channel 4 Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
EN5 : XDMAC Channel 5 Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
EN6 : XDMAC Channel 6 Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
EN7 : XDMAC Channel 7 Enable Bit
bits : 7 - 7 (1 bit)
access : write-only
EN8 : XDMAC Channel 8 Enable Bit
bits : 8 - 8 (1 bit)
access : write-only
EN9 : XDMAC Channel 9 Enable Bit
bits : 9 - 9 (1 bit)
access : write-only
EN10 : XDMAC Channel 10 Enable Bit
bits : 10 - 10 (1 bit)
access : write-only
EN11 : XDMAC Channel 11 Enable Bit
bits : 11 - 11 (1 bit)
access : write-only
EN12 : XDMAC Channel 12 Enable Bit
bits : 12 - 12 (1 bit)
access : write-only
EN13 : XDMAC Channel 13 Enable Bit
bits : 13 - 13 (1 bit)
access : write-only
EN14 : XDMAC Channel 14 Enable Bit
bits : 14 - 14 (1 bit)
access : write-only
EN15 : XDMAC Channel 15 Enable Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 5)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 5)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 6)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 6)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 6)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 6)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 6)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 6)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 6)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 6)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 6)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Disable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DI0 : XDMAC Channel 0 Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
DI1 : XDMAC Channel 1 Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DI2 : XDMAC Channel 2 Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
DI3 : XDMAC Channel 3 Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
DI4 : XDMAC Channel 4 Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
DI5 : XDMAC Channel 5 Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
DI6 : XDMAC Channel 6 Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
DI7 : XDMAC Channel 7 Disable Bit
bits : 7 - 7 (1 bit)
access : write-only
DI8 : XDMAC Channel 8 Disable Bit
bits : 8 - 8 (1 bit)
access : write-only
DI9 : XDMAC Channel 9 Disable Bit
bits : 9 - 9 (1 bit)
access : write-only
DI10 : XDMAC Channel 10 Disable Bit
bits : 10 - 10 (1 bit)
access : write-only
DI11 : XDMAC Channel 11 Disable Bit
bits : 11 - 11 (1 bit)
access : write-only
DI12 : XDMAC Channel 12 Disable Bit
bits : 12 - 12 (1 bit)
access : write-only
DI13 : XDMAC Channel 13 Disable Bit
bits : 13 - 13 (1 bit)
access : write-only
DI14 : XDMAC Channel 14 Disable Bit
bits : 14 - 14 (1 bit)
access : write-only
DI15 : XDMAC Channel 15 Disable Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 6)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 6)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 7)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 7)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 7)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 7)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 7)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 7)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 7)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 7)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 7)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 7)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 7)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 7)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ST0 : XDMAC Channel 0 Status Bit
bits : 0 - 0 (1 bit)
access : read-only
ST1 : XDMAC Channel 1 Status Bit
bits : 1 - 1 (1 bit)
access : read-only
ST2 : XDMAC Channel 2 Status Bit
bits : 2 - 2 (1 bit)
access : read-only
ST3 : XDMAC Channel 3 Status Bit
bits : 3 - 3 (1 bit)
access : read-only
ST4 : XDMAC Channel 4 Status Bit
bits : 4 - 4 (1 bit)
access : read-only
ST5 : XDMAC Channel 5 Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ST6 : XDMAC Channel 6 Status Bit
bits : 6 - 6 (1 bit)
access : read-only
ST7 : XDMAC Channel 7 Status Bit
bits : 7 - 7 (1 bit)
access : read-only
ST8 : XDMAC Channel 8 Status Bit
bits : 8 - 8 (1 bit)
access : read-only
ST9 : XDMAC Channel 9 Status Bit
bits : 9 - 9 (1 bit)
access : read-only
ST10 : XDMAC Channel 10 Status Bit
bits : 10 - 10 (1 bit)
access : read-only
ST11 : XDMAC Channel 11 Status Bit
bits : 11 - 11 (1 bit)
access : read-only
ST12 : XDMAC Channel 12 Status Bit
bits : 12 - 12 (1 bit)
access : read-only
ST13 : XDMAC Channel 13 Status Bit
bits : 13 - 13 (1 bit)
access : read-only
ST14 : XDMAC Channel 14 Status Bit
bits : 14 - 14 (1 bit)
access : read-only
ST15 : XDMAC Channel 15 Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Channel Source Microblock Stride (chid = 7)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 7)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 8)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 8)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 8)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 8)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 8)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 8)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 8)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 8)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 8)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 8)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 8)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 8)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Read Suspend Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS0 : XDMAC Channel 0 Read Suspend Bit
bits : 0 - 0 (1 bit)
access : read-write
RS1 : XDMAC Channel 1 Read Suspend Bit
bits : 1 - 1 (1 bit)
access : read-write
RS2 : XDMAC Channel 2 Read Suspend Bit
bits : 2 - 2 (1 bit)
access : read-write
RS3 : XDMAC Channel 3 Read Suspend Bit
bits : 3 - 3 (1 bit)
access : read-write
RS4 : XDMAC Channel 4 Read Suspend Bit
bits : 4 - 4 (1 bit)
access : read-write
RS5 : XDMAC Channel 5 Read Suspend Bit
bits : 5 - 5 (1 bit)
access : read-write
RS6 : XDMAC Channel 6 Read Suspend Bit
bits : 6 - 6 (1 bit)
access : read-write
RS7 : XDMAC Channel 7 Read Suspend Bit
bits : 7 - 7 (1 bit)
access : read-write
RS8 : XDMAC Channel 8 Read Suspend Bit
bits : 8 - 8 (1 bit)
access : read-write
RS9 : XDMAC Channel 9 Read Suspend Bit
bits : 9 - 9 (1 bit)
access : read-write
RS10 : XDMAC Channel 10 Read Suspend Bit
bits : 10 - 10 (1 bit)
access : read-write
RS11 : XDMAC Channel 11 Read Suspend Bit
bits : 11 - 11 (1 bit)
access : read-write
RS12 : XDMAC Channel 12 Read Suspend Bit
bits : 12 - 12 (1 bit)
access : read-write
RS13 : XDMAC Channel 13 Read Suspend Bit
bits : 13 - 13 (1 bit)
access : read-write
RS14 : XDMAC Channel 14 Read Suspend Bit
bits : 14 - 14 (1 bit)
access : read-write
RS15 : XDMAC Channel 15 Read Suspend Bit
bits : 15 - 15 (1 bit)
access : read-write
Channel Source Microblock Stride (chid = 8)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 8)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 9)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 9)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 9)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 9)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 9)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 9)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 9)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 9)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 9)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 9)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 9)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 9)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Write Suspend Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WS0 : XDMAC Channel 0 Write Suspend Bit
bits : 0 - 0 (1 bit)
access : read-write
WS1 : XDMAC Channel 1 Write Suspend Bit
bits : 1 - 1 (1 bit)
access : read-write
WS2 : XDMAC Channel 2 Write Suspend Bit
bits : 2 - 2 (1 bit)
access : read-write
WS3 : XDMAC Channel 3 Write Suspend Bit
bits : 3 - 3 (1 bit)
access : read-write
WS4 : XDMAC Channel 4 Write Suspend Bit
bits : 4 - 4 (1 bit)
access : read-write
WS5 : XDMAC Channel 5 Write Suspend Bit
bits : 5 - 5 (1 bit)
access : read-write
WS6 : XDMAC Channel 6 Write Suspend Bit
bits : 6 - 6 (1 bit)
access : read-write
WS7 : XDMAC Channel 7 Write Suspend Bit
bits : 7 - 7 (1 bit)
access : read-write
WS8 : XDMAC Channel 8 Write Suspend Bit
bits : 8 - 8 (1 bit)
access : read-write
WS9 : XDMAC Channel 9 Write Suspend Bit
bits : 9 - 9 (1 bit)
access : read-write
WS10 : XDMAC Channel 10 Write Suspend Bit
bits : 10 - 10 (1 bit)
access : read-write
WS11 : XDMAC Channel 11 Write Suspend Bit
bits : 11 - 11 (1 bit)
access : read-write
WS12 : XDMAC Channel 12 Write Suspend Bit
bits : 12 - 12 (1 bit)
access : read-write
WS13 : XDMAC Channel 13 Write Suspend Bit
bits : 13 - 13 (1 bit)
access : read-write
WS14 : XDMAC Channel 14 Write Suspend Bit
bits : 14 - 14 (1 bit)
access : read-write
WS15 : XDMAC Channel 15 Write Suspend Bit
bits : 15 - 15 (1 bit)
access : read-write
Channel Source Microblock Stride (chid = 9)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 9)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 10)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 10)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 10)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 10)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 10)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 10)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 10)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 10)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 10)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 10)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 10)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 10)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Read Write Suspend Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RWS0 : XDMAC Channel 0 Read Write Suspend Bit
bits : 0 - 0 (1 bit)
access : write-only
RWS1 : XDMAC Channel 1 Read Write Suspend Bit
bits : 1 - 1 (1 bit)
access : write-only
RWS2 : XDMAC Channel 2 Read Write Suspend Bit
bits : 2 - 2 (1 bit)
access : write-only
RWS3 : XDMAC Channel 3 Read Write Suspend Bit
bits : 3 - 3 (1 bit)
access : write-only
RWS4 : XDMAC Channel 4 Read Write Suspend Bit
bits : 4 - 4 (1 bit)
access : write-only
RWS5 : XDMAC Channel 5 Read Write Suspend Bit
bits : 5 - 5 (1 bit)
access : write-only
RWS6 : XDMAC Channel 6 Read Write Suspend Bit
bits : 6 - 6 (1 bit)
access : write-only
RWS7 : XDMAC Channel 7 Read Write Suspend Bit
bits : 7 - 7 (1 bit)
access : write-only
RWS8 : XDMAC Channel 8 Read Write Suspend Bit
bits : 8 - 8 (1 bit)
access : write-only
RWS9 : XDMAC Channel 9 Read Write Suspend Bit
bits : 9 - 9 (1 bit)
access : write-only
RWS10 : XDMAC Channel 10 Read Write Suspend Bit
bits : 10 - 10 (1 bit)
access : write-only
RWS11 : XDMAC Channel 11 Read Write Suspend Bit
bits : 11 - 11 (1 bit)
access : write-only
RWS12 : XDMAC Channel 12 Read Write Suspend Bit
bits : 12 - 12 (1 bit)
access : write-only
RWS13 : XDMAC Channel 13 Read Write Suspend Bit
bits : 13 - 13 (1 bit)
access : write-only
RWS14 : XDMAC Channel 14 Read Write Suspend Bit
bits : 14 - 14 (1 bit)
access : write-only
RWS15 : XDMAC Channel 15 Read Write Suspend Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 10)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 10)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 11)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 11)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 11)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 11)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 11)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 11)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 11)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 11)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 11)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 11)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 11)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 11)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Read Write Resume Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RWR0 : XDMAC Channel 0 Read Write Resume Bit
bits : 0 - 0 (1 bit)
access : write-only
RWR1 : XDMAC Channel 1 Read Write Resume Bit
bits : 1 - 1 (1 bit)
access : write-only
RWR2 : XDMAC Channel 2 Read Write Resume Bit
bits : 2 - 2 (1 bit)
access : write-only
RWR3 : XDMAC Channel 3 Read Write Resume Bit
bits : 3 - 3 (1 bit)
access : write-only
RWR4 : XDMAC Channel 4 Read Write Resume Bit
bits : 4 - 4 (1 bit)
access : write-only
RWR5 : XDMAC Channel 5 Read Write Resume Bit
bits : 5 - 5 (1 bit)
access : write-only
RWR6 : XDMAC Channel 6 Read Write Resume Bit
bits : 6 - 6 (1 bit)
access : write-only
RWR7 : XDMAC Channel 7 Read Write Resume Bit
bits : 7 - 7 (1 bit)
access : write-only
RWR8 : XDMAC Channel 8 Read Write Resume Bit
bits : 8 - 8 (1 bit)
access : write-only
RWR9 : XDMAC Channel 9 Read Write Resume Bit
bits : 9 - 9 (1 bit)
access : write-only
RWR10 : XDMAC Channel 10 Read Write Resume Bit
bits : 10 - 10 (1 bit)
access : write-only
RWR11 : XDMAC Channel 11 Read Write Resume Bit
bits : 11 - 11 (1 bit)
access : write-only
RWR12 : XDMAC Channel 12 Read Write Resume Bit
bits : 12 - 12 (1 bit)
access : write-only
RWR13 : XDMAC Channel 13 Read Write Resume Bit
bits : 13 - 13 (1 bit)
access : write-only
RWR14 : XDMAC Channel 14 Read Write Resume Bit
bits : 14 - 14 (1 bit)
access : write-only
RWR15 : XDMAC Channel 15 Read Write Resume Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 11)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 11)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 12)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 12)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 12)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 12)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 12)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 12)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 12)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 12)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 12)
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 12)
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 12)
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 12)
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Software Request Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ0 : XDMAC Channel 0 Software Request Bit
bits : 0 - 0 (1 bit)
access : write-only
SWREQ1 : XDMAC Channel 1 Software Request Bit
bits : 1 - 1 (1 bit)
access : write-only
SWREQ2 : XDMAC Channel 2 Software Request Bit
bits : 2 - 2 (1 bit)
access : write-only
SWREQ3 : XDMAC Channel 3 Software Request Bit
bits : 3 - 3 (1 bit)
access : write-only
SWREQ4 : XDMAC Channel 4 Software Request Bit
bits : 4 - 4 (1 bit)
access : write-only
SWREQ5 : XDMAC Channel 5 Software Request Bit
bits : 5 - 5 (1 bit)
access : write-only
SWREQ6 : XDMAC Channel 6 Software Request Bit
bits : 6 - 6 (1 bit)
access : write-only
SWREQ7 : XDMAC Channel 7 Software Request Bit
bits : 7 - 7 (1 bit)
access : write-only
SWREQ8 : XDMAC Channel 8 Software Request Bit
bits : 8 - 8 (1 bit)
access : write-only
SWREQ9 : XDMAC Channel 9 Software Request Bit
bits : 9 - 9 (1 bit)
access : write-only
SWREQ10 : XDMAC Channel 10 Software Request Bit
bits : 10 - 10 (1 bit)
access : write-only
SWREQ11 : XDMAC Channel 11 Software Request Bit
bits : 11 - 11 (1 bit)
access : write-only
SWREQ12 : XDMAC Channel 12 Software Request Bit
bits : 12 - 12 (1 bit)
access : write-only
SWREQ13 : XDMAC Channel 13 Software Request Bit
bits : 13 - 13 (1 bit)
access : write-only
SWREQ14 : XDMAC Channel 14 Software Request Bit
bits : 14 - 14 (1 bit)
access : write-only
SWREQ15 : XDMAC Channel 15 Software Request Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 12)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 12)
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 13)
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 13)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 13)
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 13)
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 13)
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 13)
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 13)
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 13)
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 13)
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 13)
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 13)
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 13)
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Channel Software Request Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRS0 : XDMAC Channel 0 Software Request Status Bit
bits : 0 - 0 (1 bit)
access : read-only
SWRS1 : XDMAC Channel 1 Software Request Status Bit
bits : 1 - 1 (1 bit)
access : read-only
SWRS2 : XDMAC Channel 2 Software Request Status Bit
bits : 2 - 2 (1 bit)
access : read-only
SWRS3 : XDMAC Channel 3 Software Request Status Bit
bits : 3 - 3 (1 bit)
access : read-only
SWRS4 : XDMAC Channel 4 Software Request Status Bit
bits : 4 - 4 (1 bit)
access : read-only
SWRS5 : XDMAC Channel 5 Software Request Status Bit
bits : 5 - 5 (1 bit)
access : read-only
SWRS6 : XDMAC Channel 6 Software Request Status Bit
bits : 6 - 6 (1 bit)
access : read-only
SWRS7 : XDMAC Channel 7 Software Request Status Bit
bits : 7 - 7 (1 bit)
access : read-only
SWRS8 : XDMAC Channel 8 Software Request Status Bit
bits : 8 - 8 (1 bit)
access : read-only
SWRS9 : XDMAC Channel 9 Software Request Status Bit
bits : 9 - 9 (1 bit)
access : read-only
SWRS10 : XDMAC Channel 10 Software Request Status Bit
bits : 10 - 10 (1 bit)
access : read-only
SWRS11 : XDMAC Channel 11 Software Request Status Bit
bits : 11 - 11 (1 bit)
access : read-only
SWRS12 : XDMAC Channel 12 Software Request Status Bit
bits : 12 - 12 (1 bit)
access : read-only
SWRS13 : XDMAC Channel 13 Software Request Status Bit
bits : 13 - 13 (1 bit)
access : read-only
SWRS14 : XDMAC Channel 14 Software Request Status Bit
bits : 14 - 14 (1 bit)
access : read-only
SWRS15 : XDMAC Channel 15 Software Request Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Channel Source Microblock Stride (chid = 13)
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 13)
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 14)
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 14)
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 14)
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 14)
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 14)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 14)
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 14)
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 14)
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 14)
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 14)
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 14)
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 14)
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CGDISREG : Configuration Registers Clock Gating Disable
bits : 0 - 0 (1 bit)
access : read-write
CGDISPIPE : Pipeline Clock Gating Disable
bits : 1 - 1 (1 bit)
access : read-write
CGDISFIFO : FIFO Clock Gating Disable
bits : 2 - 2 (1 bit)
access : read-write
CGDISIF : Bus Interface Clock Gating Disable
bits : 3 - 3 (1 bit)
access : read-write
BXKBEN : Boundary X Kilobyte Enable
bits : 8 - 8 (1 bit)
access : read-write
Global Channel Software Flush Request Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWF0 : XDMAC Channel 0 Software Flush Request Bit
bits : 0 - 0 (1 bit)
access : write-only
SWF1 : XDMAC Channel 1 Software Flush Request Bit
bits : 1 - 1 (1 bit)
access : write-only
SWF2 : XDMAC Channel 2 Software Flush Request Bit
bits : 2 - 2 (1 bit)
access : write-only
SWF3 : XDMAC Channel 3 Software Flush Request Bit
bits : 3 - 3 (1 bit)
access : write-only
SWF4 : XDMAC Channel 4 Software Flush Request Bit
bits : 4 - 4 (1 bit)
access : write-only
SWF5 : XDMAC Channel 5 Software Flush Request Bit
bits : 5 - 5 (1 bit)
access : write-only
SWF6 : XDMAC Channel 6 Software Flush Request Bit
bits : 6 - 6 (1 bit)
access : write-only
SWF7 : XDMAC Channel 7 Software Flush Request Bit
bits : 7 - 7 (1 bit)
access : write-only
SWF8 : XDMAC Channel 8 Software Flush Request Bit
bits : 8 - 8 (1 bit)
access : write-only
SWF9 : XDMAC Channel 9 Software Flush Request Bit
bits : 9 - 9 (1 bit)
access : write-only
SWF10 : XDMAC Channel 10 Software Flush Request Bit
bits : 10 - 10 (1 bit)
access : write-only
SWF11 : XDMAC Channel 11 Software Flush Request Bit
bits : 11 - 11 (1 bit)
access : write-only
SWF12 : XDMAC Channel 12 Software Flush Request Bit
bits : 12 - 12 (1 bit)
access : write-only
SWF13 : XDMAC Channel 13 Software Flush Request Bit
bits : 13 - 13 (1 bit)
access : write-only
SWF14 : XDMAC Channel 14 Software Flush Request Bit
bits : 14 - 14 (1 bit)
access : write-only
SWF15 : XDMAC Channel 15 Software Flush Request Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 14)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 14)
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 15)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 15)
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 15)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 15)
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 15)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 15)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 15)
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 15)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 15)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 15)
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 15)
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 15)
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Channel Source Microblock Stride (chid = 15)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 15)
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 0)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 0)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 0)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 0)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 0)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 0)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 0)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Weighted Arbiter Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PW0 : Pool Weight 0
bits : 0 - 3 (4 bit)
access : read-write
PW1 : Pool Weight 1
bits : 4 - 7 (4 bit)
access : read-write
PW2 : Pool Weight 2
bits : 8 - 11 (4 bit)
access : read-write
PW3 : Pool Weight 3
bits : 12 - 15 (4 bit)
access : read-write
Channel Source Microblock Stride (chid = 0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 0)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 1)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 1)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 1)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 1)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 1)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 1)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 1)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 1)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 1)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 1)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 1)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 1)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
Global Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IE0 : XDMAC Channel 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
IE1 : XDMAC Channel 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
IE2 : XDMAC Channel 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
IE3 : XDMAC Channel 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
IE4 : XDMAC Channel 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
IE5 : XDMAC Channel 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
IE6 : XDMAC Channel 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
IE7 : XDMAC Channel 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : write-only
IE8 : XDMAC Channel 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : write-only
IE9 : XDMAC Channel 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : write-only
IE10 : XDMAC Channel 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : write-only
IE11 : XDMAC Channel 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : write-only
IE12 : XDMAC Channel 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : write-only
IE13 : XDMAC Channel 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : write-only
IE14 : XDMAC Channel 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : write-only
IE15 : XDMAC Channel 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : write-only
Channel Source Microblock Stride (chid = 1)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Destination Microblock Stride (chid = 1)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write
Channel Interrupt Enable Register (chid = 2)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only
LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only
DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only
FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Disable Register (chid = 2)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only
LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only
DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only
FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only
RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only
WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only
ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only
Channel Interrupt Mask Register (chid = 2)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only
LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only
DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only
FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Interrupt Status Register (chid = 2)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only
LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only
DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only
FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only
RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only
WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only
ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Channel Source Address Register (chid = 2)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Destination Address Register (chid = 2)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel Next Descriptor Address Register (chid = 2)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write
NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write
Channel Next Descriptor Control Register (chid = 2)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DSCR_FETCH_DIS
Descriptor fetch is disabled.
1 : DSCR_FETCH_EN
Descriptor fetch is enabled.
End of enumeration elements list.
NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SRC_PARAMS_UNCHANGED
Source parameters remain unchanged.
1 : SRC_PARAMS_UPDATED
Source parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DST_PARAMS_UNCHANGED
Destination parameters remain unchanged.
1 : DST_PARAMS_UPDATED
Destination parameters are updated when the descriptor is retrieved.
End of enumeration elements list.
NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x0 : NDV0
Next Descriptor View 0
0x1 : NDV1
Next Descriptor View 1
0x2 : NDV2
Next Descriptor View 2
0x3 : NDV3
Next Descriptor View 3
End of enumeration elements list.
Channel Microblock Control Register (chid = 2)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write
Channel Block Control Register (chid = 2)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write
Channel Configuration Register (chid = 2)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MEM_TRAN
Self-triggered mode (memory-to-memory transfer).
1 : PER_TRAN
Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).
End of enumeration elements list.
MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : SINGLE
The memory burst size is set to one.
0x1 : FOUR
The memory burst size is set to four.
0x2 : EIGHT
The memory burst size is set to eight.
0x3 : SIXTEEN
The memory burst size is set to sixteen.
End of enumeration elements list.
DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : PER2MEM
Peripheral-to-memory transfer.
1 : MEM2PER
Memory-to-peripheral transfer.
End of enumeration elements list.
PROT : Channel x Protection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : HWR_CONNECTED
Hardware request line is connected to the peripheral request line.
1 : SWR_CONNECTED
Software request is connected to the peripheral request line.
End of enumeration elements list.
MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL_MODE
Memset is not activated.
1 : HW_MODE
Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.
End of enumeration elements list.
CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : CHK_1
1 data transferred
0x1 : CHK_2
2 data transferred
0x2 : CHK_4
4 data transferred
0x3 : CHK_8
8 data transferred
0x4 : CHK_16
16 data transferred
End of enumeration elements list.
DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : BYTE
The data size is set to 8 bits
0x1 : HALFWORD
The data size is set to 16 bits
0x2 : WORD
The data size is set to 32 bits
0x3 : DWORD
The data size is set to 64 bits
End of enumeration elements list.
SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is read through the system bus interface 0.
1 : AHB_IF1
The data is read through the system bus interface 1.
End of enumeration elements list.
DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : AHB_IF0
The data is written through the system bus interface 0.
1 : AHB_IF1
The data is written though the system bus interface 1.
End of enumeration elements list.
SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.
End of enumeration elements list.
DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : FIXED_AM
The address remains unchanged.
0x1 : INCREMENTED_AM
The addressing mode is incremented (the increment size is set to the data size).
0x2 : UBS_AM
The microblock stride is added at the microblock boundary.
0x3 : UBS_DS_AM
The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.
End of enumeration elements list.
INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : IN_PROGRESS
Channel initialization is in progress.
1 : TERMINATED
Channel initialization is completed.
End of enumeration elements list.
RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active read transaction on the bus.
1 : IN_PROGRESS
A read transaction is in progress.
End of enumeration elements list.
WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DONE
No active write transaction on the bus.
1 : IN_PROGRESS
A write transaction is in progress.
End of enumeration elements list.
PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write
Channel Data Stride Memory Set Pattern (chid = 2)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write
DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write
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