\n

AESB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IER

IDATAR[2]

IVR[1]

IDR

ODATAR[2]

IDATAR[3]

IMR

IVR[2]

ODATAR[3]

ISR

IVR[3]

KEYWR0

KEYWR1

KEYWR2

KEYWR3

MR

KEYWR[0]

IDATAR0

IDATAR1

IDATAR2

IDATAR3

ODATAR0

ODATAR1

ODATAR2

ODATAR3

IVR0

KEYWR[1]

IVR1

IVR2

IVR3

IDATAR[0]

KEYWR[2]

ODATAR[0]

KEYWR[3]

IVR[0]

IDATAR[1]

ODATAR[1]


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START SWRST

START : Start Processing
bits : 0 - 0 (1 bit)
access : write-only

SWRST : Software Reset
bits : 8 - 8 (1 bit)
access : write-only


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD

DATRDY : Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

URAD : Unspecified Register Access Detection Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only


IDATAR[2]

Input Data Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[2] IDATAR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


IVR[1]

Initialization Vector Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[1] IVR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD

DATRDY : Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

URAD : Unspecified Register Access Detection Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only


ODATAR[2]

Output Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[2] ODATAR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


IDATAR[3]

Input Data Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[3] IDATAR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD

DATRDY : Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

URAD : Unspecified Register Access Detection Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only


IVR[2]

Initialization Vector Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[2] IVR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


ODATAR[3]

Output Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[3] ODATAR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD URAT

DATRDY : Data Ready
bits : 0 - 0 (1 bit)
access : read-only

URAD : Unspecified Register Access Detection Status
bits : 8 - 8 (1 bit)
access : read-only

URAT : Unspecified Register Access
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

0x0 : IDR_WR_PROCESSING

Input Data Register written during the data processing when SMOD = 0x2 mode

0x1 : ODR_RD_PROCESSING

Output Data Register read during the data processing

0x2 : MR_WR_PROCESSING

Mode Register written during the data processing

0x3 : ODR_RD_SUBKGEN

Output Data Register read during the sub-keys generation

0x4 : MR_WR_SUBKGEN

Mode Register written during the sub-keys generation

0x5 : WOR_RD_ACCESS

Write-only register read access

End of enumeration elements list.


IVR[3]

Initialization Vector Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[3] IVR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


KEYWR0

Key Word Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

KEYWR0 KEYWR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


KEYWR1

Key Word Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

KEYWR1 KEYWR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


KEYWR2

Key Word Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

KEYWR2 KEYWR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


KEYWR3

Key Word Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

KEYWR3 KEYWR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIPHER AAHB DUALBUFF PROCDLY SMOD OPMOD LOD CKEY

CIPHER : Processing Mode
bits : 0 - 0 (1 bit)
access : read-write

AAHB : Automatic Bridge Mode
bits : 2 - 2 (1 bit)
access : read-write

DUALBUFF : Dual Input Buffer
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0x0 : INACTIVE

AESB_IDATARx cannot be written during processing of previous block.

0x1 : ACTIVE

AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files.

End of enumeration elements list.

PROCDLY : Processing Delay
bits : 4 - 7 (4 bit)
access : read-write

SMOD : Start Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : MANUAL_START

Manual mode

0x1 : AUTO_START

Auto mode

0x2 : IDATAR0_START

AESB_IDATAR0 access only Auto mode

End of enumeration elements list.

OPMOD : Operating Mode
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x0 : ECB

Electronic Code Book mode

0x1 : CBC

Cipher Block Chaining mode

0x4 : CTR

Counter mode (16-bit internal counter)

End of enumeration elements list.

LOD : Last Output Data Mode
bits : 15 - 15 (1 bit)
access : read-write

CKEY : Key
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

0xE : PASSWD

This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR register, any value can be written, including that of 0xE.Always reads as 0.

End of enumeration elements list.


KEYWR[0]

Key Word Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[0] KEYWR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


IDATAR0

Input Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDATAR0 IDATAR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


IDATAR1

Input Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDATAR1 IDATAR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


IDATAR2

Input Data Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDATAR2 IDATAR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


IDATAR3

Input Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDATAR3 IDATAR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


ODATAR0

Output Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

ODATAR0 ODATAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


ODATAR1

Output Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

ODATAR1 ODATAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


ODATAR2

Output Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

ODATAR2 ODATAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


ODATAR3

Output Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

ODATAR3 ODATAR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


IVR0

Initialization Vector Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IVR0 IVR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


KEYWR[1]

Key Word Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[1] KEYWR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


IVR1

Initialization Vector Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IVR1 IVR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


IVR2

Initialization Vector Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IVR2 IVR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


IVR3

Initialization Vector Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IVR3 IVR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


IDATAR[0]

Input Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[0] IDATAR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


KEYWR[2]

Key Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[2] KEYWR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


ODATAR[0]

Output Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[0] ODATAR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only


KEYWR[3]

Key Word Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[3] KEYWR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only


IVR[0]

Initialization Vector Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[0] IVR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only


IDATAR[1]

Input Data Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[1] IDATAR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only


ODATAR[1]

Output Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[1] ODATAR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.