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EBI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

TPR1

DLL_OS

DLL_MAO

DLL_SO0

DLL_SO1

DLL_WRO

DLL_ADO

DLL_SM0

DLL_SM1

DLL_SM2

DLL_SM3

DLL_SSL0

DLL_SSL1

DLL_SSL2

DLL_SSL3

DLL_SSL4

DLL_SSL5

TPR2

DLL_SSL6

DLL_SSL7

DLL_SWR0

DLL_SWR1

DLL_SWR2

DLL_SWR3

DLL_SAD

LPR

MD

DLL_SM[0]

DLL_SSL[0]

LPDDR2_LPR

DLL_SWR[0]

LPDDR2_CAL_MR4

LPDDR2_TIM_CAL

IO_CALIBR

DLL_SM[1]

DLL_SSL[1]

OCMS

OCMS_KEY1

DLL_SWR[1]

RTR

OCMS_KEY2

CONF_ARBITER

DLL_SM[2]

TIMEOUT

DLL_SSL[2]

REQ_PORT_0123

REQ_PORT_4567

DLL_SWR[2]

BDW_PORT_0123

BDW_PORT_4567

DLL_SM[3]

RD_DATA_PATH

DLL_SSL[3]

DLL_SWR[3]

DLL_SSL[4]

CR

DLL_SSL[5]

DLL_SSL[6]

DLL_SSL[7]

TPR0

WPMR

WPSR


MR

MPDDRC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE MRS

MODE : MPDDRC Command Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : NORMAL_CMD

Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM.

0x1 : NOP_CMD

The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM.

0x2 : PRCGALL_CMD

The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

0x3 : LMR_CMD

The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM.

0x4 : RFSH_CMD

The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM.

0x5 : EXT_LMR_CMD

The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank.

0x6 : DEEP_MD

Deep Power mode: Access to Deep Powerdown mode

0x7 : LPDDR2_CMD

The MPDDRC issues an LPDDR2 Mode Register command when the device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM.

End of enumeration elements list.

MRS : Mode Register Select LPDDR2
bits : 8 - 15 (8 bit)
access : read-write


TPR1

MPDDRC Timing Parameter 1 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR1 TPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRFC TXSNR TXSRD TXP

TRFC : Row Cycle Delay
bits : 0 - 6 (7 bit)
access : read-write

TXSNR : Exit Self-refresh Delay to Non-Read Command
bits : 8 - 15 (8 bit)
access : read-write

TXSRD : Exit Self-refresh Delay to Read Command
bits : 16 - 23 (8 bit)
access : read-write

TXP : Exit Powerdown Delay to First Command
bits : 24 - 27 (4 bit)
access : read-write


DLL_OS

MPDDRC DLL Offset Selection Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_OS DLL_OS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELOFF

SELOFF : Offset Selection
bits : 0 - 0 (1 bit)
access : read-write


DLL_MAO

MPDDRC DLL Master Offset Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_MAO DLL_MAO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAOFF

MAOFF : Master Delay Line Offset
bits : 0 - 7 (8 bit)
access : read-write


DLL_SO0

MPDDRC DLL Slave Offset 0 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_SO0 DLL_SO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0OFF S1OFF S2OFF S3OFF

S0OFF : SLAVEx Delay Line Offset
bits : 0 - 7 (8 bit)
access : read-write

S1OFF : SLAVEx Delay Line Offset
bits : 8 - 15 (8 bit)
access : read-write

S2OFF : SLAVEx Delay Line Offset
bits : 16 - 23 (8 bit)
access : read-write

S3OFF : SLAVEx Delay Line Offset
bits : 24 - 31 (8 bit)
access : read-write


DLL_SO1

MPDDRC DLL Slave Offset 1 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_SO1 DLL_SO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S4OFF S5OFF S6OFF S7OFF

S4OFF : SLAVEx Delay Line Offset
bits : 0 - 7 (8 bit)
access : read-write

S5OFF : SLAVEx Delay Line Offset
bits : 8 - 15 (8 bit)
access : read-write

S6OFF : SLAVEx Delay Line Offset
bits : 16 - 23 (8 bit)
access : read-write

S7OFF : SLAVEx Delay Line Offset
bits : 24 - 31 (8 bit)
access : read-write


DLL_WRO

MPDDRC DLL CLKWR Offset Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_WRO DLL_WRO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR0OFF WR1OFF WR2OFF WR3OFF

WR0OFF : CLKWRx Delay Line Offset
bits : 0 - 7 (8 bit)
access : read-write

WR1OFF : CLKWRx Delay Line Offset
bits : 8 - 15 (8 bit)
access : read-write

WR2OFF : CLKWRx Delay Line Offset
bits : 16 - 23 (8 bit)
access : read-write

WR3OFF : CLKWRx Delay Line Offset
bits : 24 - 31 (8 bit)
access : read-write


DLL_ADO

MPDDRC DLL CLKAD Offset Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_ADO DLL_ADO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADOFF

ADOFF : CLKAD Delay Line Offset
bits : 0 - 7 (8 bit)
access : read-write


DLL_SM0

MPDDRC DLL Status Master 0 Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SM0 DLL_SM0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SM1

MPDDRC DLL Status Master 0 Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SM1 DLL_SM1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SM2

MPDDRC DLL Status Master 0 Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SM2 DLL_SM2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SM3

MPDDRC DLL Status Master 0 Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SM3 DLL_SM3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL0

MPDDRC DLL Status Slave 0 Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL0 DLL_SSL0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL1

MPDDRC DLL Status Slave 0 Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL1 DLL_SSL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL2

MPDDRC DLL Status Slave 0 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL2 DLL_SSL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL3

MPDDRC DLL Status Slave 0 Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL3 DLL_SSL3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL4

MPDDRC DLL Status Slave 0 Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL4 DLL_SSL4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL5

MPDDRC DLL Status Slave 0 Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL5 DLL_SSL5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


TPR2

MPDDRC Timing Parameter 2 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR2 TPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXARD TXARDS TRPA TRTP TFAW

TXARD : Exit Active Power Down Delay to Read Command in Mode "Fast Exit"
bits : 0 - 3 (4 bit)
access : read-write

TXARDS : Exit Active Power Down Delay to Read Command in Mode "Slow Exit"
bits : 4 - 7 (4 bit)
access : read-write

TRPA : Row Precharge All Delay
bits : 8 - 11 (4 bit)
access : read-write

TRTP : Read to Precharge
bits : 12 - 14 (3 bit)
access : read-write

TFAW : Four Active Windows
bits : 16 - 19 (4 bit)
access : read-write


DLL_SSL6

MPDDRC DLL Status Slave 0 Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL6 DLL_SSL6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL7

MPDDRC DLL Status Slave 0 Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SSL7 DLL_SSL7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SWR0

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SWR0 DLL_SWR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


DLL_SWR1

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SWR1 DLL_SWR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


DLL_SWR2

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SWR2 DLL_SWR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


DLL_SWR3

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DLL_SWR3 DLL_SWR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


DLL_SAD

MPDDRC DLL Status CLKAD Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SAD DLL_SAD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDCNT

ADDCNT : CLKAD Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


LPR

MPDDRC Low-power Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPR LPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPCB CLK_FR LPDDR2_PWOFF PASR DS TIMEOUT APDE UPD_MR

LPCB : Low-power Command Bit
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : NOLOWPOWER

Low-power feature is inhibited. No Powerdown, Self-refresh and Deep-power modes are issued to the DDR-SDRAM device.

0x1 : SELFREFRESH

The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access.

0x2 : POWERDOWN

The MPDDRC issues a Powerdown command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Powerdown mode when accessed and reenters it after the access.

0x3 : DEEPPOWERDOWN

The MPDDRC issues a Deep Powerdown command to the low-power DDR-SDRAM device.

End of enumeration elements list.

CLK_FR : Clock Frozen Command Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Clock(s) is/are not frozen.

1 : ENABLED

Clock(s) is/are frozen.

End of enumeration elements list.

LPDDR2_PWOFF : LPDDR2 - LPDDR3 Power Off Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

No power-off sequence applied to LPDDR2.

1 : ENABLED

A power-off sequence is applied to the LPDDR2 device. CKE is forced low.

End of enumeration elements list.

PASR : Partial Array Self-refresh
bits : 4 - 6 (3 bit)
access : read-write

DS : Drive Strength
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : DS_FULL

Full drive strength

0x1 : DS_HALF

Half drive strength

0x2 : DS_QUARTER

Quarter drive strength

0x3 : DS_OCTANT

Octant drive strength

End of enumeration elements list.

TIMEOUT : Time Between Last Transfer and Low-Power Mode
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

SDRAM Low-power mode is activated immediately after the end of the last transfer.

0x1 : DELAY_64_CLK

SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer.

0x2 : DELAY_128_CLK

SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer.

End of enumeration elements list.

APDE : Active Power Down Exit Time
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DDR2_FAST_EXIT

Fast Exit from Power Down. DDR2-SDRAM devices only.

1 : DDR2_SLOW_EXIT

Slow Exit from Power Down. DDR2-SDRAM devices only.

End of enumeration elements list.

UPD_MR : Update Load Mode Register and Extended Mode Register
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x0 : NO_UPDATE

Update of Load Mode and Extended Mode registers is disabled.

0x1 : UPDATE_SHAREDBUS

MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device.

0x2 : UPDATE_NOSHAREDBUS

MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode.

End of enumeration elements list.


MD

MPDDRC Memory Device Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MD MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD DBW

MD : Memory Device
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x3 : LPDDR_SDRAM

Low-power DDR1-SDRAM

0x6 : DDR2_SDRAM

DDR2-SDRAM

0x7 : LPDDR2_SDRAM

Low-power DDR2-SDRAM

End of enumeration elements list.

DBW : Data Bus Width
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DBW_32_BITS

Data bus width is 32 bits

1 : DBW_16_BITS

Data bus width is 16 bits.

End of enumeration elements list.


DLL_SM[0]

MPDDRC DLL Status Master 0 Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SM[0] DLL_SM[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL[0]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[0] DLL_SSL[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


LPDDR2_LPR

MPDDRC Low-power DDR2 Low-power Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPDDR2_LPR LPDDR2_LPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BK_MASK_PASR SEG_MASK DS

BK_MASK_PASR : Bank Mask Bit/PASR
bits : 0 - 7 (8 bit)
access : read-write

SEG_MASK : Segment Mask Bit
bits : 8 - 23 (16 bit)
access : read-write

DS : Drive Strength
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x1 : DS_34_3

34.3 ohm typical

0x2 : DS_40

40 ohm typical (default)

0x3 : DS_48

48 ohm typical

0x4 : DS_60

60 ohm typical

0x6 : DS_80

80 ohm typical

0x7 : DS_120

120 ohm typical

End of enumeration elements list.


DLL_SWR[0]

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SWR[0] DLL_SWR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


LPDDR2_CAL_MR4

MPDDRC Low-power DDR2 Calibration and MR4 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPDDR2_CAL_MR4 LPDDR2_CAL_MR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT_CAL MR4_READ

COUNT_CAL : LPDDR2Calibration Timer Count
bits : 0 - 15 (16 bit)
access : read-write

MR4_READ : Mode Register 4 Read Interval
bits : 16 - 31 (16 bit)
access : read-write


LPDDR2_TIM_CAL

MPDDRC Low-power DDR2 Timing Calibration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPDDR2_TIM_CAL LPDDR2_TIM_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZQCS

ZQCS : ZQ Calibration Short
bits : 0 - 7 (8 bit)
access : read-write


IO_CALIBR

MPDDRC I/O Calibration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IO_CALIBR IO_CALIBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDIV EN_CALIB TZQIO CALCODEP CALCODEN

RDIV : Resistor Divider, Output Driver Impedance
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x1 : RZQ_34

LPDDR2 serial impedance line = 34.3 ohms,DDR2/LPDDR1 serial impedance line: Not applicable

0x2 : RZQ_40_RZQ_33_3

LPDDR2 serial impedance line = 40 ohms,DDR2/LPDDR1 serial impedance line = 33.3 ohms

0x3 : RZQ_48_RZQ_40

LPDDR2 serial impedance line = 48 ohms,DDR2/LPDDR1 serial impedance line = 40 ohms

0x4 : RZQ_60_RZQ_50

LPDDR2 serial impedance line = 60 ohms,DDR2/LPDDR1 serial impedance line = 50 ohms

0x6 : RZQ_80_RZQ_66_7

LPDDR2 serial impedance line = 80 ohms,DDR2/LPDDR1 serial impedance line = 66.7 ohms

0x7 : RZQ_120_RZQ_100

LPDDR2 serial impedance line = 120 ohms,DDR2/LPDDR1 serial impedance line = 100 ohms

End of enumeration elements list.

EN_CALIB : Enable Calibration
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLE_CALIBRATION

Calibration is disabled.

1 : ENABLE_CALIBRATION

Calibration is enabled.

End of enumeration elements list.

TZQIO : IO Calibration
bits : 8 - 10 (3 bit)
access : read-write

CALCODEP : Number of Transistor P (read-only)
bits : 16 - 19 (4 bit)
access : read-write

CALCODEN : Number of Transistor N (read-only)
bits : 20 - 23 (4 bit)
access : read-write


DLL_SM[1]

MPDDRC DLL Status Master 0 Register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SM[1] DLL_SM[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL[1]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[1] DLL_SSL[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


OCMS

MPDDRC OCMS Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMS OCMS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCR_EN

SCR_EN : Scrambling Enable
bits : 0 - 0 (1 bit)
access : read-write


OCMS_KEY1

MPDDRC OCMS KEY1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OCMS_KEY1 OCMS_KEY1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY1

KEY1 : Off-chip Memory Scrambling (OCMS) Key Part 1
bits : 0 - 31 (32 bit)
access : write-only


DLL_SWR[1]

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SWR[1] DLL_SWR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


RTR

MPDDRC Refresh Timer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTR RTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT ADJ_REF REF_PB MR4_VALUE

COUNT : MPDDRC Refresh Timer Count
bits : 0 - 11 (12 bit)
access : read-write

ADJ_REF : Adjust Refresh Rate
bits : 16 - 16 (1 bit)
access : read-write

REF_PB : Refresh Per Bank
bits : 17 - 17 (1 bit)
access : read-write

MR4_VALUE : Content of MR4 Register (read-only)
bits : 20 - 22 (3 bit)
access : read-write


OCMS_KEY2

MPDDRC OCMS KEY2 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OCMS_KEY2 OCMS_KEY2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : Off-chip Memory Scrambling (OCMS) Key Part 2
bits : 0 - 31 (32 bit)
access : write-only


CONF_ARBITER

MPDDRC Configuration Arbiter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF_ARBITER CONF_ARBITER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARB BDW_MAX_CUR RQ_WD_P0 RQ_WD_P1 RQ_WD_P2 RQ_WD_P3 RQ_WD_P4 RQ_WD_P5 RQ_WD_P6 RQ_WD_P7 MA_PR_P0 MA_PR_P1 MA_PR_P2 MA_PR_P3 MA_PR_P4 MA_PR_P5 MA_PR_P6 MA_PR_P7 BDW_BURST_P0 BDW_BURST_P1 BDW_BURST_P2 BDW_BURST_P3 BDW_BURST_P4 BDW_BURST_P5 BDW_BURST_P6 BDW_BURST_P7

ARB : Type of Arbitration
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : ROUND

Round Robin

0x1 : NB_REQUEST

Request Policy

0x2 : BANDWIDTH

Bandwidth Policy

End of enumeration elements list.

BDW_MAX_CUR : Bandwidth Max or Current
bits : 3 - 3 (1 bit)
access : read-write

RQ_WD_P0 : Request or Word from Port X
bits : 8 - 8 (1 bit)
access : read-write

RQ_WD_P1 : Request or Word from Port X
bits : 9 - 9 (1 bit)
access : read-write

RQ_WD_P2 : Request or Word from Port X
bits : 10 - 10 (1 bit)
access : read-write

RQ_WD_P3 : Request or Word from Port X
bits : 11 - 11 (1 bit)
access : read-write

RQ_WD_P4 : Request or Word from Port X
bits : 12 - 12 (1 bit)
access : read-write

RQ_WD_P5 : Request or Word from Port X
bits : 13 - 13 (1 bit)
access : read-write

RQ_WD_P6 : Request or Word from Port X
bits : 14 - 14 (1 bit)
access : read-write

RQ_WD_P7 : Request or Word from Port X
bits : 15 - 15 (1 bit)
access : read-write

MA_PR_P0 : Master or Software Provide Information
bits : 16 - 16 (1 bit)
access : read-write

MA_PR_P1 : Master or Software Provide Information
bits : 17 - 17 (1 bit)
access : read-write

MA_PR_P2 : Master or Software Provide Information
bits : 18 - 18 (1 bit)
access : read-write

MA_PR_P3 : Master or Software Provide Information
bits : 19 - 19 (1 bit)
access : read-write

MA_PR_P4 : Master or Software Provide Information
bits : 20 - 20 (1 bit)
access : read-write

MA_PR_P5 : Master or Software Provide Information
bits : 21 - 21 (1 bit)
access : read-write

MA_PR_P6 : Master or Software Provide Information
bits : 22 - 22 (1 bit)
access : read-write

MA_PR_P7 : Master or Software Provide Information
bits : 23 - 23 (1 bit)
access : read-write

BDW_BURST_P0 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 24 - 24 (1 bit)
access : read-write

BDW_BURST_P1 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 25 - 25 (1 bit)
access : read-write

BDW_BURST_P2 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 26 - 26 (1 bit)
access : read-write

BDW_BURST_P3 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 27 - 27 (1 bit)
access : read-write

BDW_BURST_P4 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 28 - 28 (1 bit)
access : read-write

BDW_BURST_P5 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 29 - 29 (1 bit)
access : read-write

BDW_BURST_P6 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 30 - 30 (1 bit)
access : read-write

BDW_BURST_P7 : Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X
bits : 31 - 31 (1 bit)
access : read-write


DLL_SM[2]

MPDDRC DLL Status Master 0 Register
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SM[2] DLL_SM[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


TIMEOUT

MPDDRC Timeout Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMEOUT TIMEOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT_P0 TIMEOUT_P1 TIMEOUT_P2 TIMEOUT_P3 TIMEOUT_P4 TIMEOUT_P5 TIMEOUT_P6 TIMEOUT_P7

TIMEOUT_P0 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 0 - 3 (4 bit)
access : read-write

TIMEOUT_P1 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 4 - 7 (4 bit)
access : read-write

TIMEOUT_P2 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 8 - 11 (4 bit)
access : read-write

TIMEOUT_P3 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 12 - 15 (4 bit)
access : read-write

TIMEOUT_P4 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 16 - 19 (4 bit)
access : read-write

TIMEOUT_P5 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 20 - 23 (4 bit)
access : read-write

TIMEOUT_P6 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 24 - 27 (4 bit)
access : read-write

TIMEOUT_P7 : Timeout for Ports 0, 1, 2, 3, 4, 5, 6 and 7
bits : 28 - 31 (4 bit)
access : read-write


DLL_SSL[2]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[2] DLL_SSL[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


REQ_PORT_0123

MPDDRC Request Port 0-1-2-3 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_PORT_0123 REQ_PORT_0123 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRQ_NWD_BDW_P0 NRQ_NWD_BDW_P1 NRQ_NWD_BDW_P2 NRQ_NWD_BDW_P3

NRQ_NWD_BDW_P0 : Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3
bits : 0 - 7 (8 bit)
access : read-write

NRQ_NWD_BDW_P1 : Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3
bits : 8 - 15 (8 bit)
access : read-write

NRQ_NWD_BDW_P2 : Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3
bits : 16 - 23 (8 bit)
access : read-write

NRQ_NWD_BDW_P3 : Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3
bits : 24 - 31 (8 bit)
access : read-write


REQ_PORT_4567

MPDDRC Request Port 4-5-6-7 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQ_PORT_4567 REQ_PORT_4567 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRQ_NWD_BDW_P4 NRQ_NWD_BDW_P5 NRQ_NWD_BDW_P6 NRQ_NWD_BDW_P7

NRQ_NWD_BDW_P4 : Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7
bits : 0 - 7 (8 bit)
access : read-write

NRQ_NWD_BDW_P5 : Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7
bits : 8 - 15 (8 bit)
access : read-write

NRQ_NWD_BDW_P6 : Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7
bits : 16 - 23 (8 bit)
access : read-write

NRQ_NWD_BDW_P7 : Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7
bits : 24 - 31 (8 bit)
access : read-write


DLL_SWR[2]

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SWR[2] DLL_SWR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


BDW_PORT_0123

MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BDW_PORT_0123 BDW_PORT_0123 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDW_P0 BDW_P1 BDW_P2 BDW_P3

BDW_P0 : Current/Maximum Bandwidth from Port 0-1-2-3
bits : 0 - 6 (7 bit)
access : read-only

BDW_P1 : Current/Maximum Bandwidth from Port 0-1-2-3
bits : 8 - 14 (7 bit)
access : read-only

BDW_P2 : Current/Maximum Bandwidth from Port 0-1-2-3
bits : 16 - 22 (7 bit)
access : read-only

BDW_P3 : Current/Maximum Bandwidth from Port 0-1-2-3
bits : 24 - 30 (7 bit)
access : read-only


BDW_PORT_4567

MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BDW_PORT_4567 BDW_PORT_4567 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDW_P4 BDW_P5 BDW_P6 BDW_P7

BDW_P4 : Current/Maximum Bandwidth from Port 4-5-6-7
bits : 0 - 6 (7 bit)
access : read-only

BDW_P5 : Current/Maximum Bandwidth from Port 4-5-6-7
bits : 8 - 14 (7 bit)
access : read-only

BDW_P6 : Current/Maximum Bandwidth from Port 4-5-6-7
bits : 16 - 22 (7 bit)
access : read-only

BDW_P7 : Current/Maximum Bandwidth from Port 4-5-6-7
bits : 24 - 30 (7 bit)
access : read-only


DLL_SM[3]

MPDDRC DLL Status Master 0 Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SM[3] DLL_SM[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDINC MDDEC MDOVF MDLVAL MDCNT

MDINC : MASTERx Delay Increment
bits : 0 - 0 (1 bit)
access : read-only

MDDEC : MASTERx Delay Decrement
bits : 1 - 1 (1 bit)
access : read-only

MDOVF : MASTERx Delay Overflow Flag
bits : 2 - 2 (1 bit)
access : read-only

MDLVAL : MASTERx Delay Lock Value
bits : 8 - 15 (8 bit)
access : read-only

MDCNT : MASTERx Delay Counter Value
bits : 20 - 27 (8 bit)
access : read-only


RD_DATA_PATH

MPDDRC Read Data Path Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD_DATA_PATH RD_DATA_PATH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFT_SAMPLING

SHIFT_SAMPLING : Shift Sampling Point of Data
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : NO_SHIFT

Initial sampling point.

0x1 : SHIFT_ONE_CYCLE

Sampling point is shifted by one cycle.

0x2 : SHIFT_TWO_CYCLES

Sampling point is shifted by two cycles.

0x3 : SHIFT_THREE_CYCLES

Sampling point is shifted by three cycles, unique for LPDDR2.Not applicable for DDR2 and LPDDR1 devices.

End of enumeration elements list.


DLL_SSL[3]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[3] DLL_SSL[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SWR[3]

MPDDRC DLL Status CLKWR 0 Register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SWR[3] DLL_SWR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRDCNT

WRDCNT : CLKWRx Delay Counter Value
bits : 0 - 7 (8 bit)
access : read-only


DLL_SSL[4]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[4] DLL_SSL[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


CR

MPDDRC Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NC NR CAS DLL DIC_DS DIS_DLL ZQ OCD DQMS ENRDM LC_LPDDR1 NB NDQS DECOD UNAL

NC : Number of Column Bits
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : 9_COL_BITS

9 bits to define the column number, up to 512 columns

0x1 : 10_COL_BITS

10 bits to define the column number, up to 1024 columns

0x2 : 11_COL_BITS

11 bits to define the column number, up to 2048 columns

0x3 : 12_COL_BITS

12 bits to define the column number, up to 4096 columns

End of enumeration elements list.

NR : Number of Row Bits
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 11_ROW_BITS

11 bits to define the row number, up to 2048 rows

0x1 : 12_ROW_BITS

12 bits to define the row number, up to 4096 rows

0x2 : 13_ROW_BITS

13 bits to define the row number, up to 8192 rows

0x3 : 14_ROW_BITS

14 bits to define the row number, up to 16384 rows

End of enumeration elements list.

CAS : CAS Latency
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x2 : DDR_CAS2

LPDDR1 CAS Latency 2

0x3 : DDR_CAS3

DDR2/LPDDR2/LPDDR1 CAS Latency 3

End of enumeration elements list.

DLL : Reset DLL
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : RESET_DISABLED

Disable DLL reset

1 : RESET_ENABLED

Enable DLL reset

End of enumeration elements list.

DIC_DS : Output Driver Impedance Control (Drive Strength)
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DDR2_NORMALSTRENGTH

Normal drive strength (DDR2)

1 : DDR2_WEAKSTRENGTH

Weak drive strength (DDR2)

End of enumeration elements list.

DIS_DLL : DISABLE DLL
bits : 9 - 9 (1 bit)
access : read-write

ZQ : ZQ Calibration
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

0x0 : INIT

Calibration command after initialization

0x1 : LONG

Long calibration

0x2 : SHORT

Short calibration

0x3 : RESET

ZQ Reset

End of enumeration elements list.

OCD : Off-chip Driver
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x0 : DDR2_EXITCALIB

Exit from OCD Calibration mode and maintain settings

0x7 : DDR2_DEFAULT_CALIB

OCD calibration default

End of enumeration elements list.

DQMS : Mask Data is Shared
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_SHARED

DQM is not shared with another controller

1 : SHARED

DQM is shared with another controller

End of enumeration elements list.

ENRDM : Enable Read Measure
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : OFF

DQS/DDR_DATA phase error correction is disabled

1 : ON

DQS/DDR_DATA phase error correction is enabled

End of enumeration elements list.

LC_LPDDR1 : Low-cost Low-power DDR1
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_2_BANKS

Any type of memory devices except of low cost, low density Low Power DDR1.

1 : 2_BANKS_LPDDR1

Low-cost and low-density low-power DDR1. These devices have a density of 32 Mbits and are organized as two internal banks. To use this feature, the user has to define the type of memory and the data bus width (see Section 8.8 "MPDDRC Memory Device Register").The 16-bit memory device is organized as 2 banks, 9 columns and 11 rows.

End of enumeration elements list.

NB : Number of Banks
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : 4_BANKS

4-bank memory devices

1 : 8_BANKS

8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM devices.

End of enumeration elements list.

NDQS : Not DQS
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : ENABLED

Not DQS is enabled

1 : DISABLED

Not DQS is disabled

End of enumeration elements list.

DECOD : Type of Decoding
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SEQUENTIAL

Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank.

1 : INTERLEAVED

Method for address mapping where banks alternate at each DDR-SDRAM end of page of the current bank.

End of enumeration elements list.

UNAL : Support Unaligned Access
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : UNSUPPORTED

Unaligned access is not supported.

1 : SUPPORTED

Unaligned access is supported.

End of enumeration elements list.


DLL_SSL[5]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[5] DLL_SSL[5] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL[6]

MPDDRC DLL Status Slave 0 Register
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[6] DLL_SSL[6] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


DLL_SSL[7]

MPDDRC DLL Status Slave 0 Register
address_offset : 0xAD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DLL_SSL[7] DLL_SSL[7] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOVF SDCUDF SDERF SDCNT SDCVAL

SDCOVF : SLAVEx Delay Correction Overflow Flag
bits : 0 - 0 (1 bit)
access : read-only

SDCUDF : SLAVEx Delay Correction Underflow Flag
bits : 1 - 1 (1 bit)
access : read-only

SDERF : SLAVEx Delay Correction Error Flag
bits : 2 - 2 (1 bit)
access : read-only

SDCNT : SLAVEx Delay Counter Value
bits : 8 - 15 (8 bit)
access : read-only

SDCVAL : SLAVEx Delay Correction Value
bits : 20 - 27 (8 bit)
access : read-only


TPR0

MPDDRC Timing Parameter 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR0 TPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRAS TRCD TWR TRC TRP TRRD TWTR TMRD

TRAS : Active to Precharge Delay
bits : 0 - 3 (4 bit)
access : read-write

TRCD : Row to Column Delay
bits : 4 - 7 (4 bit)
access : read-write

TWR : Write Recovery Delay
bits : 8 - 11 (4 bit)
access : read-write

TRC : Row Cycle Delay
bits : 12 - 15 (4 bit)
access : read-write

TRP : Row Precharge Delay
bits : 16 - 19 (4 bit)
access : read-write

TRRD : Active BankA to Active BankB
bits : 20 - 23 (4 bit)
access : read-write

TWTR : Internal Write to Read Delay
bits : 24 - 27 (4 bit)
access : read-write

TMRD : Load Mode Register Command to Activate or Refresh Command
bits : 28 - 31 (4 bit)
access : read-write


WPMR

MPDDRC Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x444452 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

MPDDRC Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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