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PMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCER

PCER0

PCER1

PCDR1

PCSR1

PCK[2]

PCR

PCDR0

PCSR0

CKGR_UCKR

CKGR_MOR

CKGR_MCFR

CKGR_PLLAR

MCKR

USB

SMD

SCDR

PCK0

PCK1

PCK2

IER

IDR

SR

IMR

FOCR

SCSR

PCK[0]

PLLICPR

PCK[1]

WPMR

WPSR


SCER

System Clock Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCER SCER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DDRCK LCDCK SMDCK UHP UDP PCK0 PCK1 PCK2

DDRCK : DDR Clock Enable
bits : 2 - 2 (1 bit)
access : write-only

LCDCK : MCK2x Clock Enable
bits : 3 - 3 (1 bit)
access : write-only

SMDCK : SMD Clock Enable
bits : 4 - 4 (1 bit)
access : write-only

UHP : USB Host OHCI Clocks Enable
bits : 6 - 6 (1 bit)
access : write-only

UDP : USB Device Clock Enable
bits : 7 - 7 (1 bit)
access : write-only

PCK0 : Programmable Clock 0 Output Enable
bits : 8 - 8 (1 bit)
access : write-only

PCK1 : Programmable Clock 1 Output Enable
bits : 9 - 9 (1 bit)
access : write-only

PCK2 : Programmable Clock 2 Output Enable
bits : 10 - 10 (1 bit)
access : write-only


PCER0

Peripheral Clock Enable Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCER0 PCER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID2 PID3 PID4 PID5 PID6 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID2 : Peripheral Clock 2 Enable
bits : 2 - 2 (1 bit)
access : write-only

PID3 : Peripheral Clock 3 Enable
bits : 3 - 3 (1 bit)
access : write-only

PID4 : Peripheral Clock 4 Enable
bits : 4 - 4 (1 bit)
access : write-only

PID5 : Peripheral Clock 5 Enable
bits : 5 - 5 (1 bit)
access : write-only

PID6 : Peripheral Clock 6 Enable
bits : 6 - 6 (1 bit)
access : write-only

PID7 : Peripheral Clock 7 Enable
bits : 7 - 7 (1 bit)
access : write-only

PID8 : Peripheral Clock 8 Enable
bits : 8 - 8 (1 bit)
access : write-only

PID9 : Peripheral Clock 9 Enable
bits : 9 - 9 (1 bit)
access : write-only

PID10 : Peripheral Clock 10 Enable
bits : 10 - 10 (1 bit)
access : write-only

PID11 : Peripheral Clock 11 Enable
bits : 11 - 11 (1 bit)
access : write-only

PID12 : Peripheral Clock 12 Enable
bits : 12 - 12 (1 bit)
access : write-only

PID13 : Peripheral Clock 13 Enable
bits : 13 - 13 (1 bit)
access : write-only

PID14 : Peripheral Clock 14 Enable
bits : 14 - 14 (1 bit)
access : write-only

PID15 : Peripheral Clock 15 Enable
bits : 15 - 15 (1 bit)
access : write-only

PID16 : Peripheral Clock 16 Enable
bits : 16 - 16 (1 bit)
access : write-only

PID17 : Peripheral Clock 17 Enable
bits : 17 - 17 (1 bit)
access : write-only

PID18 : Peripheral Clock 18 Enable
bits : 18 - 18 (1 bit)
access : write-only

PID19 : Peripheral Clock 19 Enable
bits : 19 - 19 (1 bit)
access : write-only

PID20 : Peripheral Clock 20 Enable
bits : 20 - 20 (1 bit)
access : write-only

PID21 : Peripheral Clock 21 Enable
bits : 21 - 21 (1 bit)
access : write-only

PID22 : Peripheral Clock 22 Enable
bits : 22 - 22 (1 bit)
access : write-only

PID23 : Peripheral Clock 23 Enable
bits : 23 - 23 (1 bit)
access : write-only

PID24 : Peripheral Clock 24 Enable
bits : 24 - 24 (1 bit)
access : write-only

PID25 : Peripheral Clock 25 Enable
bits : 25 - 25 (1 bit)
access : write-only

PID26 : Peripheral Clock 26 Enable
bits : 26 - 26 (1 bit)
access : write-only

PID27 : Peripheral Clock 27 Enable
bits : 27 - 27 (1 bit)
access : write-only

PID28 : Peripheral Clock 28 Enable
bits : 28 - 28 (1 bit)
access : write-only

PID29 : Peripheral Clock 29 Enable
bits : 29 - 29 (1 bit)
access : write-only

PID30 : Peripheral Clock 30 Enable
bits : 30 - 30 (1 bit)
access : write-only

PID31 : Peripheral Clock 31 Enable
bits : 31 - 31 (1 bit)
access : write-only


PCER1

Peripheral Clock Enable Register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCER1 PCER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID36 PID37 PID38 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID54 PID55 PID56 PID57 PID58 PID59 PID60 PID61 PID62 PID63

PID32 : Peripheral Clock 32 Enable
bits : 0 - 0 (1 bit)
access : write-only

PID33 : Peripheral Clock 33 Enable
bits : 1 - 1 (1 bit)
access : write-only

PID34 : Peripheral Clock 34 Enable
bits : 2 - 2 (1 bit)
access : write-only

PID35 : Peripheral Clock 35 Enable
bits : 3 - 3 (1 bit)
access : write-only

PID36 : Peripheral Clock 36 Enable
bits : 4 - 4 (1 bit)
access : write-only

PID37 : Peripheral Clock 37 Enable
bits : 5 - 5 (1 bit)
access : write-only

PID38 : Peripheral Clock 38 Enable
bits : 6 - 6 (1 bit)
access : write-only

PID39 : Peripheral Clock 39 Enable
bits : 7 - 7 (1 bit)
access : write-only

PID40 : Peripheral Clock 40 Enable
bits : 8 - 8 (1 bit)
access : write-only

PID41 : Peripheral Clock 41 Enable
bits : 9 - 9 (1 bit)
access : write-only

PID42 : Peripheral Clock 42 Enable
bits : 10 - 10 (1 bit)
access : write-only

PID43 : Peripheral Clock 43 Enable
bits : 11 - 11 (1 bit)
access : write-only

PID44 : Peripheral Clock 44 Enable
bits : 12 - 12 (1 bit)
access : write-only

PID45 : Peripheral Clock 45 Enable
bits : 13 - 13 (1 bit)
access : write-only

PID46 : Peripheral Clock 46 Enable
bits : 14 - 14 (1 bit)
access : write-only

PID47 : Peripheral Clock 47 Enable
bits : 15 - 15 (1 bit)
access : write-only

PID48 : Peripheral Clock 48 Enable
bits : 16 - 16 (1 bit)
access : write-only

PID49 : Peripheral Clock 49 Enable
bits : 17 - 17 (1 bit)
access : write-only

PID50 : Peripheral Clock 50 Enable
bits : 18 - 18 (1 bit)
access : write-only

PID51 : Peripheral Clock 51 Enable
bits : 19 - 19 (1 bit)
access : write-only

PID52 : Peripheral Clock 52 Enable
bits : 20 - 20 (1 bit)
access : write-only

PID53 : Peripheral Clock 53 Enable
bits : 21 - 21 (1 bit)
access : write-only

PID54 : Peripheral Clock 54 Enable
bits : 22 - 22 (1 bit)
access : write-only

PID55 : Peripheral Clock 55 Enable
bits : 23 - 23 (1 bit)
access : write-only

PID56 : Peripheral Clock 56 Enable
bits : 24 - 24 (1 bit)
access : write-only

PID57 : Peripheral Clock 57 Enable
bits : 25 - 25 (1 bit)
access : write-only

PID58 : Peripheral Clock 58 Enable
bits : 26 - 26 (1 bit)
access : write-only

PID59 : Peripheral Clock 59 Enable
bits : 27 - 27 (1 bit)
access : write-only

PID60 : Peripheral Clock 60 Enable
bits : 28 - 28 (1 bit)
access : write-only

PID61 : Peripheral Clock 61 Enable
bits : 29 - 29 (1 bit)
access : write-only

PID62 : Peripheral Clock 62 Enable
bits : 30 - 30 (1 bit)
access : write-only

PID63 : Peripheral Clock 63 Enable
bits : 31 - 31 (1 bit)
access : write-only


PCDR1

Peripheral Clock Disable Register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCDR1 PCDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID36 PID37 PID38 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID54 PID55 PID56 PID57 PID58 PID59 PID60 PID61 PID62 PID63

PID32 : Peripheral Clock 32 Disable
bits : 0 - 0 (1 bit)
access : write-only

PID33 : Peripheral Clock 33 Disable
bits : 1 - 1 (1 bit)
access : write-only

PID34 : Peripheral Clock 34 Disable
bits : 2 - 2 (1 bit)
access : write-only

PID35 : Peripheral Clock 35 Disable
bits : 3 - 3 (1 bit)
access : write-only

PID36 : Peripheral Clock 36 Disable
bits : 4 - 4 (1 bit)
access : write-only

PID37 : Peripheral Clock 37 Disable
bits : 5 - 5 (1 bit)
access : write-only

PID38 : Peripheral Clock 38 Disable
bits : 6 - 6 (1 bit)
access : write-only

PID39 : Peripheral Clock 39 Disable
bits : 7 - 7 (1 bit)
access : write-only

PID40 : Peripheral Clock 40 Disable
bits : 8 - 8 (1 bit)
access : write-only

PID41 : Peripheral Clock 41 Disable
bits : 9 - 9 (1 bit)
access : write-only

PID42 : Peripheral Clock 42 Disable
bits : 10 - 10 (1 bit)
access : write-only

PID43 : Peripheral Clock 43 Disable
bits : 11 - 11 (1 bit)
access : write-only

PID44 : Peripheral Clock 44 Disable
bits : 12 - 12 (1 bit)
access : write-only

PID45 : Peripheral Clock 45 Disable
bits : 13 - 13 (1 bit)
access : write-only

PID46 : Peripheral Clock 46 Disable
bits : 14 - 14 (1 bit)
access : write-only

PID47 : Peripheral Clock 47 Disable
bits : 15 - 15 (1 bit)
access : write-only

PID48 : Peripheral Clock 48 Disable
bits : 16 - 16 (1 bit)
access : write-only

PID49 : Peripheral Clock 49 Disable
bits : 17 - 17 (1 bit)
access : write-only

PID50 : Peripheral Clock 50 Disable
bits : 18 - 18 (1 bit)
access : write-only

PID51 : Peripheral Clock 51 Disable
bits : 19 - 19 (1 bit)
access : write-only

PID52 : Peripheral Clock 52 Disable
bits : 20 - 20 (1 bit)
access : write-only

PID53 : Peripheral Clock 53 Disable
bits : 21 - 21 (1 bit)
access : write-only

PID54 : Peripheral Clock 54 Disable
bits : 22 - 22 (1 bit)
access : write-only

PID55 : Peripheral Clock 55 Disable
bits : 23 - 23 (1 bit)
access : write-only

PID56 : Peripheral Clock 56 Disable
bits : 24 - 24 (1 bit)
access : write-only

PID57 : Peripheral Clock 57 Disable
bits : 25 - 25 (1 bit)
access : write-only

PID58 : Peripheral Clock 58 Disable
bits : 26 - 26 (1 bit)
access : write-only

PID59 : Peripheral Clock 59 Disable
bits : 27 - 27 (1 bit)
access : write-only

PID60 : Peripheral Clock 60 Disable
bits : 28 - 28 (1 bit)
access : write-only

PID61 : Peripheral Clock 61 Disable
bits : 29 - 29 (1 bit)
access : write-only

PID62 : Peripheral Clock 62 Disable
bits : 30 - 30 (1 bit)
access : write-only

PID63 : Peripheral Clock 63 Disable
bits : 31 - 31 (1 bit)
access : write-only


PCSR1

Peripheral Clock Status Register 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR1 PCSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID36 PID37 PID38 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID54 PID55 PID56 PID57 PID58 PID59 PID60 PID61 PID62 PID63

PID32 : Peripheral Clock 32 Status
bits : 0 - 0 (1 bit)
access : read-only

PID33 : Peripheral Clock 33 Status
bits : 1 - 1 (1 bit)
access : read-only

PID34 : Peripheral Clock 34 Status
bits : 2 - 2 (1 bit)
access : read-only

PID35 : Peripheral Clock 35 Status
bits : 3 - 3 (1 bit)
access : read-only

PID36 : Peripheral Clock 36 Status
bits : 4 - 4 (1 bit)
access : read-only

PID37 : Peripheral Clock 37 Status
bits : 5 - 5 (1 bit)
access : read-only

PID38 : Peripheral Clock 38 Status
bits : 6 - 6 (1 bit)
access : read-only

PID39 : Peripheral Clock 39 Status
bits : 7 - 7 (1 bit)
access : read-only

PID40 : Peripheral Clock 40 Status
bits : 8 - 8 (1 bit)
access : read-only

PID41 : Peripheral Clock 41 Status
bits : 9 - 9 (1 bit)
access : read-only

PID42 : Peripheral Clock 42 Status
bits : 10 - 10 (1 bit)
access : read-only

PID43 : Peripheral Clock 43 Status
bits : 11 - 11 (1 bit)
access : read-only

PID44 : Peripheral Clock 44 Status
bits : 12 - 12 (1 bit)
access : read-only

PID45 : Peripheral Clock 45 Status
bits : 13 - 13 (1 bit)
access : read-only

PID46 : Peripheral Clock 46 Status
bits : 14 - 14 (1 bit)
access : read-only

PID47 : Peripheral Clock 47 Status
bits : 15 - 15 (1 bit)
access : read-only

PID48 : Peripheral Clock 48 Status
bits : 16 - 16 (1 bit)
access : read-only

PID49 : Peripheral Clock 49 Status
bits : 17 - 17 (1 bit)
access : read-only

PID50 : Peripheral Clock 50 Status
bits : 18 - 18 (1 bit)
access : read-only

PID51 : Peripheral Clock 51 Status
bits : 19 - 19 (1 bit)
access : read-only

PID52 : Peripheral Clock 52 Status
bits : 20 - 20 (1 bit)
access : read-only

PID53 : Peripheral Clock 53 Status
bits : 21 - 21 (1 bit)
access : read-only

PID54 : Peripheral Clock 54 Status
bits : 22 - 22 (1 bit)
access : read-only

PID55 : Peripheral Clock 55 Status
bits : 23 - 23 (1 bit)
access : read-only

PID56 : Peripheral Clock 56 Status
bits : 24 - 24 (1 bit)
access : read-only

PID57 : Peripheral Clock 57 Status
bits : 25 - 25 (1 bit)
access : read-only

PID58 : Peripheral Clock 58 Status
bits : 26 - 26 (1 bit)
access : read-only

PID59 : Peripheral Clock 59 Status
bits : 27 - 27 (1 bit)
access : read-only

PID60 : Peripheral Clock 60 Status
bits : 28 - 28 (1 bit)
access : read-only

PID61 : Peripheral Clock 61 Status
bits : 29 - 29 (1 bit)
access : read-only

PID62 : Peripheral Clock 62 Status
bits : 30 - 30 (1 bit)
access : read-only

PID63 : Peripheral Clock 63 Status
bits : 31 - 31 (1 bit)
access : read-only


PCK[2]

Programmable Clock 0 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[2] PCK[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


PCR

Peripheral Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID CMD EN

PID : Peripheral ID
bits : 0 - 6 (7 bit)
access : read-write

CMD : Command
bits : 12 - 12 (1 bit)
access : read-write

EN : Enable
bits : 28 - 28 (1 bit)
access : read-write


PCDR0

Peripheral Clock Disable Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCDR0 PCDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID2 PID3 PID4 PID5 PID6 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID2 : Peripheral Clock 2 Disable
bits : 2 - 2 (1 bit)
access : write-only

PID3 : Peripheral Clock 3 Disable
bits : 3 - 3 (1 bit)
access : write-only

PID4 : Peripheral Clock 4 Disable
bits : 4 - 4 (1 bit)
access : write-only

PID5 : Peripheral Clock 5 Disable
bits : 5 - 5 (1 bit)
access : write-only

PID6 : Peripheral Clock 6 Disable
bits : 6 - 6 (1 bit)
access : write-only

PID7 : Peripheral Clock 7 Disable
bits : 7 - 7 (1 bit)
access : write-only

PID8 : Peripheral Clock 8 Disable
bits : 8 - 8 (1 bit)
access : write-only

PID9 : Peripheral Clock 9 Disable
bits : 9 - 9 (1 bit)
access : write-only

PID10 : Peripheral Clock 10 Disable
bits : 10 - 10 (1 bit)
access : write-only

PID11 : Peripheral Clock 11 Disable
bits : 11 - 11 (1 bit)
access : write-only

PID12 : Peripheral Clock 12 Disable
bits : 12 - 12 (1 bit)
access : write-only

PID13 : Peripheral Clock 13 Disable
bits : 13 - 13 (1 bit)
access : write-only

PID14 : Peripheral Clock 14 Disable
bits : 14 - 14 (1 bit)
access : write-only

PID15 : Peripheral Clock 15 Disable
bits : 15 - 15 (1 bit)
access : write-only

PID16 : Peripheral Clock 16 Disable
bits : 16 - 16 (1 bit)
access : write-only

PID17 : Peripheral Clock 17 Disable
bits : 17 - 17 (1 bit)
access : write-only

PID18 : Peripheral Clock 18 Disable
bits : 18 - 18 (1 bit)
access : write-only

PID19 : Peripheral Clock 19 Disable
bits : 19 - 19 (1 bit)
access : write-only

PID20 : Peripheral Clock 20 Disable
bits : 20 - 20 (1 bit)
access : write-only

PID21 : Peripheral Clock 21 Disable
bits : 21 - 21 (1 bit)
access : write-only

PID22 : Peripheral Clock 22 Disable
bits : 22 - 22 (1 bit)
access : write-only

PID23 : Peripheral Clock 23 Disable
bits : 23 - 23 (1 bit)
access : write-only

PID24 : Peripheral Clock 24 Disable
bits : 24 - 24 (1 bit)
access : write-only

PID25 : Peripheral Clock 25 Disable
bits : 25 - 25 (1 bit)
access : write-only

PID26 : Peripheral Clock 26 Disable
bits : 26 - 26 (1 bit)
access : write-only

PID27 : Peripheral Clock 27 Disable
bits : 27 - 27 (1 bit)
access : write-only

PID28 : Peripheral Clock 28 Disable
bits : 28 - 28 (1 bit)
access : write-only

PID29 : Peripheral Clock 29 Disable
bits : 29 - 29 (1 bit)
access : write-only

PID30 : Peripheral Clock 30 Disable
bits : 30 - 30 (1 bit)
access : write-only

PID31 : Peripheral Clock 31 Disable
bits : 31 - 31 (1 bit)
access : write-only


PCSR0

Peripheral Clock Status Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR0 PCSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID2 PID3 PID4 PID5 PID6 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID2 : Peripheral Clock 2 Status
bits : 2 - 2 (1 bit)
access : read-only

PID3 : Peripheral Clock 3 Status
bits : 3 - 3 (1 bit)
access : read-only

PID4 : Peripheral Clock 4 Status
bits : 4 - 4 (1 bit)
access : read-only

PID5 : Peripheral Clock 5 Status
bits : 5 - 5 (1 bit)
access : read-only

PID6 : Peripheral Clock 6 Status
bits : 6 - 6 (1 bit)
access : read-only

PID7 : Peripheral Clock 7 Status
bits : 7 - 7 (1 bit)
access : read-only

PID8 : Peripheral Clock 8 Status
bits : 8 - 8 (1 bit)
access : read-only

PID9 : Peripheral Clock 9 Status
bits : 9 - 9 (1 bit)
access : read-only

PID10 : Peripheral Clock 10 Status
bits : 10 - 10 (1 bit)
access : read-only

PID11 : Peripheral Clock 11 Status
bits : 11 - 11 (1 bit)
access : read-only

PID12 : Peripheral Clock 12 Status
bits : 12 - 12 (1 bit)
access : read-only

PID13 : Peripheral Clock 13 Status
bits : 13 - 13 (1 bit)
access : read-only

PID14 : Peripheral Clock 14 Status
bits : 14 - 14 (1 bit)
access : read-only

PID15 : Peripheral Clock 15 Status
bits : 15 - 15 (1 bit)
access : read-only

PID16 : Peripheral Clock 16 Status
bits : 16 - 16 (1 bit)
access : read-only

PID17 : Peripheral Clock 17 Status
bits : 17 - 17 (1 bit)
access : read-only

PID18 : Peripheral Clock 18 Status
bits : 18 - 18 (1 bit)
access : read-only

PID19 : Peripheral Clock 19 Status
bits : 19 - 19 (1 bit)
access : read-only

PID20 : Peripheral Clock 20 Status
bits : 20 - 20 (1 bit)
access : read-only

PID21 : Peripheral Clock 21 Status
bits : 21 - 21 (1 bit)
access : read-only

PID22 : Peripheral Clock 22 Status
bits : 22 - 22 (1 bit)
access : read-only

PID23 : Peripheral Clock 23 Status
bits : 23 - 23 (1 bit)
access : read-only

PID24 : Peripheral Clock 24 Status
bits : 24 - 24 (1 bit)
access : read-only

PID25 : Peripheral Clock 25 Status
bits : 25 - 25 (1 bit)
access : read-only

PID26 : Peripheral Clock 26 Status
bits : 26 - 26 (1 bit)
access : read-only

PID27 : Peripheral Clock 27 Status
bits : 27 - 27 (1 bit)
access : read-only

PID28 : Peripheral Clock 28 Status
bits : 28 - 28 (1 bit)
access : read-only

PID29 : Peripheral Clock 29 Status
bits : 29 - 29 (1 bit)
access : read-only

PID30 : Peripheral Clock 30 Status
bits : 30 - 30 (1 bit)
access : read-only

PID31 : Peripheral Clock 31 Status
bits : 31 - 31 (1 bit)
access : read-only


CKGR_UCKR

UTMI Clock Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_UCKR CKGR_UCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPLLEN UPLLCOUNT BIASEN BIASCOUNT

UPLLEN : UTMI PLL Enable
bits : 16 - 16 (1 bit)
access : read-write

UPLLCOUNT : UTMI PLL Startup Time
bits : 20 - 23 (4 bit)
access : read-write

BIASEN : UTMI BIAS Enable
bits : 24 - 24 (1 bit)
access : read-write

BIASCOUNT : UTMI BIAS Startup Time
bits : 28 - 31 (4 bit)
access : read-write


CKGR_MOR

Main Oscillator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_MOR CKGR_MOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTEN MOSCXTBY MOSCXTST KEY MOSCSEL CFDEN XT32KFME

MOSCXTEN : 12 MHz Crystal Oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

MOSCXTBY : 12 MHz Crystal Oscillator Bypass
bits : 1 - 1 (1 bit)
access : read-write

MOSCXTST : 12 MHz Crystal Oscillator Startup Time
bits : 8 - 15 (8 bit)
access : read-write

KEY : Password
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0x37 : PASSWD

Writing any other value in this field aborts the write operation.

End of enumeration elements list.

MOSCSEL : Main Clock Oscillator Selection
bits : 24 - 24 (1 bit)
access : read-write

CFDEN : Clock Failure Detector Enable
bits : 25 - 25 (1 bit)
access : read-write

XT32KFME : 32.768 kHz Crystal Oscillator Frequency Monitoring Enable
bits : 26 - 26 (1 bit)
access : read-write


CKGR_MCFR

Main Clock Frequency Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_MCFR CKGR_MCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINF MAINFRDY RCMEAS

MAINF : Main Clock Frequency
bits : 0 - 15 (16 bit)
access : read-write

MAINFRDY : Main Clock Frequency Measure Ready
bits : 16 - 16 (1 bit)
access : read-write

RCMEAS : RC Oscillator Frequency Measure (write-only)
bits : 20 - 20 (1 bit)
access : read-write


CKGR_PLLAR

PLLA Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_PLLAR CKGR_PLLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVA PLLACOUNT OUTA MULA ONE

DIVA : Divider A
bits : 0 - 0 (1 bit)
access : read-write

PLLACOUNT : PLLA Counter
bits : 8 - 13 (6 bit)
access : read-write

OUTA : PLLA Clock Frequency Range
bits : 14 - 17 (4 bit)
access : read-write

MULA : PLLA Multiplier
bits : 18 - 24 (7 bit)
access : read-write

ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)
access : read-write


MCKR

Master Clock Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCKR MCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES MDIV PLLADIV2 H32MXDIV

CSS : Master/Processor Clock Source Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

End of enumeration elements list.

PRES : Master/Processor Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.

MDIV : Master Clock Division
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : EQ_PCK

Master Clock is Prescaler Output Clock divided by 1.Warning: DDRCK is not available.

0x1 : PCK_DIV2

Master Clock is Prescaler Output Clock divided by 2. DDRCK is equal to MCK.

0x2 : PCK_DIV4

Master Clock is Prescaler Output Clock divided by 4. DDRCK is equal to MCK.

0x3 : PCK_DIV3

Master Clock is Prescaler Output Clock divided by 3. DDRCK is equal to MCK.

End of enumeration elements list.

PLLADIV2 : PLLA Divisor by 2
bits : 12 - 12 (1 bit)
access : read-write

H32MXDIV : AHB 32-bit Matrix Divisor
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : H32MXDIV1

The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 100 MHz.

1 : H32MXDIV2

The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2.

End of enumeration elements list.


USB

USB Clock Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB USB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBS USBDIV

USBS : USB OHCI Input Clock Selection
bits : 0 - 0 (1 bit)
access : read-write

USBDIV : Divider for USB OHCI Clock
bits : 8 - 11 (4 bit)
access : read-write


SMD

Soft Modem Clock Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMD SMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMDS SMDDIV

SMDS : SMD Input Clock Selection
bits : 0 - 0 (1 bit)
access : read-write

SMDDIV : Divider for SMD Clock
bits : 8 - 12 (5 bit)
access : read-write


SCDR

System Clock Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCDR SCDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCK DDRCK LCDCK SMDCK UHP UDP PCK0 PCK1 PCK2

PCK : Processor Clock Disable
bits : 0 - 0 (1 bit)
access : write-only

DDRCK : DDR Clock Disable
bits : 2 - 2 (1 bit)
access : write-only

LCDCK : MCK2x Clock Disable
bits : 3 - 3 (1 bit)
access : write-only

SMDCK : SMD Clock Disable
bits : 4 - 4 (1 bit)
access : write-only

UHP : USB Host OHCI Clock Disable
bits : 6 - 6 (1 bit)
access : write-only

UDP : USB Device Clock Enable
bits : 7 - 7 (1 bit)
access : write-only

PCK0 : Programmable Clock 0 Output Disable
bits : 8 - 8 (1 bit)
access : write-only

PCK1 : Programmable Clock 1 Output Disable
bits : 9 - 9 (1 bit)
access : write-only

PCK2 : Programmable Clock 2 Output Disable
bits : 10 - 10 (1 bit)
access : write-only


PCK0

Programmable Clock 0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PCK0 PCK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


PCK1

Programmable Clock 0 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PCK1 PCK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


PCK2

Programmable Clock 0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

PCK2 PCK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


IER

Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU PCKRDY0 PCKRDY1 PCKRDY2 MOSCSELS CFDEV XT32KERR

MOSCXTS : 12 MHz Crystal Oscillator Status Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

LOCKA : PLLA Lock Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

MCKRDY : Master Clock Ready Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

LOCKU : UTMI PLL Lock Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PCKRDY0 : Programmable Clock Ready 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

PCKRDY1 : Programmable Clock Ready 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

PCKRDY2 : Programmable Clock Ready 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

MOSCSELS : Main Clock Source Oscillator Selection Status Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

CFDEV : Clock Failure Detector Event Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU PCKRDY0 PCKRDY1 PCKRDY2 MOSCSELS CFDEV XT32KERR

MOSCXTS : 12 MHz Crystal Oscillator Status Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

LOCKA : PLLA Lock Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

MCKRDY : Master Clock Ready Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

LOCKU : UTMI PLL Lock Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PCKRDY0 : Programmable Clock Ready 0 Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

PCKRDY1 : Programmable Clock Ready 1 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

PCKRDY2 : Programmable Clock Ready 2 Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

MOSCSELS : Main Oscillator Clock Source Selection Status Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

CFDEV : Clock Failure Detector Event Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only


SR

Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU OSCSELS PCKRDY0 PCKRDY1 PCKRDY2 MOSCSELS CFDEV CFDS FOS XT32KERR

MOSCXTS : 12 MHz Crystal Oscillator Status
bits : 0 - 0 (1 bit)
access : read-only

LOCKA : PLLA Lock Status
bits : 1 - 1 (1 bit)
access : read-only

MCKRDY : Master Clock Status
bits : 3 - 3 (1 bit)
access : read-only

LOCKU : UPLL Clock Status
bits : 6 - 6 (1 bit)
access : read-only

OSCSELS : Slow Clock Oscillator Selection
bits : 7 - 7 (1 bit)
access : read-only

PCKRDY0 : Programmable Clock Ready Status
bits : 8 - 8 (1 bit)
access : read-only

PCKRDY1 : Programmable Clock Ready Status
bits : 9 - 9 (1 bit)
access : read-only

PCKRDY2 : Programmable Clock Ready Status
bits : 10 - 10 (1 bit)
access : read-only

MOSCSELS : Main Oscillator Selection Status
bits : 16 - 16 (1 bit)
access : read-only

CFDEV : Clock Failure Detector Event
bits : 18 - 18 (1 bit)
access : read-only

CFDS : Clock Failure Detector Status
bits : 19 - 19 (1 bit)
access : read-only

FOS : Clock Failure Detector Fault Output Status
bits : 20 - 20 (1 bit)
access : read-only

XT32KERR : 32.768 kHz Crystal Oscillator Error
bits : 21 - 21 (1 bit)
access : read-only


IMR

Interrupt Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY PCKRDY0 PCKRDY1 PCKRDY2 MOSCSELS CFDEV XT32KERR

MOSCXTS : 12 MHz Crystal Oscillator Status Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

LOCKA : PLLA Lock Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

MCKRDY : Master Clock Ready Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

PCKRDY0 : Programmable Clock Ready 0 Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

PCKRDY1 : Programmable Clock Ready 1 Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

PCKRDY2 : Programmable Clock Ready 2 Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

MOSCSELS : Main Oscillator Clock Source Selection Status Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

CFDEV : Clock Failure Detector Event Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only


FOCR

Fault Output Clear Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FOCR FOCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FOCLR

FOCLR : Fault Output Clear
bits : 0 - 0 (1 bit)
access : write-only


SCSR

System Clock Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCK DDRCK LCDCK SMDCK UHP UDP PCK0 PCK1 PCK2

PCK : Processor Clock Status
bits : 0 - 0 (1 bit)
access : read-only

DDRCK : DDR Clock Status
bits : 2 - 2 (1 bit)
access : read-only

LCDCK : MCK2x Clock Status
bits : 3 - 3 (1 bit)
access : read-only

SMDCK : SMD Clock Status
bits : 4 - 4 (1 bit)
access : read-only

UHP : USB Host Port Clock Status
bits : 6 - 6 (1 bit)
access : read-only

UDP : USB Device Port Clock Status
bits : 7 - 7 (1 bit)
access : read-only

PCK0 : Programmable Clock 0 Output Status
bits : 8 - 8 (1 bit)
access : read-only

PCK1 : Programmable Clock 1 Output Status
bits : 9 - 9 (1 bit)
access : read-only

PCK2 : Programmable Clock 2 Output Status
bits : 10 - 10 (1 bit)
access : read-only


PCK[0]

Programmable Clock 0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[0] PCK[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


PLLICPR

PLL Charge Pump Current Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLICPR PLLICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICP_PLLA IPLL_PLLA ICP_PLLU IVCO_PLLU

ICP_PLLA : Must Be Written to Zero
bits : 0 - 1 (2 bit)
access : read-write

IPLL_PLLA : Engineering Configuration PLLA
bits : 8 - 10 (3 bit)
access : read-write

ICP_PLLU : Charge Pump Current PLL UTMI
bits : 16 - 17 (2 bit)
access : read-write

IVCO_PLLU : Voltage Control Output Current PLL UTMI
bits : 24 - 25 (2 bit)
access : read-write


PCK[1]

Programmable Clock 0 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[1] PCK[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Master Clock Source Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : SLOW_CLK

Slow clock is selected

0x1 : MAIN_CLK

Main clock is selected

0x2 : PLLA_CLK

PLLACK is selected

0x3 : UPLL_CLK

UPLL Clock is selected

0x4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : CLOCK

Selected clock

0x1 : CLOCK_DIV2

Selected clock divided by 2

0x2 : CLOCK_DIV4

Selected clock divided by 4

0x3 : CLOCK_DIV8

Selected clock divided by 8

0x4 : CLOCK_DIV16

Selected clock divided by 16

0x5 : CLOCK_DIV32

Selected clock divided by 32

0x6 : CLOCK_DIV64

Selected clock divided by 64

End of enumeration elements list.


WPMR

Write ProtectIon Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x504D43 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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