\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CHER

CHDR

CDR[2]

CHSR

CDR[3]

LCDR

CDR[4]

IER

IDR

IMR

ISR

OVER

MR

EMR

CWR

CDR0

CDR1

CDR2

CDR3

CDR4

SEQR1

ACR

CDR[0]

TSMR

XPOSR

YPOSR

PRESSR

TRGR

WPMR

WPSR

CDR[1]


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST START TSCALIB

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

START : Start Conversion
bits : 1 - 1 (1 bit)
access : write-only

TSCALIB : Touchscreen Calibration
bits : 2 - 2 (1 bit)
access : write-only


CHER

Channel Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHER CHER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4

CH0 : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only

CH1 : Channel 1 Enable
bits : 1 - 1 (1 bit)
access : write-only

CH2 : Channel 2 Enable
bits : 2 - 2 (1 bit)
access : write-only

CH3 : Channel 3 Enable
bits : 3 - 3 (1 bit)
access : write-only

CH4 : Channel 4 Enable
bits : 4 - 4 (1 bit)
access : write-only


CHDR

Channel Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHDR CHDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4

CH0 : Channel 0 Disable
bits : 0 - 0 (1 bit)
access : write-only

CH1 : Channel 1 Disable
bits : 1 - 1 (1 bit)
access : write-only

CH2 : Channel 2 Disable
bits : 2 - 2 (1 bit)
access : write-only

CH3 : Channel 3 Disable
bits : 3 - 3 (1 bit)
access : write-only

CH4 : Channel 4 Disable
bits : 4 - 4 (1 bit)
access : write-only


CDR[2]

Channel Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[2] CDR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CHSR

Channel Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSR CHSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4

CH0 : Channel 0 Status
bits : 0 - 0 (1 bit)
access : read-only

CH1 : Channel 1 Status
bits : 1 - 1 (1 bit)
access : read-only

CH2 : Channel 2 Status
bits : 2 - 2 (1 bit)
access : read-only

CH3 : Channel 3 Status
bits : 3 - 3 (1 bit)
access : read-only

CH4 : Channel 4 Status
bits : 4 - 4 (1 bit)
access : read-only


CDR[3]

Channel Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[3] CDR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


LCDR

Last Converted Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LCDR LCDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDATA CHNB

LDATA : Last Data Converted
bits : 0 - 11 (12 bit)
access : read-only

CHNB : Channel Number
bits : 12 - 15 (4 bit)
access : read-only


CDR[4]

Channel Data Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[4] CDR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 XRDY YRDY PRDY DRDY GOVRE COMPE PEN NOPEN

EOC0 : End of Conversion Interrupt Enable 0
bits : 0 - 0 (1 bit)
access : write-only

EOC1 : End of Conversion Interrupt Enable 1
bits : 1 - 1 (1 bit)
access : write-only

EOC2 : End of Conversion Interrupt Enable 2
bits : 2 - 2 (1 bit)
access : write-only

EOC3 : End of Conversion Interrupt Enable 3
bits : 3 - 3 (1 bit)
access : write-only

EOC4 : End of Conversion Interrupt Enable 4
bits : 4 - 4 (1 bit)
access : write-only

XRDY : Touchscreen Measure XPOS Ready Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

YRDY : Touchscreen Measure YPOS Ready Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

PRDY : Touchscreen Measure Pressure Ready Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only

GOVRE : General Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

COMPE : Comparison Event Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

PEN : Pen Contact Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only

NOPEN : No Pen Contact Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 XRDY YRDY PRDY DRDY GOVRE COMPE PEN NOPEN

EOC0 : End of Conversion Interrupt Disable 0
bits : 0 - 0 (1 bit)
access : write-only

EOC1 : End of Conversion Interrupt Disable 1
bits : 1 - 1 (1 bit)
access : write-only

EOC2 : End of Conversion Interrupt Disable 2
bits : 2 - 2 (1 bit)
access : write-only

EOC3 : End of Conversion Interrupt Disable 3
bits : 3 - 3 (1 bit)
access : write-only

EOC4 : End of Conversion Interrupt Disable 4
bits : 4 - 4 (1 bit)
access : write-only

XRDY : Touchscreen Measure XPOS Ready Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

YRDY : Touchscreen Measure YPOS Ready Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

PRDY : Touchscreen Measure Pressure Ready Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only

GOVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

COMPE : Comparison Event Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

PEN : Pen Contact Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only

NOPEN : No Pen Contact Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 XRDY YRDY PRDY DRDY GOVRE COMPE PEN NOPEN

EOC0 : End of Conversion Interrupt Mask 0
bits : 0 - 0 (1 bit)
access : read-only

EOC1 : End of Conversion Interrupt Mask 1
bits : 1 - 1 (1 bit)
access : read-only

EOC2 : End of Conversion Interrupt Mask 2
bits : 2 - 2 (1 bit)
access : read-only

EOC3 : End of Conversion Interrupt Mask 3
bits : 3 - 3 (1 bit)
access : read-only

EOC4 : End of Conversion Interrupt Mask 4
bits : 4 - 4 (1 bit)
access : read-only

XRDY : Touchscreen Measure XPOS Ready Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

YRDY : Touchscreen Measure YPOS Ready Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

PRDY : Touchscreen Measure Pressure Ready Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only

GOVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

COMPE : Comparison Event Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

PEN : Pen Contact Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only

NOPEN : No Pen Contact Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only


ISR

Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC0 EOC1 EOC2 EOC3 EOC4 XRDY YRDY PRDY DRDY GOVRE COMPE PEN NOPEN PENS

EOC0 : End of Conversion 0 (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only

EOC1 : End of Conversion 1 (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only

EOC2 : End of Conversion 2 (automatically set / cleared)
bits : 2 - 2 (1 bit)
access : read-only

EOC3 : End of Conversion 3 (automatically set / cleared)
bits : 3 - 3 (1 bit)
access : read-only

EOC4 : End of Conversion 4 (automatically set / cleared)
bits : 4 - 4 (1 bit)
access : read-only

XRDY : Touchscreen XPOS Measure Ready (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only

YRDY : Touchscreen YPOS Measure Ready (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only

PRDY : Touchscreen Pressure Measure Ready (cleared on read)
bits : 22 - 22 (1 bit)
access : read-only

DRDY : Data Ready (automatically set / cleared)
bits : 24 - 24 (1 bit)
access : read-only

GOVRE : General Overrun Error (cleared on read)
bits : 25 - 25 (1 bit)
access : read-only

COMPE : Comparison Event (cleared on read)
bits : 26 - 26 (1 bit)
access : read-only

PEN : Pen contact (cleared on read)
bits : 29 - 29 (1 bit)
access : read-only

NOPEN : No Pen Contact (cleared on read)
bits : 30 - 30 (1 bit)
access : read-only

PENS : Pen Detect Status
bits : 31 - 31 (1 bit)
access : read-only


OVER

Overrun Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OVER OVER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVRE0 OVRE1 OVRE2 OVRE3 OVRE4

OVRE0 : Overrun Error 0
bits : 0 - 0 (1 bit)
access : read-only

OVRE1 : Overrun Error 1
bits : 1 - 1 (1 bit)
access : read-only

OVRE2 : Overrun Error 2
bits : 2 - 2 (1 bit)
access : read-only

OVRE3 : Overrun Error 3
bits : 3 - 3 (1 bit)
access : read-only

OVRE4 : Overrun Error 4
bits : 4 - 4 (1 bit)
access : read-only


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGSEL LOWRES SLEEP PRESCAL STARTUP TRACKTIM USEQ

TRGSEL : Trigger Selection
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0x0 : ADC_TRIG0

ADTRG

0x1 : ADC_TRIG1

TIOA0

0x2 : ADC_TRIG2

TIOA1

0x3 : ADC_TRIG3

TIOA2

0x4 : ADC_TRIG4

PWM event line 0

0x5 : ADC_TRIG5

PWM_even line 1

0x7 : ADC_TRIG7

-

End of enumeration elements list.

LOWRES : Resolution
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : BITS_10

10-bit resolution. For higher resolution by averaging, refer to Section 8.18 "ADC Extended Mode Register".

1 : BITS_8

8-bit resolution

End of enumeration elements list.

SLEEP : Sleep Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions.

1 : SLEEP

Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions.

End of enumeration elements list.

PRESCAL : Prescaler Rate Selection
bits : 8 - 15 (8 bit)
access : read-write

STARTUP : Startup Time
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0x0 : SUT0

0 periods of ADCCLK

0x1 : SUT8

8 periods of ADCCLK

0x2 : SUT16

16 periods of ADCCLK

0x3 : SUT24

24 periods of ADCCLK

0x4 : SUT64

64 periods of ADCCLK

0x5 : SUT80

80 periods of ADCCLK

0x6 : SUT96

96 periods of ADCCLK

0x7 : SUT112

112 periods of ADCCLK

0x8 : SUT512

512 periods of ADCCLK

0x9 : SUT576

576 periods of ADCCLK

0xA : SUT640

640 periods of ADCCLK

0xB : SUT704

704 periods of ADCCLK

0xC : SUT768

768 periods of ADCCLK

0xD : SUT832

832 periods of ADCCLK

0xE : SUT896

896 periods of ADCCLK

0xF : SUT960

960 periods of ADCCLK

End of enumeration elements list.

TRACKTIM : Tracking Time
bits : 24 - 27 (4 bit)
access : read-write

USEQ : Use Sequence Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NUM_ORDER

Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.

1 : REG_ORDER

User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times.

End of enumeration elements list.


EMR

Extended Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMR EMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPMODE CMPSEL CMPALL CMPFILTER OSR ASTE TAG

CMPMODE : Comparison Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : LOW

When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR.

0x1 : HIGH

When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR.

0x2 : IN

When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR.

0x3 : OUT

When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR.

End of enumeration elements list.

CMPSEL : Comparison Selected Channel
bits : 4 - 7 (4 bit)
access : read-write

CMPALL : Compare All Channels
bits : 9 - 9 (1 bit)
access : read-write

CMPFILTER : Compare Event Filtering
bits : 12 - 13 (2 bit)
access : read-write

OSR : Oversampling Rate
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : NO_AVERAGE

No averaging. ADC sample rate is maximum.

0x1 : OSR4

1-bit enhanced resolution by averaging. ADC sample rate divided by 4.

0x2 : OSR16

2-bit enhanced resolution by averaging. ADC sample rate divided by 16.

End of enumeration elements list.

ASTE : Averaging on Single Trigger Event
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : MULTI_TRIG_AVERAGE

The average requests several trigger events.

1 : SINGLE_TRIG_AVERAGE

The average requests only one trigger event.

End of enumeration elements list.

TAG : Tag of ADC_LCDR
bits : 24 - 24 (1 bit)
access : read-write


CWR

Compare Window Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWR CWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOWTHRES HIGHTHRES

LOWTHRES : Low Threshold
bits : 0 - 11 (12 bit)
access : read-write

HIGHTHRES : High Threshold
bits : 16 - 27 (12 bit)
access : read-write


CDR0

Channel Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR0 CDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR1

Channel Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR1 CDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR2

Channel Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR2 CDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR3

Channel Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR3 CDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


CDR4

Channel Data Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CDR4 CDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


SEQR1

Channel Sequence Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQR1 SEQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USCH1 USCH2 USCH3 USCH4

USCH1 : User Sequence Number 1
bits : 0 - 3 (4 bit)
access : read-write

USCH2 : User Sequence Number 2
bits : 4 - 7 (4 bit)
access : read-write

USCH3 : User Sequence Number 3
bits : 8 - 11 (4 bit)
access : read-write

USCH4 : User Sequence Number 4
bits : 12 - 15 (4 bit)
access : read-write


ACR

Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDETSENS

PENDETSENS : Pen Detection Sensitivity
bits : 0 - 1 (2 bit)
access : read-write


CDR[0]

Channel Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[0] CDR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only


TSMR

Touchscreen Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSMR TSMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSMODE TSAV TSFREQ TSSCTIM NOTSDMA PENDET PENDBC

TSMODE : Touchscreen Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No Touchscreen

0x1 : 4_WIRE_NO_PM

4-wire Touchscreen without pressure measurement

0x2 : 4_WIRE

4-wire Touchscreen with pressure measurement

0x3 : 5_WIRE

5-wire Touchscreen

End of enumeration elements list.

TSAV : Touchscreen Average
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : NO_FILTER

No Filtering. Only one ADC conversion per measure

0x1 : AVG2CONV

Averages 2 ADC conversions

0x2 : AVG4CONV

Averages 4 ADC conversions

0x3 : AVG8CONV

Averages 8 ADC conversions

End of enumeration elements list.

TSFREQ : Touchscreen Frequency
bits : 8 - 11 (4 bit)
access : read-write

TSSCTIM : Touchscreen Switches Closure Time
bits : 16 - 19 (4 bit)
access : read-write

NOTSDMA : No TouchScreen DMA
bits : 22 - 22 (1 bit)
access : read-write

PENDET : Pen Contact Detection Enable
bits : 24 - 24 (1 bit)
access : read-write

PENDBC : Pen Detect Debouncing Period
bits : 28 - 31 (4 bit)
access : read-write


XPOSR

Touchscreen X Position Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

XPOSR XPOSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XPOS XSCALE

XPOS : X Position
bits : 0 - 11 (12 bit)
access : read-only

XSCALE : Scale of XPOS
bits : 16 - 27 (12 bit)
access : read-only


YPOSR

Touchscreen Y Position Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

YPOSR YPOSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 YPOS YSCALE

YPOS : Y Position
bits : 0 - 11 (12 bit)
access : read-only

YSCALE : Scale of YPOS
bits : 16 - 27 (12 bit)
access : read-only


PRESSR

Touchscreen Pressure Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESSR PRESSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z1 Z2

Z1 : Data of Z1 Measurement
bits : 0 - 11 (12 bit)
access : read-only

Z2 : Data of Z2 Measurement
bits : 16 - 27 (12 bit)
access : read-only


TRGR

Trigger Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGR TRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGMOD TRGPER

TRGMOD : Trigger Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x0 : NO_TRIGGER

No trigger, only software trigger can start conversions

0x1 : EXT_TRIG_RISE

External trigger rising edge

0x2 : EXT_TRIG_FALL

External trigger falling edge

0x3 : EXT_TRIG_ANY

External trigger any edge

0x4 : PEN_TRIG

Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode)

0x5 : PERIOD_TRIG

ADC internal periodic trigger (see field TRGPER)

0x6 : CONTINUOUS

Continuous Mode

End of enumeration elements list.

TRGPER : Trigger Period
bits : 16 - 31 (16 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x414443 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only


CDR[1]

Channel Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDR[1] CDR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Converted Data
bits : 0 - 11 (12 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.