\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Network Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBL : Loop Back Local
bits : 1 - 1 (1 bit)
access : read-write
RXEN : Receive Enable
bits : 2 - 2 (1 bit)
access : read-write
TXEN : Transmit Enable
bits : 3 - 3 (1 bit)
access : read-write
MPE : Management Port Enable
bits : 4 - 4 (1 bit)
access : read-write
CLRSTAT : Clear Statistics Registers
bits : 5 - 5 (1 bit)
access : read-write
INCSTAT : Increment Statistics Registers
bits : 6 - 6 (1 bit)
access : read-write
WESTAT : Write Enable for Statistics Registers
bits : 7 - 7 (1 bit)
access : read-write
BP : Back pressure
bits : 8 - 8 (1 bit)
access : read-write
TSTART : Start Transmission
bits : 9 - 9 (1 bit)
access : read-write
THALT : Transmit Halt
bits : 10 - 10 (1 bit)
access : read-write
TXPF : Transmit Pause Frame
bits : 11 - 11 (1 bit)
access : read-write
TXZQPF : Transmit Zero Quantum Pause Frame
bits : 12 - 12 (1 bit)
access : read-write
SRTSM : Store Receive Time Stamp to Memory
bits : 15 - 15 (1 bit)
access : read-write
ENPBPR : Enable PFC Priority-based Pause Reception
bits : 16 - 16 (1 bit)
access : read-write
TXPBPF : Transmit PFC Priority-based Pause Frame
bits : 17 - 17 (1 bit)
access : read-write
FNP : Flush Next Packet
bits : 18 - 18 (1 bit)
access : read-write
TXLPIEN : Enable LPI Transmission
bits : 19 - 19 (1 bit)
access : read-write
DMA Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBLDO : Fixed Burst Length for DMA Data Operations:
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x1 : SINGLE
00001: Always use SINGLE AHB bursts
0x4 : INCR4
001xx: Attempt to use INCR4 AHB bursts (Default)
0x8 : INCR8
01xxx: Attempt to use INCR8 AHB bursts
0x10 : INCR16
1xxxx: Attempt to use INCR16 AHB bursts
End of enumeration elements list.
ESMA : Endian Swap Mode Enable for Management Descriptor Accesses
bits : 6 - 6 (1 bit)
access : read-write
ESPA : Endian Swap Mode Enable for Packet Data Accesses
bits : 7 - 7 (1 bit)
access : read-write
DRBS : DMA Receive Buffer Size
bits : 16 - 23 (8 bit)
access : read-write
Octets Transmitted Low Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXO : Transmitted Octets
bits : 0 - 31 (32 bit)
access : read-only
Octets Transmitted High Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXO : Transmitted Octets
bits : 0 - 15 (16 bit)
access : read-only
Frames Transmitted Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTX : Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
Broadcast Frames Transmitted Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BFTX : Broadcast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
Multicast Frames Transmitted Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFTX : Multicast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
Pause Frames Transmitted Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PFTX : Pause Frames Transmitted Register
bits : 0 - 15 (16 bit)
access : read-only
64 Byte Frames Transmitted Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 64 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
65 to 127 Byte Frames Transmitted Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 65 to 127 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
128 to 255 Byte Frames Transmitted Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 128 to 255 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
256 to 511 Byte Frames Transmitted Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 256 to 511 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
512 to 1023 Byte Frames Transmitted Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 512 to 1023 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
1024 to 1518 Byte Frames Transmitted Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 1024 to 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
Greater Than 1518 Byte Frames Transmitted Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : Greater than 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only
Transmit Underruns Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXUNR : Transmit Underruns
bits : 0 - 9 (10 bit)
access : read-only
Single Collision Frames Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCOL : Single Collision
bits : 0 - 17 (18 bit)
access : read-only
Multiple Collision Frames Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCOL : Multiple Collision
bits : 0 - 17 (18 bit)
access : read-only
Transmit Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBR : Used Bit Read
bits : 0 - 0 (1 bit)
access : read-write
COL : Collision Occurred
bits : 1 - 1 (1 bit)
access : read-write
RLE : Retry Limit Exceeded
bits : 2 - 2 (1 bit)
access : read-write
TXGO : Transmit Go
bits : 3 - 3 (1 bit)
access : read-write
TFC : Transmit Frame Corruption Due to AHB Error
bits : 4 - 4 (1 bit)
access : read-write
TXCOMP : Transmit Complete
bits : 5 - 5 (1 bit)
access : read-write
UND : Transmit Underrun
bits : 6 - 6 (1 bit)
access : read-write
HRESP : HRESP Not OK
bits : 8 - 8 (1 bit)
access : read-write
Excessive Collisions Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XCOL : Excessive Collisions
bits : 0 - 9 (10 bit)
access : read-only
Late Collisions Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LCOL : Late Collisions
bits : 0 - 9 (10 bit)
access : read-only
Deferred Transmission Frames Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEFT : Deferred Transmission
bits : 0 - 17 (18 bit)
access : read-only
Carrier Sense Errors Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSR : Carrier Sense Error
bits : 0 - 9 (10 bit)
access : read-only
Octets Received Low Received Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXO : Received Octets
bits : 0 - 31 (32 bit)
access : read-only
Octets Received High Received Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXO : Received Octets
bits : 0 - 15 (16 bit)
access : read-only
Frames Received Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRX : Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
Broadcast Frames Received Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BFRX : Broadcast Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
Multicast Frames Received Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFRX : Multicast Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
Pause Frames Received Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PFRX : Pause Frames Received Register
bits : 0 - 15 (16 bit)
access : read-only
64 Byte Frames Received Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 64 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
65 to 127 Byte Frames Received Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 65 to 127 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
128 to 255 Byte Frames Received Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 128 to 255 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
256 to 511 Byte Frames Received Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 256 to 511 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
512 to 1023 Byte Frames Received Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 512 to 1023 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
1024 to 1518 Byte Frames Received Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 1024 to 1518 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
Receive Buffer Queue Base Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
1519 to Maximum Byte Frames Received Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 1519 to Maximum Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only
Undersize Frames Received Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UFRX : Undersize Frames Received
bits : 0 - 9 (10 bit)
access : read-only
Oversize Frames Received Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OFRX : Oversized Frames Received
bits : 0 - 9 (10 bit)
access : read-only
Jabbers Received Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JRX : Jabbers Received
bits : 0 - 9 (10 bit)
access : read-only
Frame Check Sequence Errors Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCKR : Frame Check Sequence Errors
bits : 0 - 9 (10 bit)
access : read-only
Length Field Frame Errors Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFER : Length Field Frame Errors
bits : 0 - 9 (10 bit)
access : read-only
Receive Symbol Errors Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXSE : Receive Symbol Errors
bits : 0 - 9 (10 bit)
access : read-only
Alignment Errors Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AER : Alignment Errors
bits : 0 - 9 (10 bit)
access : read-only
Receive Resource Errors Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRER : Receive Resource Errors
bits : 0 - 17 (18 bit)
access : read-only
Receive Overrun Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXOVR : Receive Overruns
bits : 0 - 9 (10 bit)
access : read-only
IP Header Checksum Errors Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HCKER : IP Header Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only
TCP Checksum Errors Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TCKER : TCP Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only
UDP Checksum Errors Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UCKER : UDP Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only
1588 Timer Increment Sub-nanoseconds Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSBTIR : Lower Significant Bits of Timer Increment Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Buffer Queue Base Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
1588 Timer Seconds High Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCS : Timer Count in Seconds
bits : 0 - 15 (16 bit)
access : read-write
1588 Timer Seconds Low Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCS : Timer Count in Seconds
bits : 0 - 31 (32 bit)
access : read-write
1588 Timer Nanoseconds Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TNS : Timer Count in Nanoseconds
bits : 0 - 29 (30 bit)
access : read-write
1588 Timer Adjust Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ITDT : Increment/Decrement
bits : 0 - 29 (30 bit)
access : write-only
ADJ : Adjust 1588 Timer
bits : 31 - 31 (1 bit)
access : write-only
1588 Timer Increment Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNS : Count Nanoseconds
bits : 0 - 7 (8 bit)
access : read-write
ACNS : Alternative Count Nanoseconds
bits : 8 - 15 (8 bit)
access : read-write
NIT : Number of Increments
bits : 16 - 23 (8 bit)
access : read-write
PTP Event Frame Transmitted Seconds Low Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only
PTP Event Frame Transmitted Nanoseconds Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only
PTP Event Frame Received Seconds Low Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only
PTP Event Frame Received Nanoseconds Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only
PTP Peer Event Frame Transmitted Seconds Low Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only
PTP Peer Event Frame Transmitted Nanoseconds Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only
PTP Peer Event Frame Received Seconds Low Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only
PTP Peer Event Frame Received Nanoseconds Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only
Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNA : Buffer Not Available
bits : 0 - 0 (1 bit)
access : read-write
REC : Frame Received
bits : 1 - 1 (1 bit)
access : read-write
RXOVR : Receive Overrun
bits : 2 - 2 (1 bit)
access : read-write
HNO : HRESP Not OK
bits : 3 - 3 (1 bit)
access : read-write
Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : read-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : read-only
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : read-only
RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-only
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : read-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-only
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : read-only
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : read-only
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : read-only
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : read-only
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : read-only
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : read-only
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : read-only
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : read-only
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : read-only
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : read-only
RXLPISBC : Receive LPI indication Status Bit Change
bits : 27 - 27 (1 bit)
access : read-only
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : read-only
TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : read-only
Received LPI Transitions
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count of RX LPI transitions (cleared on read)
bits : 0 - 15 (16 bit)
access : read-only
Received LPI Time
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPITIME : Time in LPI (cleared on read)
bits : 0 - 23 (24 bit)
access : read-only
Transmit LPI Transitions
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Count of LPI transitions (cleared on read)
bits : 0 - 15 (16 bit)
access : read-only
Transmit LPI Time
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPITIME : Time in LPI (cleared on read)
bits : 0 - 23 (24 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : write-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : write-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : write-only
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : write-only
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : write-only
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : write-only
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : write-only
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : write-only
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : write-only
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : write-only
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : write-only
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : write-only
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : write-only
RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : write-only
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : write-only
TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : write-only
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : write-only
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : write-only
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : write-only
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : write-only
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : write-only
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : write-only
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : write-only
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : write-only
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : write-only
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : write-only
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : write-only
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : write-only
RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : write-only
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : write-only
TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : read-write
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : read-write
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : read-write
RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-write
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-write
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-write
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : read-write
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-write
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : read-write
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : read-write
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : read-write
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : read-write
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : read-write
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : read-write
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : read-write
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : read-write
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : read-write
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : read-write
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : read-write
RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : read-write
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : read-write
TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : read-write
PHY Maintenance Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : PHY Data
bits : 0 - 15 (16 bit)
access : read-write
WTN : Write Ten
bits : 16 - 17 (2 bit)
access : read-write
REGA : Register Address
bits : 18 - 22 (5 bit)
access : read-write
PHYA : PHY Address
bits : 23 - 27 (5 bit)
access : read-write
OP : Operation
bits : 28 - 29 (2 bit)
access : read-write
CLTTO : Clause 22 Operation
bits : 30 - 30 (1 bit)
access : read-write
WZO : Write ZERO
bits : 31 - 31 (1 bit)
access : read-write
Received Pause Quantum Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPQ : Received Pause Quantum
bits : 0 - 15 (16 bit)
access : read-only
Transmit Pause Quantum Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPQ : Transmit Pause Quantum
bits : 0 - 15 (16 bit)
access : read-write
Network Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPD : Speed
bits : 0 - 0 (1 bit)
access : read-write
FD : Full Duplex
bits : 1 - 1 (1 bit)
access : read-write
DNVLAN : Discard Non-VLAN FRAMES
bits : 2 - 2 (1 bit)
access : read-write
JFRAME : Jumbo Frame Size
bits : 3 - 3 (1 bit)
access : read-write
CAF : Copy All Frames
bits : 4 - 4 (1 bit)
access : read-write
NBC : No Broadcast
bits : 5 - 5 (1 bit)
access : read-write
MTIHEN : Multicast Hash Enable
bits : 6 - 6 (1 bit)
access : read-write
UNIHEN : Unicast Hash Enable
bits : 7 - 7 (1 bit)
access : read-write
MAXFS : 1536 Maximum Frame Size
bits : 8 - 8 (1 bit)
access : read-write
RTY : Retry Test
bits : 12 - 12 (1 bit)
access : read-write
PEN : Pause Enable
bits : 13 - 13 (1 bit)
access : read-write
RXBUFO : Receive Buffer Offset
bits : 14 - 15 (2 bit)
access : read-write
LFERD : Length Field Error Frame Discard
bits : 16 - 16 (1 bit)
access : read-write
RFCS : Remove FCS
bits : 17 - 17 (1 bit)
access : read-write
CLK : MDC CLock Division
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0x0 : MCK_8
MCK divided by 8 (MCK up to 20 MHz)
0x1 : MCK_16
MCK divided by 16 (MCK up to 40 MHz)
0x2 : MCK_32
MCK divided by 32 (MCK up to 80 MHz)
0x3 : MCK_48
MCK divided by 48 (MCK up to 120 MHz)
0x4 : MCK_64
MCK divided by 64 (MCK up to 160 MHz)
0x5 : MCK_96
MCK divided by 96 (MCK up to 240 MHz)
End of enumeration elements list.
DBW : Data Bus Width
bits : 21 - 22 (2 bit)
access : read-write
DCPF : Disable Copy of Pause Frames
bits : 23 - 23 (1 bit)
access : read-write
RXCOEN : Receive Checksum Offload Enable
bits : 24 - 24 (1 bit)
access : read-write
EFRHD : Enable Frames Received in Half Duplex
bits : 25 - 25 (1 bit)
access : read-write
IRXFCS : Ignore RX FCS
bits : 26 - 26 (1 bit)
access : read-write
IPGSEN : IP Stretch Enable
bits : 28 - 28 (1 bit)
access : read-write
RXBP : Receive Bad Preamble
bits : 29 - 29 (1 bit)
access : read-write
IRXER : Ignore IPG GRXER
bits : 30 - 30 (1 bit)
access : read-write
RX Jumbo Frame Max Length Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FML : Frame Max Length
bits : 0 - 13 (14 bit)
access : read-write
Network Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDIO : MDIO Input Status
bits : 1 - 1 (1 bit)
access : read-only
IDLE : PHY Management Logic Idle
bits : 2 - 2 (1 bit)
access : read-only
RXLPIS : LPI Indication
bits : 7 - 7 (1 bit)
access : read-only
Hash Register Bottom
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Hash Address
bits : 0 - 31 (32 bit)
access : read-write
Hash Register Top
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Hash Address
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Bottom Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Top Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 2 Bottom Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 2
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 2 Top Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 2
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 3 Bottom Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 3
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 3 Top Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 3
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 4 Bottom Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 4
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 4 Top Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 4
bits : 0 - 15 (16 bit)
access : read-write
Type ID Match 1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 1
bits : 0 - 15 (16 bit)
access : read-write
ENID1 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 2 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 2
bits : 0 - 15 (16 bit)
access : read-write
ENID2 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 3 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 3
bits : 0 - 15 (16 bit)
access : read-write
ENID3 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write
Type ID Match 4 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 4
bits : 0 - 15 (16 bit)
access : read-write
ENID4 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write
Wake on LAN Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IP : ARP Request IP Address
bits : 0 - 15 (16 bit)
access : read-write
MAG : Magic Packet Event Enable
bits : 16 - 16 (1 bit)
access : read-write
ARP : ARP Request IP Address
bits : 17 - 17 (1 bit)
access : read-write
SA1 : Specific Address Register 1 Event Enable
bits : 18 - 18 (1 bit)
access : read-write
MTI : Multicast Hash Event Enable
bits : 19 - 19 (1 bit)
access : read-write
IPG Stretch Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FL : Frame Length
bits : 0 - 15 (16 bit)
access : read-write
User Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMII : Reduced MII Mode
bits : 0 - 0 (1 bit)
access : read-write
Stacked VLAN Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLAN_TYPE : User Defined VLAN_TYPE Field
bits : 0 - 15 (16 bit)
access : read-write
ESVLAN : Enable Stacked VLAN Processing Mode
bits : 31 - 31 (1 bit)
access : read-write
Transmit PFC Pause Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEV : Priority Enable Vector
bits : 0 - 7 (8 bit)
access : read-write
PQ : Pause Quantum
bits : 8 - 15 (8 bit)
access : read-write
Specific Address 1 Mask Bottom Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1 Mask
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Mask Top Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1 Mask
bits : 0 - 15 (16 bit)
access : read-write
1588 Timer Nanosecond Comparison Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NANOSEC : 1588 Timer Nanosecond Comparison Value
bits : 0 - 21 (22 bit)
access : read-write
1588 Timer Second Comparison Low Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1588 Timer Second Comparison Value
bits : 0 - 31 (32 bit)
access : read-write
1588 Timer Second Comparison High Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1588 Timer Second Comparison Value
bits : 0 - 15 (16 bit)
access : read-write
PTP Event Frame Transmitted Seconds High Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only
PTP Event Frame Received Seconds High Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only
PTP Peer Event Frame Transmitted Seconds High Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only
PTP Peer Event Frame Received Seconds High Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only
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