\n

GMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NCR

DCFGR

OTLO

OTHI

FT

BCFT

MFT

PFT

BFT64

TBFT127

TBFT255

TBFT511

TBFT1023

TBFT1518

GTBFT1518

TUR

SCF

MCF

TSR

EC

LC

DTF

CSE

ORLO

ORHI

FR

BCFR

MFR

PFR

BFR64

TBFR127

TBFR255

TBFR511

TBFR1023

TBFR1518

RBQB

TMXBFR

UFR

OFR

JR

FCSE

LFFE

RSE

AE

RRE

ROE

IHCE

TCE

UCE

TISUBN

TBQB

TSH

TSL

TN

TA

TI

EFTSL

EFTN

EFRSL

EFRN

PEFTSL

PEFTN

PEFRSL

PEFRN

RSR

ISR

RXLPI

RXLPITIME

TXLPI

TXLPITIME

IER

IDR

IMR

MAN

RPQ

TPQ

NCFGR

RJFML

NSR

HRB

HRT

SAB1

SAT1

SAB2

SAT2

SAB3

SAT3

SAB4

SAT4

TIDM1

TIDM2

TIDM3

TIDM4

WOL

IPGS

UR

SVLAN

TPFCP

SAMB1

SAMT1

NSC

SCL

SCH

EFTSH

EFRSH

PEFTSH

PEFRSH


NCR

Network Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR NCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBL RXEN TXEN MPE CLRSTAT INCSTAT WESTAT BP TSTART THALT TXPF TXZQPF SRTSM ENPBPR TXPBPF FNP TXLPIEN

LBL : Loop Back Local
bits : 1 - 1 (1 bit)
access : read-write

RXEN : Receive Enable
bits : 2 - 2 (1 bit)
access : read-write

TXEN : Transmit Enable
bits : 3 - 3 (1 bit)
access : read-write

MPE : Management Port Enable
bits : 4 - 4 (1 bit)
access : read-write

CLRSTAT : Clear Statistics Registers
bits : 5 - 5 (1 bit)
access : read-write

INCSTAT : Increment Statistics Registers
bits : 6 - 6 (1 bit)
access : read-write

WESTAT : Write Enable for Statistics Registers
bits : 7 - 7 (1 bit)
access : read-write

BP : Back pressure
bits : 8 - 8 (1 bit)
access : read-write

TSTART : Start Transmission
bits : 9 - 9 (1 bit)
access : read-write

THALT : Transmit Halt
bits : 10 - 10 (1 bit)
access : read-write

TXPF : Transmit Pause Frame
bits : 11 - 11 (1 bit)
access : read-write

TXZQPF : Transmit Zero Quantum Pause Frame
bits : 12 - 12 (1 bit)
access : read-write

SRTSM : Store Receive Time Stamp to Memory
bits : 15 - 15 (1 bit)
access : read-write

ENPBPR : Enable PFC Priority-based Pause Reception
bits : 16 - 16 (1 bit)
access : read-write

TXPBPF : Transmit PFC Priority-based Pause Frame
bits : 17 - 17 (1 bit)
access : read-write

FNP : Flush Next Packet
bits : 18 - 18 (1 bit)
access : read-write

TXLPIEN : Enable LPI Transmission
bits : 19 - 19 (1 bit)
access : read-write


DCFGR

DMA Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFGR DCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBLDO ESMA ESPA DRBS

FBLDO : Fixed Burst Length for DMA Data Operations:
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x1 : SINGLE

00001: Always use SINGLE AHB bursts

0x4 : INCR4

001xx: Attempt to use INCR4 AHB bursts (Default)

0x8 : INCR8

01xxx: Attempt to use INCR8 AHB bursts

0x10 : INCR16

1xxxx: Attempt to use INCR16 AHB bursts

End of enumeration elements list.

ESMA : Endian Swap Mode Enable for Management Descriptor Accesses
bits : 6 - 6 (1 bit)
access : read-write

ESPA : Endian Swap Mode Enable for Packet Data Accesses
bits : 7 - 7 (1 bit)
access : read-write

DRBS : DMA Receive Buffer Size
bits : 16 - 23 (8 bit)
access : read-write


OTLO

Octets Transmitted Low Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTLO OTLO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXO

TXO : Transmitted Octets
bits : 0 - 31 (32 bit)
access : read-only


OTHI

Octets Transmitted High Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OTHI OTHI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXO

TXO : Transmitted Octets
bits : 0 - 15 (16 bit)
access : read-only


FT

Frames Transmitted Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FT FT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTX

FTX : Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


BCFT

Broadcast Frames Transmitted Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCFT BCFT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFTX

BFTX : Broadcast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


MFT

Multicast Frames Transmitted Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFT MFT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFTX

MFTX : Multicast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


PFT

Pause Frames Transmitted Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PFT PFT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFTX

PFTX : Pause Frames Transmitted Register
bits : 0 - 15 (16 bit)
access : read-only


BFT64

64 Byte Frames Transmitted Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BFT64 BFT64 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 64 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFT127

65 to 127 Byte Frames Transmitted Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFT127 TBFT127 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 65 to 127 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFT255

128 to 255 Byte Frames Transmitted Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFT255 TBFT255 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 128 to 255 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFT511

256 to 511 Byte Frames Transmitted Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFT511 TBFT511 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 256 to 511 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFT1023

512 to 1023 Byte Frames Transmitted Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFT1023 TBFT1023 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 512 to 1023 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFT1518

1024 to 1518 Byte Frames Transmitted Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFT1518 TBFT1518 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : 1024 to 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


GTBFT1518

Greater Than 1518 Byte Frames Transmitted Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GTBFT1518 GTBFT1518 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFTX

NFTX : Greater than 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
access : read-only


TUR

Transmit Underruns Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TUR TUR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXUNR

TXUNR : Transmit Underruns
bits : 0 - 9 (10 bit)
access : read-only


SCF

Single Collision Frames Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCF SCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCOL

SCOL : Single Collision
bits : 0 - 17 (18 bit)
access : read-only


MCF

Multiple Collision Frames Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCF MCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCOL

MCOL : Multiple Collision
bits : 0 - 17 (18 bit)
access : read-only


TSR

Transmit Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBR COL RLE TXGO TFC TXCOMP UND HRESP

UBR : Used Bit Read
bits : 0 - 0 (1 bit)
access : read-write

COL : Collision Occurred
bits : 1 - 1 (1 bit)
access : read-write

RLE : Retry Limit Exceeded
bits : 2 - 2 (1 bit)
access : read-write

TXGO : Transmit Go
bits : 3 - 3 (1 bit)
access : read-write

TFC : Transmit Frame Corruption Due to AHB Error
bits : 4 - 4 (1 bit)
access : read-write

TXCOMP : Transmit Complete
bits : 5 - 5 (1 bit)
access : read-write

UND : Transmit Underrun
bits : 6 - 6 (1 bit)
access : read-write

HRESP : HRESP Not OK
bits : 8 - 8 (1 bit)
access : read-write


EC

Excessive Collisions Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EC EC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XCOL

XCOL : Excessive Collisions
bits : 0 - 9 (10 bit)
access : read-only


LC

Late Collisions Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LC LC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCOL

LCOL : Late Collisions
bits : 0 - 9 (10 bit)
access : read-only


DTF

Deferred Transmission Frames Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DTF DTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEFT

DEFT : Deferred Transmission
bits : 0 - 17 (18 bit)
access : read-only


CSE

Carrier Sense Errors Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSE CSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSR

CSR : Carrier Sense Error
bits : 0 - 9 (10 bit)
access : read-only


ORLO

Octets Received Low Received Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ORLO ORLO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXO

RXO : Received Octets
bits : 0 - 31 (32 bit)
access : read-only


ORHI

Octets Received High Received Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ORHI ORHI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXO

RXO : Received Octets
bits : 0 - 15 (16 bit)
access : read-only


FR

Frames Received Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FR FR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRX

FRX : Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


BCFR

Broadcast Frames Received Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BCFR BCFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFRX

BFRX : Broadcast Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


MFR

Multicast Frames Received Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFR MFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFRX

MFRX : Multicast Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


PFR

Pause Frames Received Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PFR PFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFRX

PFRX : Pause Frames Received Register
bits : 0 - 15 (16 bit)
access : read-only


BFR64

64 Byte Frames Received Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BFR64 BFR64 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 64 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFR127

65 to 127 Byte Frames Received Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFR127 TBFR127 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 65 to 127 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFR255

128 to 255 Byte Frames Received Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFR255 TBFR255 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 128 to 255 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFR511

256 to 511 Byte Frames Received Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFR511 TBFR511 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 256 to 511 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFR1023

512 to 1023 Byte Frames Received Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFR1023 TBFR1023 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 512 to 1023 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


TBFR1518

1024 to 1518 Byte Frames Received Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TBFR1518 TBFR1518 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 1024 to 1518 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


RBQB

Receive Buffer Queue Base Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBQB RBQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write


TMXBFR

1519 to Maximum Byte Frames Received Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TMXBFR TMXBFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NFRX

NFRX : 1519 to Maximum Byte Frames Received without Error
bits : 0 - 31 (32 bit)
access : read-only


UFR

Undersize Frames Received Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UFR UFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UFRX

UFRX : Undersize Frames Received
bits : 0 - 9 (10 bit)
access : read-only


OFR

Oversize Frames Received Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OFR OFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFRX

OFRX : Oversized Frames Received
bits : 0 - 9 (10 bit)
access : read-only


JR

Jabbers Received Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JR JR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JRX

JRX : Jabbers Received
bits : 0 - 9 (10 bit)
access : read-only


FCSE

Frame Check Sequence Errors Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FCSE FCSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCKR

FCKR : Frame Check Sequence Errors
bits : 0 - 9 (10 bit)
access : read-only


LFFE

Length Field Frame Errors Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LFFE LFFE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFER

LFER : Length Field Frame Errors
bits : 0 - 9 (10 bit)
access : read-only


RSE

Receive Symbol Errors Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSE RSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXSE

RXSE : Receive Symbol Errors
bits : 0 - 9 (10 bit)
access : read-only


AE

Alignment Errors Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AE AE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AER

AER : Alignment Errors
bits : 0 - 9 (10 bit)
access : read-only


RRE

Receive Resource Errors Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RRE RRE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRER

RXRER : Receive Resource Errors
bits : 0 - 17 (18 bit)
access : read-only


ROE

Receive Overrun Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROE ROE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXOVR

RXOVR : Receive Overruns
bits : 0 - 9 (10 bit)
access : read-only


IHCE

IP Header Checksum Errors Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IHCE IHCE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCKER

HCKER : IP Header Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only


TCE

TCP Checksum Errors Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCE TCE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCKER

TCKER : TCP Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only


UCE

UDP Checksum Errors Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UCE UCE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCKER

UCKER : UDP Checksum Errors
bits : 0 - 7 (8 bit)
access : read-only


TISUBN

1588 Timer Increment Sub-nanoseconds Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TISUBN TISUBN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSBTIR

LSBTIR : Lower Significant Bits of Timer Increment Register
bits : 0 - 15 (16 bit)
access : read-write


TBQB

Transmit Buffer Queue Base Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBQB TBQB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write


TSH

1588 Timer Seconds High Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSH TSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCS

TCS : Timer Count in Seconds
bits : 0 - 15 (16 bit)
access : read-write


TSL

1588 Timer Seconds Low Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSL TSL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCS

TCS : Timer Count in Seconds
bits : 0 - 31 (32 bit)
access : read-write


TN

1588 Timer Nanoseconds Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TN TN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TNS

TNS : Timer Count in Nanoseconds
bits : 0 - 29 (30 bit)
access : read-write


TA

1588 Timer Adjust Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TA TA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITDT ADJ

ITDT : Increment/Decrement
bits : 0 - 29 (30 bit)
access : write-only

ADJ : Adjust 1588 Timer
bits : 31 - 31 (1 bit)
access : write-only


TI

1588 Timer Increment Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TI TI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNS ACNS NIT

CNS : Count Nanoseconds
bits : 0 - 7 (8 bit)
access : read-write

ACNS : Alternative Count Nanoseconds
bits : 8 - 15 (8 bit)
access : read-write

NIT : Number of Increments
bits : 16 - 23 (8 bit)
access : read-write


EFTSL

PTP Event Frame Transmitted Seconds Low Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFTSL EFTSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only


EFTN

PTP Event Frame Transmitted Nanoseconds Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFTN EFTN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only


EFRSL

PTP Event Frame Received Seconds Low Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFRSL EFRSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only


EFRN

PTP Event Frame Received Nanoseconds Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFRN EFRN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only


PEFTSL

PTP Peer Event Frame Transmitted Seconds Low Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFTSL PEFTSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only


PEFTN

PTP Peer Event Frame Transmitted Nanoseconds Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFTN PEFTN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only


PEFRSL

PTP Peer Event Frame Received Seconds Low Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFRSL PEFRSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 31 (32 bit)
access : read-only


PEFRN

PTP Peer Event Frame Received Nanoseconds Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFRN PEFRN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 29 (30 bit)
access : read-only


RSR

Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSR RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BNA REC RXOVR HNO

BNA : Buffer Not Available
bits : 0 - 0 (1 bit)
access : read-write

REC : Frame Received
bits : 1 - 1 (1 bit)
access : read-write

RXOVR : Receive Overrun
bits : 2 - 2 (1 bit)
access : read-write

HNO : HRESP Not OK
bits : 3 - 3 (1 bit)
access : read-write


ISR

Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS RCOMP RXUBR TXUBR TUR RLEX TFC TCOMP ROVR HRESP PFNZ PTZ PFTR DRQFR SFR DRQFT SFT PDRQFR PDRSFR PDRQFT PDRSFT SRI RXLPISBC WOL TSUTIMCOMP

MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : read-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only

RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only

TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : read-only

TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : read-only

RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-only

TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only

HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-only

PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : read-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-only

PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : read-only

DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : read-only

SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : read-only

DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : read-only

SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : read-only

PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : read-only

PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : read-only

PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : read-only

PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : read-only

SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : read-only

RXLPISBC : Receive LPI indication Status Bit Change
bits : 27 - 27 (1 bit)
access : read-only

WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : read-only

TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : read-only


RXLPI

Received LPI Transitions
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXLPI RXLPI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Count of RX LPI transitions (cleared on read)
bits : 0 - 15 (16 bit)
access : read-only


RXLPITIME

Received LPI Time
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXLPITIME RXLPITIME read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPITIME

LPITIME : Time in LPI (cleared on read)
bits : 0 - 23 (24 bit)
access : read-only


TXLPI

Transmit LPI Transitions
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXLPI TXLPI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Count of LPI transitions (cleared on read)
bits : 0 - 15 (16 bit)
access : read-only


TXLPITIME

Transmit LPI Time
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXLPITIME TXLPITIME read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPITIME

LPITIME : Time in LPI (cleared on read)
bits : 0 - 23 (24 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS RCOMP RXUBR TXUBR TUR RLEX TFC TCOMP ROVR HRESP PFNZ PTZ PFTR EXINT DRQFR SFR DRQFT SFT PDRQFR PDRSFR PDRQFT PDRSFT SRI RXLPISBC WOL TSUTIMCOMP

MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : write-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only

RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only

TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only

TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : write-only

RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only

TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only

HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only

PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : write-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only

PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : write-only

EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : write-only

DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : write-only

SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : write-only

DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : write-only

SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : write-only

PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : write-only

PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : write-only

PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : write-only

PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : write-only

SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : write-only

RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : write-only

WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : write-only

TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS RCOMP RXUBR TXUBR TUR RLEX TFC TCOMP ROVR HRESP PFNZ PTZ PFTR EXINT DRQFR SFR DRQFT SFT PDRQFR PDRSFR PDRQFT PDRSFT SRI RXLPISBC WOL TSUTIMCOMP

MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : write-only

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only

RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only

TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : write-only

TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : write-only

RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only

TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only

HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only

PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : write-only

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : write-only

PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : write-only

EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : write-only

DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : write-only

SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : write-only

DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : write-only

SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : write-only

PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : write-only

PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : write-only

PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : write-only

PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : write-only

SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : write-only

RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : write-only

WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : write-only

TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFS RCOMP RXUBR TXUBR TUR RLEX TFC TCOMP ROVR HRESP PFNZ PTZ PFTR EXINT DRQFR SFR DRQFT SFT PDRQFR PDRSFR PDRQFT PDRSFT SRI RXLPISBC WOL TSUTIMCOMP

MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
access : read-write

RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write

RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write

TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
access : read-write

TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
access : read-write

RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
access : read-write

TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-write

TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write

ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write

HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-write

PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
access : read-write

PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
access : read-write

PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
access : read-write

EXINT : External Interrupt
bits : 15 - 15 (1 bit)
access : read-write

DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
access : read-write

SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
access : read-write

DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
access : read-write

SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
access : read-write

PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
access : read-write

PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
access : read-write

PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
access : read-write

PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
access : read-write

SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
access : read-write

RXLPISBC : Enable RX LPI Indication
bits : 27 - 27 (1 bit)
access : read-write

WOL : Wake On LAN
bits : 28 - 28 (1 bit)
access : read-write

TSUTIMCOMP : TSU Timer Comparison
bits : 29 - 29 (1 bit)
access : read-write


MAN

PHY Maintenance Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAN MAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA WTN REGA PHYA OP CLTTO WZO

DATA : PHY Data
bits : 0 - 15 (16 bit)
access : read-write

WTN : Write Ten
bits : 16 - 17 (2 bit)
access : read-write

REGA : Register Address
bits : 18 - 22 (5 bit)
access : read-write

PHYA : PHY Address
bits : 23 - 27 (5 bit)
access : read-write

OP : Operation
bits : 28 - 29 (2 bit)
access : read-write

CLTTO : Clause 22 Operation
bits : 30 - 30 (1 bit)
access : read-write

WZO : Write ZERO
bits : 31 - 31 (1 bit)
access : read-write


RPQ

Received Pause Quantum Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RPQ RPQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPQ

RPQ : Received Pause Quantum
bits : 0 - 15 (16 bit)
access : read-only


TPQ

Transmit Pause Quantum Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPQ TPQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPQ

TPQ : Transmit Pause Quantum
bits : 0 - 15 (16 bit)
access : read-write


NCFGR

Network Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCFGR NCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPD FD DNVLAN JFRAME CAF NBC MTIHEN UNIHEN MAXFS RTY PEN RXBUFO LFERD RFCS CLK DBW DCPF RXCOEN EFRHD IRXFCS IPGSEN RXBP IRXER

SPD : Speed
bits : 0 - 0 (1 bit)
access : read-write

FD : Full Duplex
bits : 1 - 1 (1 bit)
access : read-write

DNVLAN : Discard Non-VLAN FRAMES
bits : 2 - 2 (1 bit)
access : read-write

JFRAME : Jumbo Frame Size
bits : 3 - 3 (1 bit)
access : read-write

CAF : Copy All Frames
bits : 4 - 4 (1 bit)
access : read-write

NBC : No Broadcast
bits : 5 - 5 (1 bit)
access : read-write

MTIHEN : Multicast Hash Enable
bits : 6 - 6 (1 bit)
access : read-write

UNIHEN : Unicast Hash Enable
bits : 7 - 7 (1 bit)
access : read-write

MAXFS : 1536 Maximum Frame Size
bits : 8 - 8 (1 bit)
access : read-write

RTY : Retry Test
bits : 12 - 12 (1 bit)
access : read-write

PEN : Pause Enable
bits : 13 - 13 (1 bit)
access : read-write

RXBUFO : Receive Buffer Offset
bits : 14 - 15 (2 bit)
access : read-write

LFERD : Length Field Error Frame Discard
bits : 16 - 16 (1 bit)
access : read-write

RFCS : Remove FCS
bits : 17 - 17 (1 bit)
access : read-write

CLK : MDC CLock Division
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

0x0 : MCK_8

MCK divided by 8 (MCK up to 20 MHz)

0x1 : MCK_16

MCK divided by 16 (MCK up to 40 MHz)

0x2 : MCK_32

MCK divided by 32 (MCK up to 80 MHz)

0x3 : MCK_48

MCK divided by 48 (MCK up to 120 MHz)

0x4 : MCK_64

MCK divided by 64 (MCK up to 160 MHz)

0x5 : MCK_96

MCK divided by 96 (MCK up to 240 MHz)

End of enumeration elements list.

DBW : Data Bus Width
bits : 21 - 22 (2 bit)
access : read-write

DCPF : Disable Copy of Pause Frames
bits : 23 - 23 (1 bit)
access : read-write

RXCOEN : Receive Checksum Offload Enable
bits : 24 - 24 (1 bit)
access : read-write

EFRHD : Enable Frames Received in Half Duplex
bits : 25 - 25 (1 bit)
access : read-write

IRXFCS : Ignore RX FCS
bits : 26 - 26 (1 bit)
access : read-write

IPGSEN : IP Stretch Enable
bits : 28 - 28 (1 bit)
access : read-write

RXBP : Receive Bad Preamble
bits : 29 - 29 (1 bit)
access : read-write

IRXER : Ignore IPG GRXER
bits : 30 - 30 (1 bit)
access : read-write


RJFML

RX Jumbo Frame Max Length Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RJFML RJFML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FML

FML : Frame Max Length
bits : 0 - 13 (14 bit)
access : read-write


NSR

Network Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NSR NSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIO IDLE RXLPIS

MDIO : MDIO Input Status
bits : 1 - 1 (1 bit)
access : read-only

IDLE : PHY Management Logic Idle
bits : 2 - 2 (1 bit)
access : read-only

RXLPIS : LPI Indication
bits : 7 - 7 (1 bit)
access : read-only


HRB

Hash Register Bottom
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRB HRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Hash Address
bits : 0 - 31 (32 bit)
access : read-write


HRT

Hash Register Top
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HRT HRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Hash Address
bits : 0 - 31 (32 bit)
access : read-write


SAB1

Specific Address 1 Bottom Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAB1 SAB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
access : read-write


SAT1

Specific Address 1 Top Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAT1 SAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
access : read-write


SAB2

Specific Address 2 Bottom Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAB2 SAB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 2
bits : 0 - 31 (32 bit)
access : read-write


SAT2

Specific Address 2 Top Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAT2 SAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 2
bits : 0 - 15 (16 bit)
access : read-write


SAB3

Specific Address 3 Bottom Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAB3 SAB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 3
bits : 0 - 31 (32 bit)
access : read-write


SAT3

Specific Address 3 Top Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAT3 SAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 3
bits : 0 - 15 (16 bit)
access : read-write


SAB4

Specific Address 4 Bottom Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAB4 SAB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 4
bits : 0 - 31 (32 bit)
access : read-write


SAT4

Specific Address 4 Top Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAT4 SAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 4
bits : 0 - 15 (16 bit)
access : read-write


TIDM1

Type ID Match 1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIDM1 TIDM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TID ENID1

TID : Type ID Match 1
bits : 0 - 15 (16 bit)
access : read-write

ENID1 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write


TIDM2

Type ID Match 2 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIDM2 TIDM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TID ENID2

TID : Type ID Match 2
bits : 0 - 15 (16 bit)
access : read-write

ENID2 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write


TIDM3

Type ID Match 3 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIDM3 TIDM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TID ENID3

TID : Type ID Match 3
bits : 0 - 15 (16 bit)
access : read-write

ENID3 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write


TIDM4

Type ID Match 4 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIDM4 TIDM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TID ENID4

TID : Type ID Match 4
bits : 0 - 15 (16 bit)
access : read-write

ENID4 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
access : read-write


WOL

Wake on LAN Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WOL WOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IP MAG ARP SA1 MTI

IP : ARP Request IP Address
bits : 0 - 15 (16 bit)
access : read-write

MAG : Magic Packet Event Enable
bits : 16 - 16 (1 bit)
access : read-write

ARP : ARP Request IP Address
bits : 17 - 17 (1 bit)
access : read-write

SA1 : Specific Address Register 1 Event Enable
bits : 18 - 18 (1 bit)
access : read-write

MTI : Multicast Hash Event Enable
bits : 19 - 19 (1 bit)
access : read-write


IPGS

IPG Stretch Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPGS IPGS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FL

FL : Frame Length
bits : 0 - 15 (16 bit)
access : read-write


UR

User Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR UR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMII

RMII : Reduced MII Mode
bits : 0 - 0 (1 bit)
access : read-write


SVLAN

Stacked VLAN Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVLAN SVLAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLAN_TYPE ESVLAN

VLAN_TYPE : User Defined VLAN_TYPE Field
bits : 0 - 15 (16 bit)
access : read-write

ESVLAN : Enable Stacked VLAN Processing Mode
bits : 31 - 31 (1 bit)
access : read-write


TPFCP

Transmit PFC Pause Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPFCP TPFCP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEV PQ

PEV : Priority Enable Vector
bits : 0 - 7 (8 bit)
access : read-write

PQ : Pause Quantum
bits : 8 - 15 (8 bit)
access : read-write


SAMB1

Specific Address 1 Mask Bottom Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMB1 SAMB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 1 Mask
bits : 0 - 31 (32 bit)
access : read-write


SAMT1

Specific Address 1 Mask Top Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMT1 SAMT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Specific Address 1 Mask
bits : 0 - 15 (16 bit)
access : read-write


NSC

1588 Timer Nanosecond Comparison Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSC NSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NANOSEC

NANOSEC : 1588 Timer Nanosecond Comparison Value
bits : 0 - 21 (22 bit)
access : read-write


SCL

1588 Timer Second Comparison Low Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL SCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC

SEC : 1588 Timer Second Comparison Value
bits : 0 - 31 (32 bit)
access : read-write


SCH

1588 Timer Second Comparison High Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCH SCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC

SEC : 1588 Timer Second Comparison Value
bits : 0 - 15 (16 bit)
access : read-write


EFTSH

PTP Event Frame Transmitted Seconds High Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFTSH EFTSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only


EFRSH

PTP Event Frame Received Seconds High Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EFRSH EFRSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only


PEFTSH

PTP Peer Event Frame Transmitted Seconds High Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFTSH PEFTSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only


PEFRSH

PTP Peer Event Frame Received Seconds High Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEFRSH PEFRSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUD

RUD : Register Update
bits : 0 - 15 (16 bit)
access : read-only



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