\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGNED : Signed
bits : 0 - 0 (1 bit)
DLZ : Disable Leading Zero Optimization
bits : 1 - 1 (1 bit)
Result
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : RESULT
bits : 0 - 31 (32 bit)
access : read-only
Remainder
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REM : REM
bits : 0 - 31 (32 bit)
access : read-only
Square Root Input
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQRNUM : Square Root Input
bits : 0 - 31 (32 bit)
Status
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : DIVAS Accelerator Busy
bits : 0 - 0 (1 bit)
access : read-only
DBZ : Writing a one to this bit clears DBZ to zero
bits : 1 - 1 (1 bit)
Dividend
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDEND : DIVIDEND
bits : 0 - 31 (32 bit)
Divisor
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVISOR : DIVISOR
bits : 0 - 31 (32 bit)
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