CR

DLR

CCR

AR

ABR

DR

PSMKR

PSMAR

PIR

LPTR

DCR

SR

FCR

EN : Enable Enable the QUADSPI.
bits : 0 - 0 (1 bit)

ABORT : Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is complete. This bit stops the current transfer. In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit.
bits : 1 - 1 (1 bit)

DMAEN : DMA enable In indirect mode, DMA can be used to input or output data via the QUADSPI_DR register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set.
bits : 2 - 2 (1 bit)

TCEN : Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR). Enable the timeout counter. By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO becomes full with prefetch data. This bit can be modified only when BUSY = 0.
bits : 3 - 3 (1 bit)

SSHIFT : Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays. Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1). This field can be modified only when BUSY = 0.
bits : 4 - 4 (1 bit)

DFM : Dual-flash mode This bit activates dual-flash mode, where two external Flash memories are used simultaneously to double throughput and capacity. This bit can be modified only when BUSY = 0.
bits : 6 - 6 (1 bit)

FSEL : Flash memory selection This bit selects the Flash memory to be addressed in single flash mode (when DFM = 0). This bit can be modified only when BUSY = 0. This bit is ignored when DFM = 1.
bits : 7 - 7 (1 bit)

FTHRES : FIFO threshold level Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set. In indirect write mode (FMODE = 00): ... In indirect read mode (FMODE = 01): ... If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled before changing the FTHRES value.
bits : 8 - 12 (5 bit)

TEIE : Transfer error interrupt enable This bit enables the transfer error interrupt.
bits : 16 - 16 (1 bit)

TCIE : Transfer complete interrupt enable This bit enables the transfer complete interrupt.
bits : 17 - 17 (1 bit)

FTIE : FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.
bits : 18 - 18 (1 bit)

SMIE : Status match interrupt enable This bit enables the status match interrupt.
bits : 19 - 19 (1 bit)

TOIE : TimeOut interrupt enable This bit enables the TimeOut interrupt.
bits : 20 - 20 (1 bit)

APMS : Automatic poll mode stop This bit determines if automatic polling is stopped after a match. This bit can be modified only when BUSY = 0.
bits : 22 - 22 (1 bit)

PMM : Polling match mode This bit indicates which method should be used for determining a match during automatic polling mode. This bit can be modified only when BUSY = 0.
bits : 23 - 23 (1 bit)

PRESCALER : clock prescaler
bits : 24 - 31 (8 bit)

DL : Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. 0x0000_0000: 1 byte is to be transferred 0x0000_0001: 2 bytes are to be transferred 0x0000_0002: 3 bytes are to be transferred 0x0000_0003: 4 bytes are to be transferred ... 0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred 0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred 0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F. DL[0] is stuck at 1 in dual-flash mode (DFM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes. This field has no effect when in memory-mapped mode (FMODE = 10). This field can be written only when BUSY = 0.
bits : 0 - 31 (32 bit)

INSTRUCTION : Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0.
bits : 0 - 7 (8 bit)

IMODE : Instruction mode This field defines the instruction phase mode of operation: This field can be written only when BUSY = 0.
bits : 8 - 9 (2 bit)

ADMODE : Address mode This field defines the address phase mode of operation: This field can be written only when BUSY = 0.
bits : 10 - 11 (2 bit)

ADSIZE : Address size This bit defines address size: This field can be written only when BUSY = 0.
bits : 12 - 13 (2 bit)

ABMODE : Alternate bytes mode This field defines the alternate-bytes phase mode of operation: This field can be written only when BUSY = 0.
bits : 14 - 15 (2 bit)

ABSIZE : Alternate bytes size This bit defines alternate bytes size: This field can be written only when BUSY = 0.
bits : 16 - 17 (2 bit)

DCYC : Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0.
bits : 18 - 22 (5 bit)

DMODE : Data mode This field defines the data phases mode of operation: This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0.
bits : 24 - 25 (2 bit)

FMODE : Functional mode This field defines the QUADSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0.
bits : 26 - 27 (2 bit)

SIOO : Send instruction only once mode See Section15.3.11: Sending the instruction only once on page13. This bit has no effect when IMODE = 00. This field can be written only when BUSY = 0.
bits : 28 - 28 (1 bit)

DHHC : DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: This feature is only active in DDR mode. This field can be written only when BUSY = 0.
bits : 30 - 30 (1 bit)

DDRM : Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: This field can be written only when BUSY = 0.
bits : 31 - 31 (1 bit)

ADDRESS : [31 0]: Address Address to be send to the external Flash memory Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped mode). In dual flash mode, ADDRESS[0] is automatically stuck to 0 as the address should always be even
bits : 0 - 31 (32 bit)

ALTERNATE : Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0.
bits : 0 - 31 (32 bit)

DATA : Data Data to be sent/received to/from the external SPI device. In indirect write mode, data written to this register is stored on the FIFO before it is sent to the Flash memory during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written. In indirect read mode, reading this register gives (via the FIFO) the data which was received from the Flash memory. If the FIFO does not have as many bytes as requested by the read operation and if BUSY=1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first. In automatic polling mode, this register contains the last data read from the Flash memory (without masking). Word, halfword, and byte accesses to this register are supported. In indirect write mode, a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a byte read must read DATA[7:0] and a halfword read must read DATA[15:0].
bits : 0 - 31 (32 bit)

MASK : Status mask Mask to be applied to the status bytes received in polling mode. For bit n: This field can be written only when BUSY = 0.
bits : 0 - 31 (32 bit)

MATCH : Status match Value to be compared with the masked status register to get a match. This field can be written only when BUSY = 0.
bits : 0 - 31 (32 bit)

INTERVAL : Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0.
bits : 0 - 15 (16 bit)

TIMEOUT : Timeout period After each access in memory-mapped mode, the QUADSPI prefetches the subsequent bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash memory in a lower-consumption state. This field can be written only when BUSY = 0.
bits : 0 - 15 (16 bit)

CKMODE : indicates the level that clk takes between command
bits : 0 - 0 (1 bit)

CSHT : Chip select high time CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must remain high between commands issued to the Flash memory. ... This field can be modified only when BUSY = 0.
bits : 8 - 10 (3 bit)

FSIZE : Flash memory size This field defines the size of external memory using the following formula: Number of bytes in Flash memory = 2[FSIZE+1] FSIZE+1 is effectively the number of address bits required to address the Flash memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB. If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together. This field can be modified only when BUSY = 0.
bits : 16 - 20 (5 bit)

TEF : Transfer error flag This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF.
bits : 0 - 0 (1 bit)

TCF : Transfer complete flag This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.
bits : 1 - 1 (1 bit)

FTF : FIFO threshold flag In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after reads from the Flash memory are complete. It is cleared automatically as soon as threshold condition is no longer true. In automatic polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read.
bits : 2 - 2 (1 bit)

SMF : Status match flag This bit is set in automatic polling mode when the unmasked received data matches the corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1 to CSMF.
bits : 3 - 3 (1 bit)

TOF : Timeout flag This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.
bits : 4 - 4 (1 bit)

BUSY : Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty.
bits : 5 - 5 (1 bit)

FLEVEL : FIFO level This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0 when the FIFO is empty, and 16 when it is full. In memory-mapped mode and in automatic status polling mode, FLEVEL is zero.
bits : 8 - 13 (6 bit)

CTEF : Clear transfer error flag Writing 1 clears the TEF flag in the QUADSPI_SR register
bits : 0 - 0 (1 bit)

CTCF : Clear transfer complete flag Writing 1 clears the TCF flag in the QUADSPI_SR register
bits : 1 - 1 (1 bit)

CSMF : Clear status match flag Writing 1 clears the SMF flag in the QUADSPI_SR register
bits : 3 - 3 (1 bit)

CTOF : Clear timeout flag Writing 1 clears the TOF flag in the QUADSPI_SR register
bits : 4 - 4 (1 bit)