Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : Second units in BCD format
bits : 0 - 3 (4 bit)
ST : Second tens in BCD format
bits : 4 - 6 (3 bit)
MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)
MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)
HU : Hour units in BCD format
bits : 16 - 19 (4 bit)
HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)
PM : AM/PM notation
bits : 22 - 22 (1 bit)
This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREDIV_S : Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
bits : 0 - 14 (15 bit)
PREDIV_A : Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
bits : 16 - 22 (7 bit)
This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUT : Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.
bits : 0 - 15 (16 bit)
This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : Second units in BCD format.
bits : 0 - 3 (4 bit)
ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)
MSK1 : Alarm A seconds mask
bits : 7 - 7 (1 bit)
MNU : Minute units in BCD format.
bits : 8 - 11 (4 bit)
MNT : Minute tens in BCD format.
bits : 12 - 14 (3 bit)
MSK2 : Alarm A minutes mask
bits : 15 - 15 (1 bit)
HU : Hour units in BCD format.
bits : 16 - 19 (4 bit)
HT : Hour tens in BCD format.
bits : 20 - 21 (2 bit)
PM : AM/PM notation
bits : 22 - 22 (1 bit)
MSK3 : Alarm A hours mask
bits : 23 - 23 (1 bit)
DU : Date units or day in BCD format.
bits : 24 - 27 (4 bit)
DT : Date tens in BCD format.
bits : 28 - 29 (2 bit)
WDSEL : Week day selection
bits : 30 - 30 (1 bit)
MSK4 : Alarm A date mask
bits : 31 - 31 (1 bit)
This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SU : Second units in BCD format
bits : 0 - 3 (4 bit)
ST : Second tens in BCD format
bits : 4 - 6 (3 bit)
MSK1 : Alarm B seconds mask
bits : 7 - 7 (1 bit)
MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)
MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)
MSK2 : Alarm B minutes mask
bits : 15 - 15 (1 bit)
HU : Hour units in BCD format
bits : 16 - 19 (4 bit)
HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)
PM : AM/PM notation
bits : 22 - 22 (1 bit)
MSK3 : Alarm B hours mask
bits : 23 - 23 (1 bit)
DU : Date units or day in BCD format
bits : 24 - 27 (4 bit)
DT : Date tens in BCD format
bits : 28 - 29 (2 bit)
WDSEL : Week day selection
bits : 30 - 30 (1 bit)
MSK4 : Alarm B date mask
bits : 31 - 31 (1 bit)
RTC write protection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection.
bits : 0 - 7 (8 bit)
RTC sub second register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SS : Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
bits : 0 - 15 (16 bit)
This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUBFS : Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time.
bits : 0 - 14 (15 bit)
ADD1S : Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
bits : 31 - 31 (1 bit)
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SU : Second units in BCD format.
bits : 0 - 3 (4 bit)
ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)
MNU : Minute units in BCD format.
bits : 8 - 11 (4 bit)
MNT : Minute tens in BCD format.
bits : 12 - 14 (3 bit)
HU : Hour units in BCD format.
bits : 16 - 19 (4 bit)
HT : Hour tens in BCD format.
bits : 20 - 21 (2 bit)
PM : AM/PM notation
bits : 22 - 22 (1 bit)
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DU : Date units in BCD format
bits : 0 - 3 (4 bit)
DT : Date tens in BCD format
bits : 4 - 5 (2 bit)
MU : Month units in BCD format
bits : 8 - 11 (4 bit)
MT : Month tens in BCD format
bits : 12 - 12 (1 bit)
WDU : Week day units
bits : 13 - 15 (3 bit)
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SS : Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred.
bits : 0 - 15 (16 bit)
This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALM : Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13.
bits : 0 - 8 (9 bit)
CALW16 : Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration.
bits : 13 - 13 (1 bit)
CALW8 : Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration.
bits : 14 - 14 (1 bit)
CALP : Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration.
bits : 15 - 15 (1 bit)
The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DU : Date units in BCD format
bits : 0 - 3 (4 bit)
DT : Date tens in BCD format
bits : 4 - 5 (2 bit)
MU : Month units in BCD format
bits : 8 - 11 (4 bit)
MT : Month tens in BCD format
bits : 12 - 12 (1 bit)
WDU : Week day units
bits : 13 - 15 (3 bit)
YU : Year units in BCD format
bits : 16 - 19 (4 bit)
YT : Year tens in BCD format
bits : 20 - 23 (4 bit)
RTC tamper and alternate function configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAMP1E : RTC_TAMP1 input detection enable
bits : 0 - 0 (1 bit)
TAMP1TRG : Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:
bits : 1 - 1 (1 bit)
TAMPIE : Tamper interrupt enable
bits : 2 - 2 (1 bit)
TAMP2E : RTC_TAMP2 input detection enable
bits : 3 - 3 (1 bit)
TAMP2TRG : Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:
bits : 4 - 4 (1 bit)
TAMP3E : RTC_TAMP3 detection enable
bits : 5 - 5 (1 bit)
TAMP3TRG : Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:
bits : 6 - 6 (1 bit)
TAMPTS : Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register.
bits : 7 - 7 (1 bit)
TAMPFREQ : Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled.
bits : 8 - 10 (3 bit)
TAMPFLT : RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs.
bits : 11 - 12 (2 bit)
TAMPPRCH : RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs.
bits : 13 - 14 (2 bit)
TAMPPUDIS : RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample.
bits : 15 - 15 (1 bit)
TAMP1IE : Tamper 1 interrupt enable
bits : 16 - 16 (1 bit)
TAMP1NOERASE : Tamper 1 no erase
bits : 17 - 17 (1 bit)
TAMP1MF : Tamper 1 mask flag
bits : 18 - 18 (1 bit)
TAMP2IE : Tamper 2 interrupt enable
bits : 19 - 19 (1 bit)
TAMP2NOERASE : Tamper 2 no erase
bits : 20 - 20 (1 bit)
TAMP2MF : Tamper 2 mask flag
bits : 21 - 21 (1 bit)
TAMP3IE : Tamper 3 interrupt enable
bits : 22 - 22 (1 bit)
TAMP3NOERASE : Tamper 3 no erase
bits : 23 - 23 (1 bit)
TAMP3MF : Tamper 3 mask flag
bits : 24 - 24 (1 bit)
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
bits : 0 - 14 (15 bit)
MASKSS : Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
bits : 24 - 27 (4 bit)
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
bits : 0 - 14 (15 bit)
MASKSS : Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
bits : 24 - 27 (4 bit)
RTC option register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_ALARM_TYPE : RTC_ALARM output type on PC13
bits : 0 - 0 (1 bit)
RTC_OUT_RMP : RTC_OUT remap
bits : 1 - 1 (1 bit)
RTC backup registers
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUCKSEL : Wakeup clock selection
bits : 0 - 2 (3 bit)
access : read-write
TSEDGE : Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
bits : 3 - 3 (1 bit)
access : read-write
REFCKON : RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
bits : 4 - 4 (1 bit)
access : read-write
BYPSHAD : Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
bits : 5 - 5 (1 bit)
access : read-write
FMT : Hour format
bits : 6 - 6 (1 bit)
access : read-write
ALRAE : Alarm A enable
bits : 8 - 8 (1 bit)
access : read-write
ALRBE : Alarm B enable
bits : 9 - 9 (1 bit)
access : read-write
WUTE : Wakeup timer enable
bits : 10 - 10 (1 bit)
access : read-write
TSE : timestamp enable
bits : 11 - 11 (1 bit)
access : read-write
ALRAIE : Alarm A interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
ALRBIE : Alarm B interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
WUTIE : Wakeup timer interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
TSIE : Time-stamp interrupt enable
bits : 15 - 15 (1 bit)
access : read-write
ADD1H : Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
bits : 16 - 16 (1 bit)
access : write-only
SUB1H : Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
bits : 17 - 17 (1 bit)
access : write-only
BKP : Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
bits : 18 - 18 (1 bit)
access : read-write
COSEL : Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output
bits : 19 - 19 (1 bit)
access : read-write
POL : Output polarity This bit is used to configure the polarity of RTC_ALARM output
bits : 20 - 20 (1 bit)
access : read-write
OSEL : Output selection These bits are used to select the flag to be routed to RTC_ALARM output
bits : 21 - 22 (2 bit)
access : read-write
COE : Calibration output enable This bit enables the RTC_CALIB output
bits : 23 - 23 (1 bit)
access : read-write
ITSE : timestamp on internal event enable
bits : 24 - 24 (1 bit)
access : read-write
RTC backup registers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALRAWF : Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
bits : 0 - 0 (1 bit)
access : read-only
ALRBWF : Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
bits : 1 - 1 (1 bit)
access : read-only
WUTWF : Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
bits : 2 - 2 (1 bit)
access : read-only
SHPF : Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
bits : 3 - 3 (1 bit)
access : read-only
INITS : Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
bits : 4 - 4 (1 bit)
access : read-only
RSF : Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
bits : 5 - 5 (1 bit)
access : read-write
INITF : Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
bits : 6 - 6 (1 bit)
access : read-only
INIT : Initialization mode
bits : 7 - 7 (1 bit)
access : read-write
ALRAF : Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0.
bits : 8 - 8 (1 bit)
access : read-write
ALRBF : Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0.
bits : 9 - 9 (1 bit)
access : read-write
WUTF : Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
bits : 10 - 10 (1 bit)
access : read-write
TSF : Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0.
bits : 11 - 11 (1 bit)
access : read-write
TSOVF : Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared.
bits : 12 - 12 (1 bit)
access : read-write
TAMP1F : RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0
bits : 13 - 13 (1 bit)
access : read-write
TAMP2F : RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0
bits : 14 - 14 (1 bit)
access : read-write
TAMP3F : RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0
bits : 15 - 15 (1 bit)
access : read-write
RECALPF : Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly.
bits : 16 - 16 (1 bit)
access : read-only
ITSF : Internal tTime-stamp flag
bits : 17 - 17 (1 bit)
access : read-write
RTC backup registers
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
RTC backup registers
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKP : The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled.
bits : 0 - 31 (32 bit)
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