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OSCCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :

Registers

INTENCLR

XOSCCTRL

CFDPRESC

EVCTRL

OSC48MCTRL

OSC48MDIV

OSC48MSTUP

OSC48MSYNCBUSY

DPLLCTRLA

DPLLRATIO

DPLLCTRLB

DPLLPRESC

DPLLSYNCBUSY

DPLLSTATUS

CAL48M

INTENSET

INTFLAG

STATUS


INTENCLR

Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSCFAIL OSC48MRDY DPLLLCKR DPLLLCKF DPLLLTO DPLLLDRTO

XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)

XOSCFAIL : XOSC Clock Failure Detector Interrupt Enable
bits : 1 - 1 (1 bit)

OSC48MRDY : OSC48M Ready Interrupt Enable
bits : 4 - 4 (1 bit)

DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 8 - 8 (1 bit)

DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 9 - 9 (1 bit)

DPLLLTO : DPLL Time Out Interrupt Enable
bits : 10 - 10 (1 bit)

DPLLLDRTO : DPLL Ratio Ready Interrupt Enable
bits : 11 - 11 (1 bit)


XOSCCTRL

External Multipurpose Crystal Oscillator (XOSC) Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSCCTRL XOSCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE XTALEN CFDEN SWBEN RUNSTDBY ONDEMAND GAIN AMPGC STARTUP

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)

CFDEN : Xosc Clock Failure Detecteor Enable
bits : 3 - 3 (1 bit)

SWBEN : Xosc Clock Switch Enable
bits : 4 - 4 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

GAIN : Oscillator Gain
bits : 8 - 10 (3 bit)

AMPGC : Automatic Amplitude Gain Control
bits : 11 - 11 (1 bit)

STARTUP : Start-Up Time
bits : 12 - 15 (4 bit)


CFDPRESC

Clock Failure Detector Prescaler
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFDPRESC CFDPRESC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFDPRESC

CFDPRESC : Clock Failure Detector Prescaler
bits : 0 - 2 (3 bit)


EVCTRL

Event Control
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CFDEO

CFDEO : Clock Failure Detector Event Output Enable
bits : 0 - 0 (1 bit)


OSC48MCTRL

48MHz Internal Oscillator (OSC48M) Control
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC48MCTRL OSC48MCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY ONDEMAND

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)


OSC48MDIV

OSC48M Divider
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC48MDIV OSC48MDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIV

DIV : OSC48M Division Factor
bits : 0 - 3 (4 bit)


OSC48MSTUP

OSC48M Startup Time
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC48MSTUP OSC48MSTUP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STARTUP

STARTUP : Startup Time
bits : 0 - 2 (3 bit)


OSC48MSYNCBUSY

OSC48M Synchronization Busy
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSC48MSYNCBUSY OSC48MSYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC48MDIV

OSC48MDIV : OSC48MDIV Synchronization Status
bits : 2 - 2 (1 bit)


DPLLCTRLA

DPLL Control
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRLA DPLLCTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY ONDEMAND

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand
bits : 7 - 7 (1 bit)


DPLLRATIO

DPLL Ratio Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLRATIO DPLLRATIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDR LDRFRAC

LDR : Loop Divider Ratio
bits : 0 - 11 (12 bit)

LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 19 (4 bit)


DPLLCTRLB

Digital Core Configuration
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRLB DPLLCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER LPEN WUF REFCLK LTIME LBYPASS DIV

FILTER : Proportional Integral Filter Selection
bits : 0 - 1 (2 bit)

LPEN : Low-Power Enable
bits : 2 - 2 (1 bit)

WUF : Wake Up Fast
bits : 3 - 3 (1 bit)

REFCLK : Reference Clock Selection
bits : 4 - 5 (2 bit)

LTIME : Lock Time
bits : 8 - 10 (3 bit)

LBYPASS : Lock Bypass
bits : 12 - 12 (1 bit)

DIV : Clock Divider
bits : 16 - 26 (11 bit)


DPLLPRESC

DPLL Prescaler
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLPRESC DPLLPRESC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRESC

PRESC : Output Clock Prescaler
bits : 0 - 1 (2 bit)

Enumeration: PRESCSelect

0x0 : DIV1

DPLL output is divided by 1

0x1 : DIV2

DPLL output is divided by 2

0x2 : DIV4

DPLL output is divided by 4

End of enumeration elements list.


DPLLSYNCBUSY

DPLL Synchronization Busy
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DPLLSYNCBUSY DPLLSYNCBUSY read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE DPLLRATIO DPLLPRESC

ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
access : read-only

DPLLRATIO : DPLL Ratio Synchronization Status
bits : 2 - 2 (1 bit)
access : read-only

DPLLPRESC : DPLL Prescaler Synchronization Status
bits : 3 - 3 (1 bit)
access : read-only


DPLLSTATUS

DPLL Status
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DPLLSTATUS DPLLSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LOCK CLKRDY

LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
access : read-only

CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
access : read-only


CAL48M

48MHz Oscillator Calibration
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL48M CAL48M read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCAL FRANGE TCAL

FCAL : Frequency Calibration (48MHz)
bits : 0 - 5 (6 bit)

FRANGE : Frequency Range (48MHz)
bits : 8 - 9 (2 bit)

TCAL : Temperature Calibration (48MHz)
bits : 16 - 21 (6 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSCFAIL OSC48MRDY DPLLLCKR DPLLLCKF DPLLLTO DPLLLDRTO

XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)

XOSCFAIL : XOSC Clock Failure Detector Interrupt Enable
bits : 1 - 1 (1 bit)

OSC48MRDY : OSC48M Ready Interrupt Enable
bits : 4 - 4 (1 bit)

DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 8 - 8 (1 bit)

DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 9 - 9 (1 bit)

DPLLLTO : DPLL Time Out Interrupt Enable
bits : 10 - 10 (1 bit)

DPLLLDRTO : DPLL Ratio Ready Interrupt Enable
bits : 11 - 11 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSCFAIL OSC48MRDY DPLLLCKR DPLLLCKF DPLLLTO DPLLLDRTO

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)

XOSCFAIL : XOSC Clock Failure Detector
bits : 1 - 1 (1 bit)

OSC48MRDY : OSC48M Ready
bits : 4 - 4 (1 bit)

DPLLLCKR : DPLL Lock Rise
bits : 8 - 8 (1 bit)

DPLLLCKF : DPLL Lock Fall
bits : 9 - 9 (1 bit)

DPLLLTO : DPLL Timeout
bits : 10 - 10 (1 bit)

DPLLLDRTO : DPLL Ratio Ready
bits : 11 - 11 (1 bit)


STATUS

Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSCFAIL XOSCCKSW OSC48MRDY DPLLLCKR DPLLLCKF DPLLTO DPLLLDRTO

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)
access : read-only

XOSCFAIL : XOSC Clock Failure Detector
bits : 1 - 1 (1 bit)
access : read-only

XOSCCKSW : XOSC Clock Switch
bits : 2 - 2 (1 bit)
access : read-only

OSC48MRDY : OSC48M Ready
bits : 4 - 4 (1 bit)
access : read-only

DPLLLCKR : DPLL Lock Rise
bits : 8 - 8 (1 bit)
access : read-only

DPLLLCKF : DPLL Lock Fall
bits : 9 - 9 (1 bit)
access : read-only

DPLLTO : DPLL Timeout
bits : 10 - 10 (1 bit)
access : read-only

DPLLLDRTO : DPLL Ratio Ready
bits : 11 - 11 (1 bit)
access : read-only



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