\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
Interrupt n Status
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x1B7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x1E2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x20E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x23B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x269 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x298 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x2C8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x2F9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x32B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x35E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x392 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x3C7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x3FD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Reset Control
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt n Status
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x434 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x46C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x4A5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x4DF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
External Break Control
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable BRK Pin
bits : 0 - 0 (1 bit)
INV : Invert BRK Pin
bits : 1 - 1 (1 bit)
Interrupt n Status
address_offset : 0x51A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x593 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x5D1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Event Control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEI : Break Input Event Enable
bits : 0 - 0 (1 bit)
BRKEO : Break Output Event Enable
bits : 1 - 1 (1 bit)
Interrupt Trigger
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Trigger Enable
bits : 0 - 0 (1 bit)
IRQNUM : Interrupt Request Number
bits : 1 - 5 (5 bit)
OVERRIDE : Interrupt Request Override Value
bits : 8 - 15 (8 bit)
Interrupt n Status
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt Status for CPU n
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUIRQS : Interrupt Requests for CPU n
bits : 0 - 30 (31 bit)
Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt n Status
address_offset : 0x83 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break
bits : 0 - 0 (1 bit)
Interrupt n Status
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Global Break Requests Mask
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Debug Halt Request
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt Status for CPU n
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUIRQS : Interrupt Requests for CPU n
bits : 0 - 30 (31 bit)
Interrupt n Status
address_offset : 0xCA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Debug Restart Request
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Break Request Status
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Request
bits : 0 - 1 (2 bit)
EVBRK : Event Break Request
bits : 12 - 13 (2 bit)
EXTBRK : External Break Request
bits : 14 - 15 (2 bit)
Interrupt n Status
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
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