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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

IER

SR

IFCR

TXDR

RXDR

CR2

CRCPOLY

TXCRC

RXCRC

UDRDR

CGFR

CFG1

CFG2


CR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPE MASRX CSTART CSUSP HDDIR SSI CRC33_17 RCRCI TCRCI IOLOCK

SPE : Serial Peripheral Enable
bits : 0 - 0 (1 bit)
access : read-write

MASRX : Master automatic SUSP in Receive mode
bits : 8 - 8 (1 bit)
access : read-write

CSTART : Master transfer start
bits : 9 - 9 (1 bit)
access : read-only

CSUSP : Master SUSPend request
bits : 10 - 10 (1 bit)
access : write-only

HDDIR : Rx/Tx direction at Half-duplex mode
bits : 11 - 11 (1 bit)
access : read-write

SSI : Internal SS signal input level
bits : 12 - 12 (1 bit)
access : read-write

CRC33_17 : 32-bit CRC polynomial configuration
bits : 13 - 13 (1 bit)
access : read-write

RCRCI : CRC calculation initialization pattern control for receiver
bits : 14 - 14 (1 bit)
access : read-write

TCRCI : CRC calculation initialization pattern control for transmitter
bits : 15 - 15 (1 bit)
access : read-write

IOLOCK : Locking the AF configuration of associated IOs
bits : 16 - 16 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPIE TXPIE DPXPIE EOTIE TXTFIE UDRIE OVRIE CRCEIE TIFREIE MODFIE TSERFIE

RXPIE : RXP Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

TXPIE : TXP interrupt enable
bits : 1 - 1 (1 bit)
access : read-only

DPXPIE : DXP interrupt enabled
bits : 2 - 2 (1 bit)
access : read-only

EOTIE : EOT, SUSP and TXC interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

TXTFIE : TXTFIE interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

UDRIE : UDR interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

OVRIE : OVR interrupt enable
bits : 6 - 6 (1 bit)
access : read-write

CRCEIE : CRC Interrupt enable
bits : 7 - 7 (1 bit)
access : read-write

TIFREIE : TIFRE interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

MODFIE : Mode Fault interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

TSERFIE : Additional number of transactions reload interrupt enable
bits : 10 - 10 (1 bit)
access : read-write


SR

Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXP TXP DXP EOT TXTF UDR OVR CRCE TIFRE MODF TSERF SUSP TXC RXPLVL RXWNE CTSIZE

RXP : Rx-Packet available
bits : 0 - 0 (1 bit)

TXP : Tx-Packet space available
bits : 1 - 1 (1 bit)

DXP : Duplex Packet
bits : 2 - 2 (1 bit)

EOT : End Of Transfer
bits : 3 - 3 (1 bit)

TXTF : Transmission Transfer Filled
bits : 4 - 4 (1 bit)

UDR : Underrun at slave transmission mode
bits : 5 - 5 (1 bit)

OVR : Overrun
bits : 6 - 6 (1 bit)

CRCE : CRC Error
bits : 7 - 7 (1 bit)

TIFRE : TI frame format error
bits : 8 - 8 (1 bit)

MODF : Mode Fault
bits : 9 - 9 (1 bit)

TSERF : Additional number of SPI data to be transacted was reload
bits : 10 - 10 (1 bit)

SUSP : SUSPend
bits : 11 - 11 (1 bit)

TXC : TxFIFO transmission complete
bits : 12 - 12 (1 bit)

RXPLVL : RxFIFO Packing LeVeL
bits : 13 - 14 (2 bit)

RXWNE : RxFIFO Word Not Empty
bits : 15 - 15 (1 bit)

CTSIZE : Number of data frames remaining in current TSIZE session
bits : 16 - 31 (16 bit)


IFCR

Interrupt/Status Flags Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOTC TXTFC UDRC OVRC CRCEC TIFREC MODFC TSERFC SUSPC

EOTC : End Of Transfer flag clear
bits : 3 - 3 (1 bit)

TXTFC : Transmission Transfer Filled flag clear
bits : 4 - 4 (1 bit)

UDRC : Underrun flag clear
bits : 5 - 5 (1 bit)

OVRC : Overrun flag clear
bits : 6 - 6 (1 bit)

CRCEC : CRC Error flag clear
bits : 7 - 7 (1 bit)

TIFREC : TI frame format error flag clear
bits : 8 - 8 (1 bit)

MODFC : Mode Fault flag clear
bits : 9 - 9 (1 bit)

TSERFC : TSERFC flag clear
bits : 10 - 10 (1 bit)

SUSPC : SUSPend flag clear
bits : 11 - 11 (1 bit)


TXDR

Transmit Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDR TXDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDR

TXDR : Transmit data register
bits : 0 - 31 (32 bit)


RXDR

Receive Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDR RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDR

RXDR : Receive data register
bits : 0 - 31 (32 bit)


CR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSIZE TSER

TSIZE : Number of data at current transfer
bits : 0 - 15 (16 bit)
access : read-write

TSER : Number of data transfer extension to be reload into TSIZE just when a previous
bits : 16 - 31 (16 bit)
access : read-only


CRCPOLY

Polynomial Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCPOLY CRCPOLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCPOLY

CRCPOLY : CRC polynomial register
bits : 0 - 31 (32 bit)


TXCRC

Transmitter CRC Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCRC TXCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCRC

TXCRC : CRC register for transmitter
bits : 0 - 31 (32 bit)


RXCRC

Receiver CRC Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCRC RXCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRC

RXCRC : CRC register for receiver
bits : 0 - 31 (32 bit)


UDRDR

Underrun Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UDRDR UDRDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDRDR

UDRDR : Data at slave underrun condition
bits : 0 - 31 (32 bit)


CGFR

configuration register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGFR CGFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SMOD I2SCFG I2SSTD PCMSYNC DATLEN CHLEN CKPOL FIXCH WSINV DATFMT I2SDIV ODD MCKOE

I2SMOD : I2S mode selection
bits : 0 - 0 (1 bit)

I2SCFG : I2S configuration mode
bits : 1 - 3 (3 bit)

I2SSTD : I2S standard selection
bits : 4 - 5 (2 bit)

PCMSYNC : PCM frame synchronization
bits : 7 - 7 (1 bit)

DATLEN : Data length to be transferred
bits : 8 - 9 (2 bit)

CHLEN : Channel length (number of bits per audio channel)
bits : 10 - 10 (1 bit)

CKPOL : Serial audio clock polarity
bits : 11 - 11 (1 bit)

FIXCH : Word select inversion
bits : 12 - 12 (1 bit)

WSINV : Fixed channel length in SLAVE
bits : 13 - 13 (1 bit)

DATFMT : Data format
bits : 14 - 14 (1 bit)

I2SDIV : I2S linear prescaler
bits : 16 - 23 (8 bit)

ODD : Odd factor for the prescaler
bits : 24 - 24 (1 bit)

MCKOE : Master clock output enable
bits : 25 - 25 (1 bit)


CFG1

configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSIZE FTHVL UDRCFG UDRDET RXDMAEN TXDMAEN CRCSIZE CRCEN MBR

DSIZE : Number of bits in at single SPI data frame
bits : 0 - 4 (5 bit)

FTHVL : threshold level
bits : 5 - 8 (4 bit)

UDRCFG : Behavior of slave transmitter at underrun condition
bits : 9 - 10 (2 bit)

UDRDET : Detection of underrun condition at slave transmitter
bits : 11 - 12 (2 bit)

RXDMAEN : Rx DMA stream enable
bits : 14 - 14 (1 bit)

TXDMAEN : Tx DMA stream enable
bits : 15 - 15 (1 bit)

CRCSIZE : Length of CRC frame to be transacted and compared
bits : 16 - 20 (5 bit)

CRCEN : Hardware CRC computation enable
bits : 22 - 22 (1 bit)

MBR : Master baud rate
bits : 28 - 30 (3 bit)


CFG2

configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSSI MIDI IOSWP COMM SP MASTER LSBFRST CPHA CPOL SSM SSIOP SSOE SSOM AFCNTR

MSSI : Master SS Idleness
bits : 0 - 3 (4 bit)

MIDI : Master Inter-Data Idleness
bits : 4 - 7 (4 bit)

IOSWP : Swap functionality of MISO and MOSI pins
bits : 15 - 15 (1 bit)

COMM : SPI Communication Mode
bits : 17 - 18 (2 bit)

SP : Serial Protocol
bits : 19 - 21 (3 bit)

MASTER : SPI Master
bits : 22 - 22 (1 bit)

LSBFRST : Data frame format
bits : 23 - 23 (1 bit)

CPHA : Clock phase
bits : 24 - 24 (1 bit)

CPOL : Clock polarity
bits : 25 - 25 (1 bit)

SSM : Software management of SS signal input
bits : 26 - 26 (1 bit)

SSIOP : SS input/output polarity
bits : 28 - 28 (1 bit)

SSOE : SS output enable
bits : 29 - 29 (1 bit)

SSOM : SS output management in master mode
bits : 30 - 30 (1 bit)

AFCNTR : Alternate function GPIOs control
bits : 31 - 31 (1 bit)



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