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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

C0CR

C4CR

RG0CR

RG1CR

RG2CR

RG3CR

RG4CR

RG5CR

RG6CR

RG7CR

C5CR

RGSR

RGCFR

C6CR

C7CR

C8CR

C9CR

C10CR

C11CR

C12CR

C13CR

C14CR

C15CR

C1CR

C2CR

CSR

CFR

C3CR


C0CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0CR C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C4CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C4CR C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


RG0CR

DMAMux - DMA request generator channel x control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0CR RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG1CR

DMAMux - DMA request generator channel x control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1CR RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG2CR

DMAMux - DMA request generator channel x control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG2CR RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG3CR

DMAMux - DMA request generator channel x control register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG3CR RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG4CR

DMAMux - DMA request generator channel x control register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG4CR RG4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG5CR

DMAMux - DMA request generator channel x control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG5CR RG5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG6CR

DMAMux - DMA request generator channel x control register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG6CR RG6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


RG7CR

DMAMux - DMA request generator channel x control register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG7CR RG7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


C5CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C5CR C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


RGSR

DMAMux - DMA request generator status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RGSR RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF

OF : Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
bits : 0 - 7 (8 bit)


RGCFR

DMAMux - DMA request generator clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RGCFR RGCFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COF

COF : Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.
bits : 0 - 7 (8 bit)


C6CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C6CR C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C7CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C7CR C7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C8CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C8CR C8CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C9CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C9CR C9CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C10CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C10CR C10CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C11CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C11CR C11CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C12CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C12CR C12CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C13CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C13CR C13CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C14CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C14CR C14CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C15CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C15CR C15CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C1CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1CR C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


C2CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


CSR

DMAMUX request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF

SOF : Synchronization overrun event flag
bits : 0 - 15 (16 bit)


CFR

DMAMUX request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CFR CFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF

CSOF : Clear synchronization overrun event flag
bits : 0 - 15 (16 bit)


C3CR

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C3CR C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)



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