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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CFGR

AHB1LPENR

AHB2LPENR

AHB4LPENR

APB3LPENR

APB1LLPENR

APB1HLPENR

APB2LPENR

APB4LPENR

C1_RSR

C1_AHB3ENR

C1_AHB1ENR

C1_AHB2ENR

C1_AHB4ENR

C1_APB3ENR

C1_APB1LENR

C1_APB1HENR

C1_APB2ENR

C1_APB4ENR

C1_AHB3LPENR

C1_AHB1LPENR

C1_AHB2LPENR

C1_AHB4LPENR

C1_APB3LPENR

C1_APB1LLPENR

C1_APB1HLPENR

C1_APB2LPENR

C1_APB4LPENR

D1CFGR

D2CFGR

D3CFGR

PLLCKSELR

PLLCFGR

PLL1DIVR

PLL1FRACR

PLL2DIVR

PLL2FRACR

ICSCR

PLL3DIVR

PLL3FRACR

D1CCIPR

D2CCIP1R

D2CCIP2R

D3CCIPR

CIER

CIFR

CICR

BDCR

CSR

AHB3RSTR

CRRCR

AHB1RSTR

AHB2RSTR

AHB4RSTR

APB3RSTR

APB1LRSTR

APB1HRSTR

APB2RSTR

APB4RSTR

GCR

D3AMR

RSR

AHB3ENR

AHB1ENR

AHB2ENR

AHB4ENR

APB3ENR

APB1LENR

APB1HENR

APB2ENR

APB4ENR

AHB3LPENR


CR

clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIKERON HSIRDY HSIDIV HSIDIVF CSION CSIRDY CSIKERON RC48ON RC48RDY D1CKRDY D2CKRDY HSEON HSERDY HSEBYP HSECSSON PLL1ON PLL1RDY PLL2ON PLL2RDY PLL3ON PLL3RDY

HSION : Internal high-speed clock enable
bits : 0 - 0 (1 bit)

HSIKERON : High Speed Internal clock enable in Stop mode
bits : 1 - 1 (1 bit)

HSIRDY : HSI clock ready flag
bits : 2 - 2 (1 bit)

HSIDIV : HSI clock divider
bits : 3 - 4 (2 bit)

HSIDIVF : HSI divider flag
bits : 5 - 5 (1 bit)

CSION : CSI clock enable
bits : 7 - 7 (1 bit)

CSIRDY : CSI clock ready flag
bits : 8 - 8 (1 bit)

CSIKERON : CSI clock enable in Stop mode
bits : 9 - 9 (1 bit)

RC48ON : RC48 clock enable
bits : 12 - 12 (1 bit)

RC48RDY : RC48 clock ready flag
bits : 13 - 13 (1 bit)

D1CKRDY : D1 domain clocks ready flag
bits : 14 - 14 (1 bit)

D2CKRDY : D2 domain clocks ready flag
bits : 15 - 15 (1 bit)

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)

HSEBYP : HSE clock bypass
bits : 18 - 18 (1 bit)

HSECSSON : HSE Clock Security System enable
bits : 19 - 19 (1 bit)

PLL1ON : PLL1 enable
bits : 24 - 24 (1 bit)

PLL1RDY : PLL1 clock ready flag
bits : 25 - 25 (1 bit)

PLL2ON : PLL2 enable
bits : 26 - 26 (1 bit)

PLL2RDY : PLL2 clock ready flag
bits : 27 - 27 (1 bit)

PLL3ON : PLL3 enable
bits : 28 - 28 (1 bit)

PLL3RDY : PLL3 clock ready flag
bits : 29 - 29 (1 bit)


CFGR

RCC Clock Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS STOPWUCK STOPKERWUCK RTCPRE HRTIMSEL TIMPRE MCO1PRE MCO1SEL MCO2PRE MCO2SEL

SW : System clock switch
bits : 0 - 2 (3 bit)

SWS : System clock switch status
bits : 3 - 5 (3 bit)

STOPWUCK : System clock selection after a wake up from system Stop
bits : 6 - 6 (1 bit)

STOPKERWUCK : Kernel clock selection after a wake up from system Stop
bits : 7 - 7 (1 bit)

RTCPRE : HSE division factor for RTC clock
bits : 8 - 13 (6 bit)

HRTIMSEL : High Resolution Timer clock prescaler selection
bits : 14 - 14 (1 bit)

TIMPRE : Timers clocks prescaler selection
bits : 15 - 15 (1 bit)

MCO1PRE : MCO1 prescaler
bits : 18 - 21 (4 bit)

MCO1SEL : Micro-controller clock output 1
bits : 22 - 24 (3 bit)

MCO2PRE : MCO2 prescaler
bits : 25 - 28 (4 bit)

MCO2SEL : Micro-controller clock output 2
bits : 29 - 31 (3 bit)


AHB1LPENR

RCC AHB1 Sleep Clock Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1LPENR AHB1LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1LPEN DMA2LPEN ADC12LPEN ETH1MACLPEN ETH1TXLPEN ETH1RXLPEN USB1OTGLPEN USB1ULPILPEN USB2OTGLPEN USB2ULPILPEN

DMA1LPEN : DMA1 Clock Enable During CSleep Mode
bits : 0 - 0 (1 bit)

DMA2LPEN : DMA2 Clock Enable During CSleep Mode
bits : 1 - 1 (1 bit)

ADC12LPEN : ADC1/2 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

ETH1MACLPEN : Ethernet MAC bus interface Clock Enable During CSleep Mode
bits : 15 - 15 (1 bit)

ETH1TXLPEN : Ethernet Transmission Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

ETH1RXLPEN : Ethernet Reception Clock Enable During CSleep Mode
bits : 17 - 17 (1 bit)

USB1OTGLPEN : USB1OTG peripheral clock enable during CSleep mode
bits : 25 - 25 (1 bit)

USB1ULPILPEN : USB_PHY1 clock enable during CSleep mode
bits : 26 - 26 (1 bit)

USB2OTGLPEN : USB2OTG peripheral clock enable during CSleep mode
bits : 27 - 27 (1 bit)

USB2ULPILPEN : USB_PHY2 clocks enable during CSleep mode
bits : 28 - 28 (1 bit)


AHB2LPENR

RCC AHB2 Sleep Clock Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2LPENR AHB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAMITFLPEN CRYPTLPEN HASHLPEN RNGLPEN SDMMC2LPEN SRAM1LPEN SRAM2LPEN SRAM3LPEN

CAMITFLPEN : CAMITF peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

CRYPTLPEN : CRYPT peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

HASHLPEN : HASH peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

RNGLPEN : RNG peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

SDMMC2LPEN : SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
bits : 9 - 9 (1 bit)

SRAM1LPEN : SRAM1 Clock Enable During CSleep Mode
bits : 29 - 29 (1 bit)

SRAM2LPEN : SRAM2 Clock Enable During CSleep Mode
bits : 30 - 30 (1 bit)

SRAM3LPEN : SRAM3 Clock Enable During CSleep Mode
bits : 31 - 31 (1 bit)


AHB4LPENR

RCC AHB4 Sleep Clock Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB4LPENR AHB4LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOALPEN GPIOBLPEN GPIOCLPEN GPIODLPEN GPIOELPEN GPIOFLPEN GPIOGLPEN GPIOHLPEN GPIOILPEN GPIOJLPEN GPIOKLPEN CRCLPEN BDMALPEN ADC3LPEN BKPRAMLPEN SRAM4LPEN

GPIOALPEN : GPIO peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

GPIOBLPEN : GPIO peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

GPIOCLPEN : GPIO peripheral clock enable during CSleep mode
bits : 2 - 2 (1 bit)

GPIODLPEN : GPIO peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

GPIOELPEN : GPIO peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

GPIOFLPEN : GPIO peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

GPIOGLPEN : GPIO peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

GPIOHLPEN : GPIO peripheral clock enable during CSleep mode
bits : 7 - 7 (1 bit)

GPIOILPEN : GPIO peripheral clock enable during CSleep mode
bits : 8 - 8 (1 bit)

GPIOJLPEN : GPIO peripheral clock enable during CSleep mode
bits : 9 - 9 (1 bit)

GPIOKLPEN : GPIO peripheral clock enable during CSleep mode
bits : 10 - 10 (1 bit)

CRCLPEN : CRC peripheral clock enable during CSleep mode
bits : 19 - 19 (1 bit)

BDMALPEN : BDMA Clock Enable During CSleep Mode
bits : 21 - 21 (1 bit)

ADC3LPEN : ADC3 Peripheral Clocks Enable During CSleep Mode
bits : 24 - 24 (1 bit)

BKPRAMLPEN : Backup RAM Clock Enable During CSleep Mode
bits : 28 - 28 (1 bit)

SRAM4LPEN : SRAM4 Clock Enable During CSleep Mode
bits : 29 - 29 (1 bit)


APB3LPENR

RCC APB3 Sleep Clock Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3LPENR APB3LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCLPEN WWDG1LPEN

LTDCLPEN : LTDC peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

WWDG1LPEN : WWDG1 Clock Enable During CSleep Mode
bits : 6 - 6 (1 bit)


APB1LLPENR

RCC APB1 Low Sleep Clock Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LLPENR APB1LLPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2LPEN TIM3LPEN TIM4LPEN TIM5LPEN TIM6LPEN TIM7LPEN TIM12LPEN TIM13LPEN TIM14LPEN LPTIM1LPEN SPI2LPEN SPI3LPEN SPDIFRXLPEN USART2LPEN USART3LPEN UART4LPEN UART5LPEN I2C1LPEN I2C2LPEN I2C3LPEN HDMICECLPEN DAC12LPEN USART7LPEN USART8LPEN

TIM2LPEN : TIM2 peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

TIM3LPEN : TIM3 peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

TIM4LPEN : TIM4 peripheral clock enable during CSleep mode
bits : 2 - 2 (1 bit)

TIM5LPEN : TIM5 peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

TIM6LPEN : TIM6 peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

TIM7LPEN : TIM7 peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

TIM12LPEN : TIM12 peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

TIM13LPEN : TIM13 peripheral clock enable during CSleep mode
bits : 7 - 7 (1 bit)

TIM14LPEN : TIM14 peripheral clock enable during CSleep mode
bits : 8 - 8 (1 bit)

LPTIM1LPEN : LPTIM1 Peripheral Clocks Enable During CSleep Mode
bits : 9 - 9 (1 bit)

SPI2LPEN : SPI2 Peripheral Clocks Enable During CSleep Mode
bits : 14 - 14 (1 bit)

SPI3LPEN : SPI3 Peripheral Clocks Enable During CSleep Mode
bits : 15 - 15 (1 bit)

SPDIFRXLPEN : SPDIFRX Peripheral Clocks Enable During CSleep Mode
bits : 16 - 16 (1 bit)

USART2LPEN : USART2 Peripheral Clocks Enable During CSleep Mode
bits : 17 - 17 (1 bit)

USART3LPEN : USART3 Peripheral Clocks Enable During CSleep Mode
bits : 18 - 18 (1 bit)

UART4LPEN : UART4 Peripheral Clocks Enable During CSleep Mode
bits : 19 - 19 (1 bit)

UART5LPEN : UART5 Peripheral Clocks Enable During CSleep Mode
bits : 20 - 20 (1 bit)

I2C1LPEN : I2C1 Peripheral Clocks Enable During CSleep Mode
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2 Peripheral Clocks Enable During CSleep Mode
bits : 22 - 22 (1 bit)

I2C3LPEN : I2C3 Peripheral Clocks Enable During CSleep Mode
bits : 23 - 23 (1 bit)

HDMICECLPEN : HDMI-CEC Peripheral Clocks Enable During CSleep Mode
bits : 27 - 27 (1 bit)

DAC12LPEN : DAC1/2 peripheral clock enable during CSleep mode
bits : 29 - 29 (1 bit)

USART7LPEN : USART7 Peripheral Clocks Enable During CSleep Mode
bits : 30 - 30 (1 bit)

USART8LPEN : USART8 Peripheral Clocks Enable During CSleep Mode
bits : 31 - 31 (1 bit)


APB1HLPENR

RCC APB1 High Sleep Clock Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1HLPENR APB1HLPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSLPEN SWPLPEN OPAMPLPEN MDIOSLPEN FDCANLPEN

CRSLPEN : Clock Recovery System peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

SWPLPEN : SWPMI Peripheral Clocks Enable During CSleep Mode
bits : 2 - 2 (1 bit)

OPAMPLPEN : OPAMP peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

MDIOSLPEN : MDIOS peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

FDCANLPEN : FDCAN Peripheral Clocks Enable During CSleep Mode
bits : 8 - 8 (1 bit)


APB2LPENR

RCC APB2 Sleep Clock Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2LPENR APB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1LPEN TIM8LPEN USART1LPEN USART6LPEN SPI1LPEN SPI4LPEN TIM15LPEN TIM16LPEN TIM17LPEN SPI5LPEN SAI1LPEN SAI2LPEN SAI3LPEN DFSDM1LPEN HRTIMLPEN

TIM1LPEN : TIM1 peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

TIM8LPEN : TIM8 peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

USART1LPEN : USART1 Peripheral Clocks Enable During CSleep Mode
bits : 4 - 4 (1 bit)

USART6LPEN : USART6 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

SPI1LPEN : SPI1 Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

SPI4LPEN : SPI4 Peripheral Clocks Enable During CSleep Mode
bits : 13 - 13 (1 bit)

TIM15LPEN : TIM15 peripheral clock enable during CSleep mode
bits : 16 - 16 (1 bit)

TIM16LPEN : TIM16 peripheral clock enable during CSleep mode
bits : 17 - 17 (1 bit)

TIM17LPEN : TIM17 peripheral clock enable during CSleep mode
bits : 18 - 18 (1 bit)

SPI5LPEN : SPI5 Peripheral Clocks Enable During CSleep Mode
bits : 20 - 20 (1 bit)

SAI1LPEN : SAI1 Peripheral Clocks Enable During CSleep Mode
bits : 22 - 22 (1 bit)

SAI2LPEN : SAI2 Peripheral Clocks Enable During CSleep Mode
bits : 23 - 23 (1 bit)

SAI3LPEN : SAI3 Peripheral Clocks Enable During CSleep Mode
bits : 24 - 24 (1 bit)

DFSDM1LPEN : DFSDM1 Peripheral Clocks Enable During CSleep Mode
bits : 28 - 28 (1 bit)

HRTIMLPEN : HRTIM peripheral clock enable during CSleep mode
bits : 29 - 29 (1 bit)


APB4LPENR

RCC APB4 Sleep Clock Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4LPENR APB4LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGLPEN LPUART1LPEN SPI6LPEN I2C4LPEN LPTIM2LPEN LPTIM3LPEN LPTIM4LPEN LPTIM5LPEN COMP12LPEN VREFLPEN RTCAPBLPEN SAI4LPEN

SYSCFGLPEN : SYSCFG peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

LPUART1LPEN : LPUART1 Peripheral Clocks Enable During CSleep Mode
bits : 3 - 3 (1 bit)

SPI6LPEN : SPI6 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

I2C4LPEN : I2C4 Peripheral Clocks Enable During CSleep Mode
bits : 7 - 7 (1 bit)

LPTIM2LPEN : LPTIM2 Peripheral Clocks Enable During CSleep Mode
bits : 9 - 9 (1 bit)

LPTIM3LPEN : LPTIM3 Peripheral Clocks Enable During CSleep Mode
bits : 10 - 10 (1 bit)

LPTIM4LPEN : LPTIM4 Peripheral Clocks Enable During CSleep Mode
bits : 11 - 11 (1 bit)

LPTIM5LPEN : LPTIM5 Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

COMP12LPEN : COMP1/2 peripheral clock enable during CSleep mode
bits : 14 - 14 (1 bit)

VREFLPEN : VREF peripheral clock enable during CSleep mode
bits : 15 - 15 (1 bit)

RTCAPBLPEN : RTC APB Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

SAI4LPEN : SAI4 Peripheral Clocks Enable During CSleep Mode
bits : 21 - 21 (1 bit)


C1_RSR

RCC Reset Status Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_RSR C1_RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMVF CPURSTF D1RSTF D2RSTF BORRSTF PINRSTF PORRSTF SFTRSTF IWDG1RSTF WWDG1RSTF LPWRRSTF

RMVF : Remove reset flag
bits : 16 - 16 (1 bit)

CPURSTF : CPU reset flag
bits : 17 - 17 (1 bit)

D1RSTF : D1 domain power switch reset flag
bits : 19 - 19 (1 bit)

D2RSTF : D2 domain power switch reset flag
bits : 20 - 20 (1 bit)

BORRSTF : BOR reset flag
bits : 21 - 21 (1 bit)

PINRSTF : Pin reset flag (NRST)
bits : 22 - 22 (1 bit)

PORRSTF : POR/PDR reset flag
bits : 23 - 23 (1 bit)

SFTRSTF : System reset from CPU reset flag
bits : 24 - 24 (1 bit)

IWDG1RSTF : Independent Watchdog reset flag
bits : 26 - 26 (1 bit)

WWDG1RSTF : Window Watchdog reset flag
bits : 28 - 28 (1 bit)

LPWRRSTF : Reset due to illegal D1 DStandby or CPU CStop flag
bits : 30 - 30 (1 bit)


C1_AHB3ENR

RCC AHB3 Clock Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB3ENR C1_AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMAEN DMA2DEN JPGDECEN FMCEN QSPIEN SDMMC1EN

MDMAEN : MDMA Peripheral Clock Enable
bits : 0 - 0 (1 bit)

DMA2DEN : DMA2D Peripheral Clock Enable
bits : 4 - 4 (1 bit)

JPGDECEN : JPGDEC Peripheral Clock Enable
bits : 5 - 5 (1 bit)

FMCEN : FMC Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

QSPIEN : QUADSPI and QUADSPI Delay Clock Enable
bits : 14 - 14 (1 bit)

SDMMC1EN : SDMMC1 and SDMMC1 Delay Clock Enable
bits : 16 - 16 (1 bit)


C1_AHB1ENR

RCC AHB1 Clock Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB1ENR C1_AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN ADC12EN ETH1MACEN ETH1TXEN ETH1RXEN USB1OTGEN USB1ULPIEN USB2OTGEN USB2ULPIEN

DMA1EN : DMA1 Clock Enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 Clock Enable
bits : 1 - 1 (1 bit)

ADC12EN : ADC1/2 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

ETH1MACEN : Ethernet MAC bus interface Clock Enable
bits : 15 - 15 (1 bit)

ETH1TXEN : Ethernet Transmission Clock Enable
bits : 16 - 16 (1 bit)

ETH1RXEN : Ethernet Reception Clock Enable
bits : 17 - 17 (1 bit)

USB1OTGEN : USB1OTG Peripheral Clocks Enable
bits : 25 - 25 (1 bit)

USB1ULPIEN : USB_PHY1 Clocks Enable
bits : 26 - 26 (1 bit)

USB2OTGEN : USB2OTG Peripheral Clocks Enable
bits : 27 - 27 (1 bit)

USB2ULPIEN : USB_PHY2 Clocks Enable
bits : 28 - 28 (1 bit)


C1_AHB2ENR

RCC AHB2 Clock Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB2ENR C1_AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAMITFEN CRYPTEN HASHEN RNGEN SDMMC2EN SRAM1EN SRAM2EN SRAM3EN

CAMITFEN : CAMITF peripheral clock enable
bits : 0 - 0 (1 bit)

CRYPTEN : CRYPT peripheral clock enable
bits : 4 - 4 (1 bit)

HASHEN : HASH peripheral clock enable
bits : 5 - 5 (1 bit)

RNGEN : RNG peripheral clocks enable
bits : 6 - 6 (1 bit)

SDMMC2EN : SDMMC2 and SDMMC2 delay clock enable
bits : 9 - 9 (1 bit)

SRAM1EN : SRAM1 block enable
bits : 29 - 29 (1 bit)

SRAM2EN : SRAM2 block enable
bits : 30 - 30 (1 bit)

SRAM3EN : SRAM3 block enable
bits : 31 - 31 (1 bit)


C1_AHB4ENR

RCC AHB4 Clock Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB4ENR C1_AHB4ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIODEN GPIOEEN GPIOFEN GPIOGEN GPIOHEN GPIOIEN GPIOJEN GPIOKEN CRCEN BDMAEN ADC3EN HSEMEN BKPRAMEN

GPIOAEN : 0GPIO peripheral clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : 0GPIO peripheral clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : 0GPIO peripheral clock enable
bits : 2 - 2 (1 bit)

GPIODEN : 0GPIO peripheral clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : 0GPIO peripheral clock enable
bits : 4 - 4 (1 bit)

GPIOFEN : 0GPIO peripheral clock enable
bits : 5 - 5 (1 bit)

GPIOGEN : 0GPIO peripheral clock enable
bits : 6 - 6 (1 bit)

GPIOHEN : 0GPIO peripheral clock enable
bits : 7 - 7 (1 bit)

GPIOIEN : 0GPIO peripheral clock enable
bits : 8 - 8 (1 bit)

GPIOJEN : 0GPIO peripheral clock enable
bits : 9 - 9 (1 bit)

GPIOKEN : 0GPIO peripheral clock enable
bits : 10 - 10 (1 bit)

CRCEN : CRC peripheral clock enable
bits : 19 - 19 (1 bit)

BDMAEN : BDMA and DMAMUX2 Clock Enable
bits : 21 - 21 (1 bit)

ADC3EN : ADC3 Peripheral Clocks Enable
bits : 24 - 24 (1 bit)

HSEMEN : HSEM peripheral clock enable
bits : 25 - 25 (1 bit)

BKPRAMEN : Backup RAM Clock Enable
bits : 28 - 28 (1 bit)


C1_APB3ENR

RCC APB3 Clock Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB3ENR C1_APB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCEN WWDG1EN

LTDCEN : LTDC peripheral clock enable
bits : 3 - 3 (1 bit)

WWDG1EN : WWDG1 Clock Enable
bits : 6 - 6 (1 bit)


C1_APB1LENR

RCC APB1 Clock Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB1LENR C1_APB1LENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM4EN TIM5EN TIM6EN TIM7EN TIM12EN TIM13EN TIM14EN LPTIM1EN SPI2EN SPI3EN SPDIFRXEN USART2EN USART3EN UART4EN UART5EN I2C1EN I2C2EN I2C3EN HDMICECEN DAC12EN USART7EN USART8EN

TIM2EN : TIM peripheral clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM peripheral clock enable
bits : 1 - 1 (1 bit)

TIM4EN : TIM peripheral clock enable
bits : 2 - 2 (1 bit)

TIM5EN : TIM peripheral clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM peripheral clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM peripheral clock enable
bits : 5 - 5 (1 bit)

TIM12EN : TIM peripheral clock enable
bits : 6 - 6 (1 bit)

TIM13EN : TIM peripheral clock enable
bits : 7 - 7 (1 bit)

TIM14EN : TIM peripheral clock enable
bits : 8 - 8 (1 bit)

LPTIM1EN : LPTIM1 Peripheral Clocks Enable
bits : 9 - 9 (1 bit)

SPI2EN : SPI2 Peripheral Clocks Enable
bits : 14 - 14 (1 bit)

SPI3EN : SPI3 Peripheral Clocks Enable
bits : 15 - 15 (1 bit)

SPDIFRXEN : SPDIFRX Peripheral Clocks Enable
bits : 16 - 16 (1 bit)

USART2EN : USART2 Peripheral Clocks Enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 Peripheral Clocks Enable
bits : 18 - 18 (1 bit)

UART4EN : UART4 Peripheral Clocks Enable
bits : 19 - 19 (1 bit)

UART5EN : UART5 Peripheral Clocks Enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 Peripheral Clocks Enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 Peripheral Clocks Enable
bits : 22 - 22 (1 bit)

I2C3EN : I2C3 Peripheral Clocks Enable
bits : 23 - 23 (1 bit)

HDMICECEN : HDMI-CEC peripheral clock enable
bits : 27 - 27 (1 bit)

DAC12EN : DAC1&2 peripheral clock enable
bits : 29 - 29 (1 bit)

USART7EN : USART7 Peripheral Clocks Enable
bits : 30 - 30 (1 bit)

USART8EN : USART8 Peripheral Clocks Enable
bits : 31 - 31 (1 bit)


C1_APB1HENR

RCC APB1 Clock Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB1HENR C1_APB1HENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSEN SWPEN OPAMPEN MDIOSEN FDCANEN

CRSEN : Clock Recovery System peripheral clock enable
bits : 1 - 1 (1 bit)

SWPEN : SWPMI Peripheral Clocks Enable
bits : 2 - 2 (1 bit)

OPAMPEN : OPAMP peripheral clock enable
bits : 4 - 4 (1 bit)

MDIOSEN : MDIOS peripheral clock enable
bits : 5 - 5 (1 bit)

FDCANEN : FDCAN Peripheral Clocks Enable
bits : 8 - 8 (1 bit)


C1_APB2ENR

RCC APB2 Clock Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB2ENR C1_APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN TIM8EN USART1EN USART6EN SPI1EN SPI4EN TIM15EN TIM16EN TIM17EN SPI5EN SAI1EN SAI2EN SAI3EN DFSDM1EN HRTIMEN

TIM1EN : TIM1 peripheral clock enable
bits : 0 - 0 (1 bit)

TIM8EN : TIM8 peripheral clock enable
bits : 1 - 1 (1 bit)

USART1EN : USART1 Peripheral Clocks Enable
bits : 4 - 4 (1 bit)

USART6EN : USART6 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

SPI1EN : SPI1 Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

SPI4EN : SPI4 Peripheral Clocks Enable
bits : 13 - 13 (1 bit)

TIM15EN : TIM15 peripheral clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 peripheral clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM17 peripheral clock enable
bits : 18 - 18 (1 bit)

SPI5EN : SPI5 Peripheral Clocks Enable
bits : 20 - 20 (1 bit)

SAI1EN : SAI1 Peripheral Clocks Enable
bits : 22 - 22 (1 bit)

SAI2EN : SAI2 Peripheral Clocks Enable
bits : 23 - 23 (1 bit)

SAI3EN : SAI3 Peripheral Clocks Enable
bits : 24 - 24 (1 bit)

DFSDM1EN : DFSDM1 Peripheral Clocks Enable
bits : 28 - 28 (1 bit)

HRTIMEN : HRTIM peripheral clock enable
bits : 29 - 29 (1 bit)


C1_APB4ENR

RCC APB4 Clock Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB4ENR C1_APB4ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN LPUART1EN SPI6EN I2C4EN LPTIM2EN LPTIM3EN LPTIM4EN LPTIM5EN COMP12EN VREFEN RTCAPBEN SAI4EN

SYSCFGEN : SYSCFG peripheral clock enable
bits : 1 - 1 (1 bit)

LPUART1EN : LPUART1 Peripheral Clocks Enable
bits : 3 - 3 (1 bit)

SPI6EN : SPI6 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

I2C4EN : I2C4 Peripheral Clocks Enable
bits : 7 - 7 (1 bit)

LPTIM2EN : LPTIM2 Peripheral Clocks Enable
bits : 9 - 9 (1 bit)

LPTIM3EN : LPTIM3 Peripheral Clocks Enable
bits : 10 - 10 (1 bit)

LPTIM4EN : LPTIM4 Peripheral Clocks Enable
bits : 11 - 11 (1 bit)

LPTIM5EN : LPTIM5 Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

COMP12EN : COMP1/2 peripheral clock enable
bits : 14 - 14 (1 bit)

VREFEN : VREF peripheral clock enable
bits : 15 - 15 (1 bit)

RTCAPBEN : RTC APB Clock Enable
bits : 16 - 16 (1 bit)

SAI4EN : SAI4 Peripheral Clocks Enable
bits : 21 - 21 (1 bit)


C1_AHB3LPENR

RCC AHB3 Sleep Clock Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB3LPENR C1_AHB3LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMALPEN DMA2DLPEN JPGDECLPEN FLITFLPEN FMCLPEN QSPILPEN SDMMC1LPEN D1DTCM1LPEN DTCM2LPEN ITCMLPEN AXISRAMLPEN

MDMALPEN : MDMA Clock Enable During CSleep Mode
bits : 0 - 0 (1 bit)

DMA2DLPEN : DMA2D Clock Enable During CSleep Mode
bits : 4 - 4 (1 bit)

JPGDECLPEN : JPGDEC Clock Enable During CSleep Mode
bits : 5 - 5 (1 bit)

FLITFLPEN : FLITF Clock Enable During CSleep Mode
bits : 8 - 8 (1 bit)

FMCLPEN : FMC Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

QSPILPEN : QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
bits : 14 - 14 (1 bit)

SDMMC1LPEN : SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

D1DTCM1LPEN : D1DTCM1 Block Clock Enable During CSleep mode
bits : 28 - 28 (1 bit)

DTCM2LPEN : D1 DTCM2 Block Clock Enable During CSleep mode
bits : 29 - 29 (1 bit)

ITCMLPEN : D1ITCM Block Clock Enable During CSleep mode
bits : 30 - 30 (1 bit)

AXISRAMLPEN : AXISRAM Block Clock Enable During CSleep mode
bits : 31 - 31 (1 bit)


C1_AHB1LPENR

RCC AHB1 Sleep Clock Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB1LPENR C1_AHB1LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1LPEN DMA2LPEN ADC12LPEN ETH1MACLPEN ETH1TXLPEN ETH1RXLPEN USB1OTGLPEN USB1ULPILPEN USB2OTGLPEN USB2ULPILPEN

DMA1LPEN : DMA1 Clock Enable During CSleep Mode
bits : 0 - 0 (1 bit)

DMA2LPEN : DMA2 Clock Enable During CSleep Mode
bits : 1 - 1 (1 bit)

ADC12LPEN : ADC1/2 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

ETH1MACLPEN : Ethernet MAC bus interface Clock Enable During CSleep Mode
bits : 15 - 15 (1 bit)

ETH1TXLPEN : Ethernet Transmission Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

ETH1RXLPEN : Ethernet Reception Clock Enable During CSleep Mode
bits : 17 - 17 (1 bit)

USB1OTGLPEN : USB1OTG peripheral clock enable during CSleep mode
bits : 25 - 25 (1 bit)

USB1ULPILPEN : USB_PHY1 clock enable during CSleep mode
bits : 26 - 26 (1 bit)

USB2OTGLPEN : USB2OTG peripheral clock enable during CSleep mode
bits : 27 - 27 (1 bit)

USB2ULPILPEN : USB_PHY2 clocks enable during CSleep mode
bits : 28 - 28 (1 bit)


C1_AHB2LPENR

RCC AHB2 Sleep Clock Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB2LPENR C1_AHB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAMITFLPEN CRYPTLPEN HASHLPEN RNGLPEN SDMMC2LPEN SRAM1LPEN SRAM2LPEN SRAM3LPEN

CAMITFLPEN : CAMITF peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

CRYPTLPEN : CRYPT peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

HASHLPEN : HASH peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

RNGLPEN : RNG peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

SDMMC2LPEN : SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
bits : 9 - 9 (1 bit)

SRAM1LPEN : SRAM1 Clock Enable During CSleep Mode
bits : 29 - 29 (1 bit)

SRAM2LPEN : SRAM2 Clock Enable During CSleep Mode
bits : 30 - 30 (1 bit)

SRAM3LPEN : SRAM3 Clock Enable During CSleep Mode
bits : 31 - 31 (1 bit)


C1_AHB4LPENR

RCC AHB4 Sleep Clock Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_AHB4LPENR C1_AHB4LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOALPEN GPIOBLPEN GPIOCLPEN GPIODLPEN GPIOELPEN GPIOFLPEN GPIOGLPEN GPIOHLPEN GPIOILPEN GPIOJLPEN GPIOKLPEN CRCLPEN BDMALPEN ADC3LPEN BKPRAMLPEN SRAM4LPEN

GPIOALPEN : GPIO peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

GPIOBLPEN : GPIO peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

GPIOCLPEN : GPIO peripheral clock enable during CSleep mode
bits : 2 - 2 (1 bit)

GPIODLPEN : GPIO peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

GPIOELPEN : GPIO peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

GPIOFLPEN : GPIO peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

GPIOGLPEN : GPIO peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

GPIOHLPEN : GPIO peripheral clock enable during CSleep mode
bits : 7 - 7 (1 bit)

GPIOILPEN : GPIO peripheral clock enable during CSleep mode
bits : 8 - 8 (1 bit)

GPIOJLPEN : GPIO peripheral clock enable during CSleep mode
bits : 9 - 9 (1 bit)

GPIOKLPEN : GPIO peripheral clock enable during CSleep mode
bits : 10 - 10 (1 bit)

CRCLPEN : CRC peripheral clock enable during CSleep mode
bits : 19 - 19 (1 bit)

BDMALPEN : BDMA Clock Enable During CSleep Mode
bits : 21 - 21 (1 bit)

ADC3LPEN : ADC3 Peripheral Clocks Enable During CSleep Mode
bits : 24 - 24 (1 bit)

BKPRAMLPEN : Backup RAM Clock Enable During CSleep Mode
bits : 28 - 28 (1 bit)

SRAM4LPEN : SRAM4 Clock Enable During CSleep Mode
bits : 29 - 29 (1 bit)


C1_APB3LPENR

RCC APB3 Sleep Clock Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB3LPENR C1_APB3LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCLPEN WWDG1LPEN

LTDCLPEN : LTDC peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

WWDG1LPEN : WWDG1 Clock Enable During CSleep Mode
bits : 6 - 6 (1 bit)


C1_APB1LLPENR

RCC APB1 Low Sleep Clock Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB1LLPENR C1_APB1LLPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2LPEN TIM3LPEN TIM4LPEN TIM5LPEN TIM6LPEN TIM7LPEN TIM12LPEN TIM13LPEN TIM14LPEN LPTIM1LPEN SPI2LPEN SPI3LPEN SPDIFRXLPEN USART2LPEN USART3LPEN UART4LPEN UART5LPEN I2C1LPEN I2C2LPEN I2C3LPEN HDMICECLPEN DAC12LPEN USART7LPEN USART8LPEN

TIM2LPEN : TIM2 peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

TIM3LPEN : TIM3 peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

TIM4LPEN : TIM4 peripheral clock enable during CSleep mode
bits : 2 - 2 (1 bit)

TIM5LPEN : TIM5 peripheral clock enable during CSleep mode
bits : 3 - 3 (1 bit)

TIM6LPEN : TIM6 peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

TIM7LPEN : TIM7 peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

TIM12LPEN : TIM12 peripheral clock enable during CSleep mode
bits : 6 - 6 (1 bit)

TIM13LPEN : TIM13 peripheral clock enable during CSleep mode
bits : 7 - 7 (1 bit)

TIM14LPEN : TIM14 peripheral clock enable during CSleep mode
bits : 8 - 8 (1 bit)

LPTIM1LPEN : LPTIM1 Peripheral Clocks Enable During CSleep Mode
bits : 9 - 9 (1 bit)

SPI2LPEN : SPI2 Peripheral Clocks Enable During CSleep Mode
bits : 14 - 14 (1 bit)

SPI3LPEN : SPI3 Peripheral Clocks Enable During CSleep Mode
bits : 15 - 15 (1 bit)

SPDIFRXLPEN : SPDIFRX Peripheral Clocks Enable During CSleep Mode
bits : 16 - 16 (1 bit)

USART2LPEN : USART2 Peripheral Clocks Enable During CSleep Mode
bits : 17 - 17 (1 bit)

USART3LPEN : USART3 Peripheral Clocks Enable During CSleep Mode
bits : 18 - 18 (1 bit)

UART4LPEN : UART4 Peripheral Clocks Enable During CSleep Mode
bits : 19 - 19 (1 bit)

UART5LPEN : UART5 Peripheral Clocks Enable During CSleep Mode
bits : 20 - 20 (1 bit)

I2C1LPEN : I2C1 Peripheral Clocks Enable During CSleep Mode
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2 Peripheral Clocks Enable During CSleep Mode
bits : 22 - 22 (1 bit)

I2C3LPEN : I2C3 Peripheral Clocks Enable During CSleep Mode
bits : 23 - 23 (1 bit)

HDMICECLPEN : HDMI-CEC Peripheral Clocks Enable During CSleep Mode
bits : 27 - 27 (1 bit)

DAC12LPEN : DAC1/2 peripheral clock enable during CSleep mode
bits : 29 - 29 (1 bit)

USART7LPEN : USART7 Peripheral Clocks Enable During CSleep Mode
bits : 30 - 30 (1 bit)

USART8LPEN : USART8 Peripheral Clocks Enable During CSleep Mode
bits : 31 - 31 (1 bit)


C1_APB1HLPENR

RCC APB1 High Sleep Clock Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB1HLPENR C1_APB1HLPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSLPEN SWPLPEN OPAMPLPEN MDIOSLPEN FDCANLPEN

CRSLPEN : Clock Recovery System peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

SWPLPEN : SWPMI Peripheral Clocks Enable During CSleep Mode
bits : 2 - 2 (1 bit)

OPAMPLPEN : OPAMP peripheral clock enable during CSleep mode
bits : 4 - 4 (1 bit)

MDIOSLPEN : MDIOS peripheral clock enable during CSleep mode
bits : 5 - 5 (1 bit)

FDCANLPEN : FDCAN Peripheral Clocks Enable During CSleep Mode
bits : 8 - 8 (1 bit)


C1_APB2LPENR

RCC APB2 Sleep Clock Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB2LPENR C1_APB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1LPEN TIM8LPEN USART1LPEN USART6LPEN SPI1LPEN SPI4LPEN TIM15LPEN TIM16LPEN TIM17LPEN SPI5LPEN SAI1LPEN SAI2LPEN SAI3LPEN DFSDM1LPEN HRTIMLPEN

TIM1LPEN : TIM1 peripheral clock enable during CSleep mode
bits : 0 - 0 (1 bit)

TIM8LPEN : TIM8 peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

USART1LPEN : USART1 Peripheral Clocks Enable During CSleep Mode
bits : 4 - 4 (1 bit)

USART6LPEN : USART6 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

SPI1LPEN : SPI1 Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

SPI4LPEN : SPI4 Peripheral Clocks Enable During CSleep Mode
bits : 13 - 13 (1 bit)

TIM15LPEN : TIM15 peripheral clock enable during CSleep mode
bits : 16 - 16 (1 bit)

TIM16LPEN : TIM16 peripheral clock enable during CSleep mode
bits : 17 - 17 (1 bit)

TIM17LPEN : TIM17 peripheral clock enable during CSleep mode
bits : 18 - 18 (1 bit)

SPI5LPEN : SPI5 Peripheral Clocks Enable During CSleep Mode
bits : 20 - 20 (1 bit)

SAI1LPEN : SAI1 Peripheral Clocks Enable During CSleep Mode
bits : 22 - 22 (1 bit)

SAI2LPEN : SAI2 Peripheral Clocks Enable During CSleep Mode
bits : 23 - 23 (1 bit)

SAI3LPEN : SAI3 Peripheral Clocks Enable During CSleep Mode
bits : 24 - 24 (1 bit)

DFSDM1LPEN : DFSDM1 Peripheral Clocks Enable During CSleep Mode
bits : 28 - 28 (1 bit)

HRTIMLPEN : HRTIM peripheral clock enable during CSleep mode
bits : 29 - 29 (1 bit)


C1_APB4LPENR

RCC APB4 Sleep Clock Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1_APB4LPENR C1_APB4LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGLPEN LPUART1LPEN SPI6LPEN I2C4LPEN LPTIM2LPEN LPTIM3LPEN LPTIM4LPEN LPTIM5LPEN COMP12LPEN VREFLPEN RTCAPBLPEN SAI4LPEN

SYSCFGLPEN : SYSCFG peripheral clock enable during CSleep mode
bits : 1 - 1 (1 bit)

LPUART1LPEN : LPUART1 Peripheral Clocks Enable During CSleep Mode
bits : 3 - 3 (1 bit)

SPI6LPEN : SPI6 Peripheral Clocks Enable During CSleep Mode
bits : 5 - 5 (1 bit)

I2C4LPEN : I2C4 Peripheral Clocks Enable During CSleep Mode
bits : 7 - 7 (1 bit)

LPTIM2LPEN : LPTIM2 Peripheral Clocks Enable During CSleep Mode
bits : 9 - 9 (1 bit)

LPTIM3LPEN : LPTIM3 Peripheral Clocks Enable During CSleep Mode
bits : 10 - 10 (1 bit)

LPTIM4LPEN : LPTIM4 Peripheral Clocks Enable During CSleep Mode
bits : 11 - 11 (1 bit)

LPTIM5LPEN : LPTIM5 Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

COMP12LPEN : COMP1/2 peripheral clock enable during CSleep mode
bits : 14 - 14 (1 bit)

VREFLPEN : VREF peripheral clock enable during CSleep mode
bits : 15 - 15 (1 bit)

RTCAPBLPEN : RTC APB Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

SAI4LPEN : SAI4 Peripheral Clocks Enable During CSleep Mode
bits : 21 - 21 (1 bit)


D1CFGR

RCC Domain 1 Clock Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1CFGR D1CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPRE D1PPRE D1CPRE

HPRE : D1 domain AHB prescaler
bits : 0 - 3 (4 bit)

D1PPRE : D1 domain APB3 prescaler
bits : 4 - 6 (3 bit)

D1CPRE : D1 domain Core prescaler
bits : 8 - 11 (4 bit)


D2CFGR

RCC Domain 2 Clock Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D2CFGR D2CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D2PPRE1 D2PPRE2

D2PPRE1 : D2 domain APB1 prescaler
bits : 4 - 6 (3 bit)

D2PPRE2 : D2 domain APB2 prescaler
bits : 8 - 10 (3 bit)


D3CFGR

RCC Domain 3 Clock Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D3CFGR D3CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3PPRE

D3PPRE : D3 domain APB4 prescaler
bits : 4 - 6 (3 bit)


PLLCKSELR

RCC PLLs Clock Source Selection Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCKSELR PLLCKSELR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLSRC DIVM1 DIVM2 DIVM3

PLLSRC : DIVMx and PLLs clock source selection
bits : 0 - 1 (2 bit)

DIVM1 : Prescaler for PLL1
bits : 4 - 9 (6 bit)

DIVM2 : Prescaler for PLL2
bits : 12 - 17 (6 bit)

DIVM3 : Prescaler for PLL3
bits : 20 - 25 (6 bit)


PLLCFGR

RCC PLLs Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFGR PLLCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL1FRACEN PLL1VCOSEL PLL1RGE PLL2FRACEN PLL2VCOSEL PLL2RGE PLL3FRACEN PLL3VCOSEL PLL3RGE DIVP1EN DIVQ1EN DIVR1EN DIVP2EN DIVQ2EN DIVR2EN DIVP3EN DIVQ3EN DIVR3EN

PLL1FRACEN : PLL1 fractional latch enable
bits : 0 - 0 (1 bit)

PLL1VCOSEL : PLL1 VCO selection
bits : 1 - 1 (1 bit)

PLL1RGE : PLL1 input frequency range
bits : 2 - 3 (2 bit)

PLL2FRACEN : PLL2 fractional latch enable
bits : 4 - 4 (1 bit)

PLL2VCOSEL : PLL2 VCO selection
bits : 5 - 5 (1 bit)

PLL2RGE : PLL2 input frequency range
bits : 6 - 7 (2 bit)

PLL3FRACEN : PLL3 fractional latch enable
bits : 8 - 8 (1 bit)

PLL3VCOSEL : PLL3 VCO selection
bits : 9 - 9 (1 bit)

PLL3RGE : PLL3 input frequency range
bits : 10 - 11 (2 bit)

DIVP1EN : PLL1 DIVP divider output enable
bits : 16 - 16 (1 bit)

DIVQ1EN : PLL1 DIVQ divider output enable
bits : 17 - 17 (1 bit)

DIVR1EN : PLL1 DIVR divider output enable
bits : 18 - 18 (1 bit)

DIVP2EN : PLL2 DIVP divider output enable
bits : 19 - 19 (1 bit)

DIVQ2EN : PLL2 DIVQ divider output enable
bits : 20 - 20 (1 bit)

DIVR2EN : PLL2 DIVR divider output enable
bits : 21 - 21 (1 bit)

DIVP3EN : PLL3 DIVP divider output enable
bits : 22 - 22 (1 bit)

DIVQ3EN : PLL3 DIVQ divider output enable
bits : 23 - 23 (1 bit)

DIVR3EN : PLL3 DIVR divider output enable
bits : 24 - 24 (1 bit)


PLL1DIVR

RCC PLL1 Dividers Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL1DIVR PLL1DIVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN1 DIVP1 DIVQ1 DIVR1

DIVN1 : Multiplication factor for PLL1 VCO
bits : 0 - 8 (9 bit)

DIVP1 : PLL1 DIVP division factor
bits : 9 - 15 (7 bit)

DIVQ1 : PLL1 DIVQ division factor
bits : 16 - 22 (7 bit)

DIVR1 : PLL1 DIVR division factor
bits : 24 - 30 (7 bit)


PLL1FRACR

RCC PLL1 Fractional Divider Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL1FRACR PLL1FRACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACN1

FRACN1 : Fractional part of the multiplication factor for PLL1 VCO
bits : 3 - 15 (13 bit)


PLL2DIVR

RCC PLL2 Dividers Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL2DIVR PLL2DIVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN1 DIVP1 DIVQ1 DIVR1

DIVN1 : Multiplication factor for PLL1 VCO
bits : 0 - 8 (9 bit)

DIVP1 : PLL1 DIVP division factor
bits : 9 - 15 (7 bit)

DIVQ1 : PLL1 DIVQ division factor
bits : 16 - 22 (7 bit)

DIVR1 : PLL1 DIVR division factor
bits : 24 - 30 (7 bit)


PLL2FRACR

RCC PLL2 Fractional Divider Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL2FRACR PLL2FRACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACN2

FRACN2 : Fractional part of the multiplication factor for PLL VCO
bits : 3 - 15 (13 bit)


ICSCR

RCC Internal Clock Source Calibration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSICAL HSITRIM CSICAL CSITRIM

HSICAL : HSI clock calibration
bits : 0 - 11 (12 bit)
access : read-only

HSITRIM : HSI clock trimming
bits : 12 - 17 (6 bit)
access : read-write

CSICAL : CSI clock calibration
bits : 18 - 25 (8 bit)
access : read-only

CSITRIM : CSI clock trimming
bits : 26 - 30 (5 bit)
access : read-write


PLL3DIVR

RCC PLL3 Dividers Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL3DIVR PLL3DIVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVN3 DIVP3 DIVQ3 DIVR3

DIVN3 : Multiplication factor for PLL1 VCO
bits : 0 - 8 (9 bit)

DIVP3 : PLL DIVP division factor
bits : 9 - 15 (7 bit)

DIVQ3 : PLL DIVQ division factor
bits : 16 - 22 (7 bit)

DIVR3 : PLL DIVR division factor
bits : 24 - 30 (7 bit)


PLL3FRACR

RCC PLL3 Fractional Divider Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL3FRACR PLL3FRACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACN3

FRACN3 : Fractional part of the multiplication factor for PLL3 VCO
bits : 3 - 15 (13 bit)


D1CCIPR

RCC Domain 1 Kernel Clock Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1CCIPR D1CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMCSRC QSPISRC SDMMCSRC CKPERSRC

FMCSRC : FMC kernel clock source selection
bits : 0 - 1 (2 bit)

QSPISRC : QUADSPI kernel clock source selection
bits : 4 - 5 (2 bit)

SDMMCSRC : SDMMC kernel clock source selection
bits : 16 - 16 (1 bit)

CKPERSRC : per_ck clock source selection
bits : 28 - 29 (2 bit)


D2CCIP1R

RCC Domain 2 Kernel Clock Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D2CCIP1R D2CCIP1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAI1SRC SAI23SRC SPI123SRC SPI45SRC SPDIFSRC DFSDM1SRC FDCANSRC SWPSRC

SAI1SRC : SAI1 and DFSDM1 kernel Aclk clock source selection
bits : 0 - 2 (3 bit)

SAI23SRC : SAI2 and SAI3 kernel clock source selection
bits : 6 - 8 (3 bit)

SPI123SRC : SPI/I2S1,2 and 3 kernel clock source selection
bits : 12 - 14 (3 bit)

SPI45SRC : SPI4 and 5 kernel clock source selection
bits : 16 - 18 (3 bit)

SPDIFSRC : SPDIFRX kernel clock source selection
bits : 20 - 21 (2 bit)

DFSDM1SRC : DFSDM1 kernel Clk clock source selection
bits : 24 - 24 (1 bit)

FDCANSRC : FDCAN kernel clock source selection
bits : 28 - 29 (2 bit)

SWPSRC : SWPMI kernel clock source selection
bits : 31 - 31 (1 bit)


D2CCIP2R

RCC Domain 2 Kernel Clock Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D2CCIP2R D2CCIP2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART234578SRC USART16SRC RNGSRC I2C123SRC USBSRC CECSRC LPTIM1SRC

USART234578SRC : USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection
bits : 0 - 2 (3 bit)

USART16SRC : USART1 and 6 kernel clock source selection
bits : 3 - 5 (3 bit)

RNGSRC : RNG kernel clock source selection
bits : 8 - 9 (2 bit)

I2C123SRC : I2C1,2,3 kernel clock source selection
bits : 12 - 13 (2 bit)

USBSRC : USBOTG 1 and 2 kernel clock source selection
bits : 20 - 21 (2 bit)

CECSRC : HDMI-CEC kernel clock source selection
bits : 22 - 23 (2 bit)

LPTIM1SRC : LPTIM1 kernel clock source selection
bits : 28 - 30 (3 bit)


D3CCIPR

RCC Domain 3 Kernel Clock Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D3CCIPR D3CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1SRC I2C4SRC LPTIM2SRC LPTIM345SRC ADCSRC SAI4ASRC SAI4BSRC SPI6SRC

LPUART1SRC : LPUART1 kernel clock source selection
bits : 0 - 2 (3 bit)

I2C4SRC : I2C4 kernel clock source selection
bits : 8 - 9 (2 bit)

LPTIM2SRC : LPTIM2 kernel clock source selection
bits : 10 - 12 (3 bit)

LPTIM345SRC : LPTIM3,4,5 kernel clock source selection
bits : 13 - 15 (3 bit)

ADCSRC : SAR ADC kernel clock source selection
bits : 16 - 17 (2 bit)

SAI4ASRC : Sub-Block A of SAI4 kernel clock source selection
bits : 21 - 23 (3 bit)

SAI4BSRC : Sub-Block B of SAI4 kernel clock source selection
bits : 24 - 26 (3 bit)

SPI6SRC : SPI6 kernel clock source selection
bits : 28 - 30 (3 bit)


CIER

RCC Clock Source Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE CSIRDYIE RC48RDYIE PLL1RDYIE PLL2RDYIE PLL3RDYIE LSECSSIE

LSIRDYIE : LSI ready Interrupt Enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready Interrupt Enable
bits : 1 - 1 (1 bit)

HSIRDYIE : HSI ready Interrupt Enable
bits : 2 - 2 (1 bit)

HSERDYIE : HSE ready Interrupt Enable
bits : 3 - 3 (1 bit)

CSIRDYIE : CSI ready Interrupt Enable
bits : 4 - 4 (1 bit)

RC48RDYIE : RC48 ready Interrupt Enable
bits : 5 - 5 (1 bit)

PLL1RDYIE : PLL1 ready Interrupt Enable
bits : 6 - 6 (1 bit)

PLL2RDYIE : PLL2 ready Interrupt Enable
bits : 7 - 7 (1 bit)

PLL3RDYIE : PLL3 ready Interrupt Enable
bits : 8 - 8 (1 bit)

LSECSSIE : LSE clock security system Interrupt Enable
bits : 9 - 9 (1 bit)


CIFR

RCC Clock Source Interrupt Flag Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF CSIRDY RC48RDYF PLL1RDYF PLL2RDYF PLL3RDYF LSECSSF HSECSSF

LSIRDYF : LSI ready Interrupt Flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready Interrupt Flag
bits : 1 - 1 (1 bit)

HSIRDYF : HSI ready Interrupt Flag
bits : 2 - 2 (1 bit)

HSERDYF : HSE ready Interrupt Flag
bits : 3 - 3 (1 bit)

CSIRDY : CSI ready Interrupt Flag
bits : 4 - 4 (1 bit)

RC48RDYF : RC48 ready Interrupt Flag
bits : 5 - 5 (1 bit)

PLL1RDYF : PLL1 ready Interrupt Flag
bits : 6 - 6 (1 bit)

PLL2RDYF : PLL2 ready Interrupt Flag
bits : 7 - 7 (1 bit)

PLL3RDYF : PLL3 ready Interrupt Flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE clock security system Interrupt Flag
bits : 9 - 9 (1 bit)

HSECSSF : HSE clock security system Interrupt Flag
bits : 10 - 10 (1 bit)


CICR

RCC Clock Source Interrupt Clear Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CICR CICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYC LSERDYC HSIRDYC HSERDYC HSE_ready_Interrupt_Clear RC48RDYC PLL1RDYC PLL2RDYC PLL3RDYC LSECSSC HSECSSC

LSIRDYC : LSI ready Interrupt Clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready Interrupt Clear
bits : 1 - 1 (1 bit)

HSIRDYC : HSI ready Interrupt Clear
bits : 2 - 2 (1 bit)

HSERDYC : HSE ready Interrupt Clear
bits : 3 - 3 (1 bit)

HSE_ready_Interrupt_Clear : CSI ready Interrupt Clear
bits : 4 - 4 (1 bit)

RC48RDYC : RC48 ready Interrupt Clear
bits : 5 - 5 (1 bit)

PLL1RDYC : PLL1 ready Interrupt Clear
bits : 6 - 6 (1 bit)

PLL2RDYC : PLL2 ready Interrupt Clear
bits : 7 - 7 (1 bit)

PLL3RDYC : PLL3 ready Interrupt Clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE clock security system Interrupt Clear
bits : 9 - 9 (1 bit)

HSECSSC : HSE clock security system Interrupt Clear
bits : 10 - 10 (1 bit)


BDCR

RCC Backup Domain Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV LSECSSON LSECSSD RTCSRC RTCEN VSWRST

LSEON : LSE oscillator enabled
bits : 0 - 0 (1 bit)

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)

LSEDRV : LSE oscillator driving capability
bits : 3 - 4 (2 bit)

LSECSSON : LSE clock security system enable
bits : 5 - 5 (1 bit)

LSECSSD : LSE clock security system failure detection
bits : 6 - 6 (1 bit)

RTCSRC : RTC clock source selection
bits : 8 - 9 (2 bit)

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)

VSWRST : VSwitch domain software reset
bits : 16 - 16 (1 bit)


CSR

RCC Clock Control and Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY

LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)

LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)


AHB3RSTR

RCC AHB3 Reset Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3RSTR AHB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMARST DMA2DRST JPGDECRST FMCRST QSPIRST SDMMC1RST CPURST

MDMARST : MDMA block reset
bits : 0 - 0 (1 bit)

DMA2DRST : DMA2D block reset
bits : 4 - 4 (1 bit)

JPGDECRST : JPGDEC block reset
bits : 5 - 5 (1 bit)

FMCRST : FMC block reset
bits : 12 - 12 (1 bit)

QSPIRST : QUADSPI and QUADSPI delay block reset
bits : 14 - 14 (1 bit)

SDMMC1RST : SDMMC1 and SDMMC1 delay block reset
bits : 16 - 16 (1 bit)

CPURST : CPU reset
bits : 31 - 31 (1 bit)


CRRCR

RCC Clock Recovery RC Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRRCR CRRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC48CAL

RC48CAL : Internal RC 48 MHz clock calibration
bits : 0 - 9 (10 bit)


AHB1RSTR

RCC AHB1 Peripheral Reset Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RSTR AHB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1RST DMA2RST ADC12RST ETH1MACRST USB1OTGRST USB2OTGRST

DMA1RST : DMA1 block reset
bits : 0 - 0 (1 bit)

DMA2RST : DMA2 block reset
bits : 1 - 1 (1 bit)

ADC12RST : ADC1&2 block reset
bits : 5 - 5 (1 bit)

ETH1MACRST : ETH1MAC block reset
bits : 15 - 15 (1 bit)

USB1OTGRST : USB1OTG block reset
bits : 25 - 25 (1 bit)

USB2OTGRST : USB2OTG block reset
bits : 27 - 27 (1 bit)


AHB2RSTR

RCC AHB2 Peripheral Reset Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2RSTR AHB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAMITFRST CRYPTRST HASHRST RNGRST SDMMC2RST

CAMITFRST : CAMITF block reset
bits : 0 - 0 (1 bit)

CRYPTRST : Cryptography block reset
bits : 4 - 4 (1 bit)

HASHRST : Hash block reset
bits : 5 - 5 (1 bit)

RNGRST : Random Number Generator block reset
bits : 6 - 6 (1 bit)

SDMMC2RST : SDMMC2 and SDMMC2 Delay block reset
bits : 9 - 9 (1 bit)


AHB4RSTR

RCC AHB4 Peripheral Reset Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB4RSTR AHB4RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIODRST GPIOERST GPIOFRST GPIOGRST GPIOHRST GPIOIRST GPIOJRST GPIOKRST CRCRST BDMARST ADC3RST HSEMRST

GPIOARST : GPIO block reset
bits : 0 - 0 (1 bit)

GPIOBRST : GPIO block reset
bits : 1 - 1 (1 bit)

GPIOCRST : GPIO block reset
bits : 2 - 2 (1 bit)

GPIODRST : GPIO block reset
bits : 3 - 3 (1 bit)

GPIOERST : GPIO block reset
bits : 4 - 4 (1 bit)

GPIOFRST : GPIO block reset
bits : 5 - 5 (1 bit)

GPIOGRST : GPIO block reset
bits : 6 - 6 (1 bit)

GPIOHRST : GPIO block reset
bits : 7 - 7 (1 bit)

GPIOIRST : GPIO block reset
bits : 8 - 8 (1 bit)

GPIOJRST : GPIO block reset
bits : 9 - 9 (1 bit)

GPIOKRST : GPIO block reset
bits : 10 - 10 (1 bit)

CRCRST : CRC block reset
bits : 19 - 19 (1 bit)

BDMARST : BDMA block reset
bits : 21 - 21 (1 bit)

ADC3RST : ADC3 block reset
bits : 24 - 24 (1 bit)

HSEMRST : HSEM block reset
bits : 25 - 25 (1 bit)


APB3RSTR

RCC APB3 Peripheral Reset Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3RSTR APB3RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCRST

LTDCRST : LTDC block reset
bits : 3 - 3 (1 bit)


APB1LRSTR

RCC APB1 Peripheral Reset Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LRSTR APB1LRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM4RST TIM5RST TIM6RST TIM7RST TIM12RST TIM13RST TIM14RST LPTIM1RST SPI2RST SPI3RST SPDIFRXRST USART2RST USART3RST UART4RST UART5RST I2C1RST I2C2RST I2C3RST HDMICECRST DAC12RST USART7RST USART8RST

TIM2RST : TIM block reset
bits : 0 - 0 (1 bit)

TIM3RST : TIM block reset
bits : 1 - 1 (1 bit)

TIM4RST : TIM block reset
bits : 2 - 2 (1 bit)

TIM5RST : TIM block reset
bits : 3 - 3 (1 bit)

TIM6RST : TIM block reset
bits : 4 - 4 (1 bit)

TIM7RST : TIM block reset
bits : 5 - 5 (1 bit)

TIM12RST : TIM block reset
bits : 6 - 6 (1 bit)

TIM13RST : TIM block reset
bits : 7 - 7 (1 bit)

TIM14RST : TIM block reset
bits : 8 - 8 (1 bit)

LPTIM1RST : TIM block reset
bits : 9 - 9 (1 bit)

SPI2RST : SPI2 block reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI3 block reset
bits : 15 - 15 (1 bit)

SPDIFRXRST : SPDIFRX block reset
bits : 16 - 16 (1 bit)

USART2RST : USART2 block reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 block reset
bits : 18 - 18 (1 bit)

UART4RST : UART4 block reset
bits : 19 - 19 (1 bit)

UART5RST : UART5 block reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C1 block reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 block reset
bits : 22 - 22 (1 bit)

I2C3RST : I2C3 block reset
bits : 23 - 23 (1 bit)

HDMICECRST : HDMI-CEC block reset
bits : 27 - 27 (1 bit)

DAC12RST : DAC1 and 2 Blocks Reset
bits : 29 - 29 (1 bit)

USART7RST : USART7 block reset
bits : 30 - 30 (1 bit)

USART8RST : USART8 block reset
bits : 31 - 31 (1 bit)


APB1HRSTR

RCC APB1 Peripheral Reset Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1HRSTR APB1HRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSRST SWPRST OPAMPRST MDIOSRST FDCANRST

CRSRST : Clock Recovery System reset
bits : 1 - 1 (1 bit)

SWPRST : SWPMI block reset
bits : 2 - 2 (1 bit)

OPAMPRST : OPAMP block reset
bits : 4 - 4 (1 bit)

MDIOSRST : MDIOS block reset
bits : 5 - 5 (1 bit)

FDCANRST : FDCAN block reset
bits : 8 - 8 (1 bit)


APB2RSTR

RCC APB2 Peripheral Reset Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1RST TIM8RST USART1RST USART6RST SPI1RST SPI4RST TIM15RST TIM16RST TIM17RST SPI5RST SAI1RST SAI2RST SAI3RST DFSDM1RST HRTIMRST

TIM1RST : TIM1 block reset
bits : 0 - 0 (1 bit)

TIM8RST : TIM8 block reset
bits : 1 - 1 (1 bit)

USART1RST : USART1 block reset
bits : 4 - 4 (1 bit)

USART6RST : USART6 block reset
bits : 5 - 5 (1 bit)

SPI1RST : SPI1 block reset
bits : 12 - 12 (1 bit)

SPI4RST : SPI4 block reset
bits : 13 - 13 (1 bit)

TIM15RST : TIM15 block reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 block reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 block reset
bits : 18 - 18 (1 bit)

SPI5RST : SPI5 block reset
bits : 20 - 20 (1 bit)

SAI1RST : SAI1 block reset
bits : 22 - 22 (1 bit)

SAI2RST : SAI2 block reset
bits : 23 - 23 (1 bit)

SAI3RST : SAI3 block reset
bits : 24 - 24 (1 bit)

DFSDM1RST : DFSDM1 block reset
bits : 28 - 28 (1 bit)

HRTIMRST : HRTIM block reset
bits : 29 - 29 (1 bit)


APB4RSTR

RCC APB4 Peripheral Reset Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4RSTR APB4RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST LPUART1RST SPI6RST I2C4RST LPTIM2RST LPTIM3RST LPTIM4RST LPTIM5RST COMP12RST VREFRST SAI4RST

SYSCFGRST : SYSCFG block reset
bits : 1 - 1 (1 bit)

LPUART1RST : LPUART1 block reset
bits : 3 - 3 (1 bit)

SPI6RST : SPI6 block reset
bits : 5 - 5 (1 bit)

I2C4RST : I2C4 block reset
bits : 7 - 7 (1 bit)

LPTIM2RST : LPTIM2 block reset
bits : 9 - 9 (1 bit)

LPTIM3RST : LPTIM3 block reset
bits : 10 - 10 (1 bit)

LPTIM4RST : LPTIM4 block reset
bits : 11 - 11 (1 bit)

LPTIM5RST : LPTIM5 block reset
bits : 12 - 12 (1 bit)

COMP12RST : COMP12 Blocks Reset
bits : 14 - 14 (1 bit)

VREFRST : VREF block reset
bits : 15 - 15 (1 bit)

SAI4RST : SAI4 block reset
bits : 21 - 21 (1 bit)


GCR

RCC Global Control Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCR GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WW1RSC

WW1RSC : WWDG1 reset scope control
bits : 0 - 0 (1 bit)


D3AMR

RCC D3 Autonomous mode Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D3AMR D3AMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDMAAMEN LPUART1AMEN SPI6AMEN I2C4AMEN LPTIM2AMEN LPTIM3AMEN LPTIM4AMEN LPTIM5AMEN COMP12AMEN VREFAMEN RTCAMEN CRCAMEN SAI4AMEN ADC3AMEN BKPSRAMAMEN SRAM4AMEN

BDMAAMEN : BDMA and DMAMUX Autonomous mode enable
bits : 0 - 0 (1 bit)

LPUART1AMEN : LPUART1 Autonomous mode enable
bits : 3 - 3 (1 bit)

SPI6AMEN : SPI6 Autonomous mode enable
bits : 5 - 5 (1 bit)

I2C4AMEN : I2C4 Autonomous mode enable
bits : 7 - 7 (1 bit)

LPTIM2AMEN : LPTIM2 Autonomous mode enable
bits : 9 - 9 (1 bit)

LPTIM3AMEN : LPTIM3 Autonomous mode enable
bits : 10 - 10 (1 bit)

LPTIM4AMEN : LPTIM4 Autonomous mode enable
bits : 11 - 11 (1 bit)

LPTIM5AMEN : LPTIM5 Autonomous mode enable
bits : 12 - 12 (1 bit)

COMP12AMEN : COMP12 Autonomous mode enable
bits : 14 - 14 (1 bit)

VREFAMEN : VREF Autonomous mode enable
bits : 15 - 15 (1 bit)

RTCAMEN : RTC Autonomous mode enable
bits : 16 - 16 (1 bit)

CRCAMEN : CRC Autonomous mode enable
bits : 19 - 19 (1 bit)

SAI4AMEN : SAI4 Autonomous mode enable
bits : 21 - 21 (1 bit)

ADC3AMEN : ADC3 Autonomous mode enable
bits : 24 - 24 (1 bit)

BKPSRAMAMEN : Backup RAM Autonomous mode enable
bits : 28 - 28 (1 bit)

SRAM4AMEN : SRAM4 Autonomous mode enable
bits : 29 - 29 (1 bit)


RSR

RCC Reset Status Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSR RSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMVF CPURSTF D1RSTF D2RSTF BORRSTF PINRSTF PORRSTF SFTRSTF IWDG1RSTF WWDG1RSTF LPWRRSTF

RMVF : Remove reset flag
bits : 16 - 16 (1 bit)

CPURSTF : CPU reset flag
bits : 17 - 17 (1 bit)

D1RSTF : D1 domain power switch reset flag
bits : 19 - 19 (1 bit)

D2RSTF : D2 domain power switch reset flag
bits : 20 - 20 (1 bit)

BORRSTF : BOR reset flag
bits : 21 - 21 (1 bit)

PINRSTF : Pin reset flag (NRST)
bits : 22 - 22 (1 bit)

PORRSTF : POR/PDR reset flag
bits : 23 - 23 (1 bit)

SFTRSTF : System reset from CPU reset flag
bits : 24 - 24 (1 bit)

IWDG1RSTF : Independent Watchdog reset flag
bits : 26 - 26 (1 bit)

WWDG1RSTF : Window Watchdog reset flag
bits : 28 - 28 (1 bit)

LPWRRSTF : Reset due to illegal D1 DStandby or CPU CStop flag
bits : 30 - 30 (1 bit)


AHB3ENR

RCC AHB3 Clock Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3ENR AHB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMAEN DMA2DEN JPGDECEN FMCEN QSPIEN SDMMC1EN

MDMAEN : MDMA Peripheral Clock Enable
bits : 0 - 0 (1 bit)

DMA2DEN : DMA2D Peripheral Clock Enable
bits : 4 - 4 (1 bit)

JPGDECEN : JPGDEC Peripheral Clock Enable
bits : 5 - 5 (1 bit)

FMCEN : FMC Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

QSPIEN : QUADSPI and QUADSPI Delay Clock Enable
bits : 14 - 14 (1 bit)

SDMMC1EN : SDMMC1 and SDMMC1 Delay Clock Enable
bits : 16 - 16 (1 bit)


AHB1ENR

RCC AHB1 Clock Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1ENR AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN DMA2EN ADC12EN ETH1MACEN ETH1TXEN ETH1RXEN USB1OTGEN USB1ULPIEN USB2OTGEN USB2ULPIEN

DMA1EN : DMA1 Clock Enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 Clock Enable
bits : 1 - 1 (1 bit)

ADC12EN : ADC1/2 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

ETH1MACEN : Ethernet MAC bus interface Clock Enable
bits : 15 - 15 (1 bit)

ETH1TXEN : Ethernet Transmission Clock Enable
bits : 16 - 16 (1 bit)

ETH1RXEN : Ethernet Reception Clock Enable
bits : 17 - 17 (1 bit)

USB1OTGEN : USB1OTG Peripheral Clocks Enable
bits : 25 - 25 (1 bit)

USB1ULPIEN : USB_PHY1 Clocks Enable
bits : 26 - 26 (1 bit)

USB2OTGEN : USB2OTG Peripheral Clocks Enable
bits : 27 - 27 (1 bit)

USB2ULPIEN : USB_PHY2 Clocks Enable
bits : 28 - 28 (1 bit)


AHB2ENR

RCC AHB2 Clock Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB2ENR AHB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAMITFEN CRYPTEN HASHEN RNGEN SDMMC2EN SRAM1EN SRAM2EN SRAM3EN

CAMITFEN : CAMITF peripheral clock enable
bits : 0 - 0 (1 bit)

CRYPTEN : CRYPT peripheral clock enable
bits : 4 - 4 (1 bit)

HASHEN : HASH peripheral clock enable
bits : 5 - 5 (1 bit)

RNGEN : RNG peripheral clocks enable
bits : 6 - 6 (1 bit)

SDMMC2EN : SDMMC2 and SDMMC2 delay clock enable
bits : 9 - 9 (1 bit)

SRAM1EN : SRAM1 block enable
bits : 29 - 29 (1 bit)

SRAM2EN : SRAM2 block enable
bits : 30 - 30 (1 bit)

SRAM3EN : SRAM3 block enable
bits : 31 - 31 (1 bit)


AHB4ENR

RCC AHB4 Clock Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB4ENR AHB4ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIODEN GPIOEEN GPIOFEN GPIOGEN GPIOHEN GPIOIEN GPIOJEN GPIOKEN CRCEN BDMAEN ADC3EN HSEMEN BKPRAMEN

GPIOAEN : 0GPIO peripheral clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : 0GPIO peripheral clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : 0GPIO peripheral clock enable
bits : 2 - 2 (1 bit)

GPIODEN : 0GPIO peripheral clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : 0GPIO peripheral clock enable
bits : 4 - 4 (1 bit)

GPIOFEN : 0GPIO peripheral clock enable
bits : 5 - 5 (1 bit)

GPIOGEN : 0GPIO peripheral clock enable
bits : 6 - 6 (1 bit)

GPIOHEN : 0GPIO peripheral clock enable
bits : 7 - 7 (1 bit)

GPIOIEN : 0GPIO peripheral clock enable
bits : 8 - 8 (1 bit)

GPIOJEN : 0GPIO peripheral clock enable
bits : 9 - 9 (1 bit)

GPIOKEN : 0GPIO peripheral clock enable
bits : 10 - 10 (1 bit)

CRCEN : CRC peripheral clock enable
bits : 19 - 19 (1 bit)

BDMAEN : BDMA and DMAMUX2 Clock Enable
bits : 21 - 21 (1 bit)

ADC3EN : ADC3 Peripheral Clocks Enable
bits : 24 - 24 (1 bit)

HSEMEN : HSEM peripheral clock enable
bits : 25 - 25 (1 bit)

BKPRAMEN : Backup RAM Clock Enable
bits : 28 - 28 (1 bit)


APB3ENR

RCC APB3 Clock Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB3ENR APB3ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCEN WWDG1EN

LTDCEN : LTDC peripheral clock enable
bits : 3 - 3 (1 bit)

WWDG1EN : WWDG1 Clock Enable
bits : 6 - 6 (1 bit)


APB1LENR

RCC APB1 Clock Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LENR APB1LENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM4EN TIM5EN TIM6EN TIM7EN TIM12EN TIM13EN TIM14EN LPTIM1EN SPI2EN SPI3EN SPDIFRXEN USART2EN USART3EN UART4EN UART5EN I2C1EN I2C2EN I2C3EN HDMICECEN DAC12EN USART7EN USART8EN

TIM2EN : TIM peripheral clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM peripheral clock enable
bits : 1 - 1 (1 bit)

TIM4EN : TIM peripheral clock enable
bits : 2 - 2 (1 bit)

TIM5EN : TIM peripheral clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM peripheral clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM peripheral clock enable
bits : 5 - 5 (1 bit)

TIM12EN : TIM peripheral clock enable
bits : 6 - 6 (1 bit)

TIM13EN : TIM peripheral clock enable
bits : 7 - 7 (1 bit)

TIM14EN : TIM peripheral clock enable
bits : 8 - 8 (1 bit)

LPTIM1EN : LPTIM1 Peripheral Clocks Enable
bits : 9 - 9 (1 bit)

SPI2EN : SPI2 Peripheral Clocks Enable
bits : 14 - 14 (1 bit)

SPI3EN : SPI3 Peripheral Clocks Enable
bits : 15 - 15 (1 bit)

SPDIFRXEN : SPDIFRX Peripheral Clocks Enable
bits : 16 - 16 (1 bit)

USART2EN : USART2 Peripheral Clocks Enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 Peripheral Clocks Enable
bits : 18 - 18 (1 bit)

UART4EN : UART4 Peripheral Clocks Enable
bits : 19 - 19 (1 bit)

UART5EN : UART5 Peripheral Clocks Enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 Peripheral Clocks Enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 Peripheral Clocks Enable
bits : 22 - 22 (1 bit)

I2C3EN : I2C3 Peripheral Clocks Enable
bits : 23 - 23 (1 bit)

HDMICECEN : HDMI-CEC peripheral clock enable
bits : 27 - 27 (1 bit)

DAC12EN : DAC1&2 peripheral clock enable
bits : 29 - 29 (1 bit)

USART7EN : USART7 Peripheral Clocks Enable
bits : 30 - 30 (1 bit)

USART8EN : USART8 Peripheral Clocks Enable
bits : 31 - 31 (1 bit)


APB1HENR

RCC APB1 Clock Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1HENR APB1HENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSEN SWPEN OPAMPEN MDIOSEN FDCANEN

CRSEN : Clock Recovery System peripheral clock enable
bits : 1 - 1 (1 bit)

SWPEN : SWPMI Peripheral Clocks Enable
bits : 2 - 2 (1 bit)

OPAMPEN : OPAMP peripheral clock enable
bits : 4 - 4 (1 bit)

MDIOSEN : MDIOS peripheral clock enable
bits : 5 - 5 (1 bit)

FDCANEN : FDCAN Peripheral Clocks Enable
bits : 8 - 8 (1 bit)


APB2ENR

RCC APB2 Clock Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN TIM8EN USART1EN USART6EN SPI1EN SPI4EN TIM15EN TIM16EN TIM17EN SPI5EN SAI1EN SAI2EN SAI3EN DFSDM1EN HRTIMEN

TIM1EN : TIM1 peripheral clock enable
bits : 0 - 0 (1 bit)

TIM8EN : TIM8 peripheral clock enable
bits : 1 - 1 (1 bit)

USART1EN : USART1 Peripheral Clocks Enable
bits : 4 - 4 (1 bit)

USART6EN : USART6 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

SPI1EN : SPI1 Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

SPI4EN : SPI4 Peripheral Clocks Enable
bits : 13 - 13 (1 bit)

TIM15EN : TIM15 peripheral clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 peripheral clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM17 peripheral clock enable
bits : 18 - 18 (1 bit)

SPI5EN : SPI5 Peripheral Clocks Enable
bits : 20 - 20 (1 bit)

SAI1EN : SAI1 Peripheral Clocks Enable
bits : 22 - 22 (1 bit)

SAI2EN : SAI2 Peripheral Clocks Enable
bits : 23 - 23 (1 bit)

SAI3EN : SAI3 Peripheral Clocks Enable
bits : 24 - 24 (1 bit)

DFSDM1EN : DFSDM1 Peripheral Clocks Enable
bits : 28 - 28 (1 bit)

HRTIMEN : HRTIM peripheral clock enable
bits : 29 - 29 (1 bit)


APB4ENR

RCC APB4 Clock Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB4ENR APB4ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN LPUART1EN SPI6EN I2C4EN LPTIM2EN LPTIM3EN LPTIM4EN LPTIM5EN COMP12EN VREFEN RTCAPBEN SAI4EN

SYSCFGEN : SYSCFG peripheral clock enable
bits : 1 - 1 (1 bit)

LPUART1EN : LPUART1 Peripheral Clocks Enable
bits : 3 - 3 (1 bit)

SPI6EN : SPI6 Peripheral Clocks Enable
bits : 5 - 5 (1 bit)

I2C4EN : I2C4 Peripheral Clocks Enable
bits : 7 - 7 (1 bit)

LPTIM2EN : LPTIM2 Peripheral Clocks Enable
bits : 9 - 9 (1 bit)

LPTIM3EN : LPTIM3 Peripheral Clocks Enable
bits : 10 - 10 (1 bit)

LPTIM4EN : LPTIM4 Peripheral Clocks Enable
bits : 11 - 11 (1 bit)

LPTIM5EN : LPTIM5 Peripheral Clocks Enable
bits : 12 - 12 (1 bit)

COMP12EN : COMP1/2 peripheral clock enable
bits : 14 - 14 (1 bit)

VREFEN : VREF peripheral clock enable
bits : 15 - 15 (1 bit)

RTCAPBEN : RTC APB Clock Enable
bits : 16 - 16 (1 bit)

SAI4EN : SAI4 Peripheral Clocks Enable
bits : 21 - 21 (1 bit)


AHB3LPENR

RCC AHB3 Sleep Clock Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB3LPENR AHB3LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDMALPEN DMA2DLPEN JPGDECLPEN FLITFLPEN FMCLPEN QSPILPEN SDMMC1LPEN D1DTCM1LPEN DTCM2LPEN ITCMLPEN AXISRAMLPEN

MDMALPEN : MDMA Clock Enable During CSleep Mode
bits : 0 - 0 (1 bit)

DMA2DLPEN : DMA2D Clock Enable During CSleep Mode
bits : 4 - 4 (1 bit)

JPGDECLPEN : JPGDEC Clock Enable During CSleep Mode
bits : 5 - 5 (1 bit)

FLITFLPEN : FLITF Clock Enable During CSleep Mode
bits : 8 - 8 (1 bit)

FMCLPEN : FMC Peripheral Clocks Enable During CSleep Mode
bits : 12 - 12 (1 bit)

QSPILPEN : QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
bits : 14 - 14 (1 bit)

SDMMC1LPEN : SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
bits : 16 - 16 (1 bit)

D1DTCM1LPEN : D1DTCM1 Block Clock Enable During CSleep mode
bits : 28 - 28 (1 bit)

DTCM2LPEN : D1 DTCM2 Block Clock Enable During CSleep mode
bits : 29 - 29 (1 bit)

ITCMLPEN : D1ITCM Block Clock Enable During CSleep mode
bits : 30 - 30 (1 bit)

AXISRAMLPEN : AXISRAM Block Clock Enable During CSleep mode
bits : 31 - 31 (1 bit)



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