\n

MCLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

INTENCLR

AHBMASK

APBAMASK

APBBMASK

APBCMASK

INTENSET

INTFLAG

CPUDIV


INTENCLR

Interrupt Enable Clear
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)


AHBMASK

AHB Mask
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBMASK AHBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPB0_ HPB1_ HPB2_ DSU_ HMATRIXHS_ NVMCTRL_ HSRAM_ DMAC_ CAN0_ PAC_ NVMCTRL_PICACHU_ DIVAS_

HPB0_ : HPB0 AHB Clock Mask
bits : 0 - 0 (1 bit)

HPB1_ : HPB1 AHB Clock Mask
bits : 1 - 1 (1 bit)

HPB2_ : HPB2 AHB Clock Mask
bits : 2 - 2 (1 bit)

DSU_ : DSU AHB Clock Mask
bits : 3 - 3 (1 bit)

HMATRIXHS_ : HMATRIXHS AHB Clock Mask
bits : 4 - 4 (1 bit)

NVMCTRL_ : NVMCTRL AHB Clock Mask
bits : 5 - 5 (1 bit)

HSRAM_ : HSRAM AHB Clock Mask
bits : 6 - 6 (1 bit)

DMAC_ : DMAC AHB Clock Mask
bits : 7 - 7 (1 bit)

CAN0_ : CAN0 AHB Clock Mask
bits : 8 - 8 (1 bit)

PAC_ : PAC AHB Clock Mask
bits : 10 - 10 (1 bit)

NVMCTRL_PICACHU_ : NVMCTRL_PICACHU AHB Clock Mask
bits : 11 - 11 (1 bit)

DIVAS_ : DIVAS AHB Clock Mask
bits : 12 - 12 (1 bit)


APBAMASK

APBA Mask
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBAMASK APBAMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC_ PM_ MCLK_ RSTC_ OSCCTRL_ OSC32KCTRL_ SUPC_ GCLK_ WDT_ RTC_ EIC_ FREQM_ TSENS_

PAC_ : PAC APB Clock Enable
bits : 0 - 0 (1 bit)

PM_ : PM APB Clock Enable
bits : 1 - 1 (1 bit)

MCLK_ : MCLK APB Clock Enable
bits : 2 - 2 (1 bit)

RSTC_ : RSTC APB Clock Enable
bits : 3 - 3 (1 bit)

OSCCTRL_ : OSCCTRL APB Clock Enable
bits : 4 - 4 (1 bit)

OSC32KCTRL_ : OSC32KCTRL APB Clock Enable
bits : 5 - 5 (1 bit)

SUPC_ : SUPC APB Clock Enable
bits : 6 - 6 (1 bit)

GCLK_ : GCLK APB Clock Enable
bits : 7 - 7 (1 bit)

WDT_ : WDT APB Clock Enable
bits : 8 - 8 (1 bit)

RTC_ : RTC APB Clock Enable
bits : 9 - 9 (1 bit)

EIC_ : EIC APB Clock Enable
bits : 10 - 10 (1 bit)

FREQM_ : FREQM APB Clock Enable
bits : 11 - 11 (1 bit)

TSENS_ : TSENS APB Clock Enable
bits : 12 - 12 (1 bit)


APBBMASK

APBB Mask
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBBMASK APBBMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ DSU_ NVMCTRL_ HMATRIXHS_

PORT_ : PORT APB Clock Enable
bits : 0 - 0 (1 bit)

DSU_ : DSU APB Clock Enable
bits : 1 - 1 (1 bit)

NVMCTRL_ : NVMCTRL APB Clock Enable
bits : 2 - 2 (1 bit)

HMATRIXHS_ : HMATRIXHS APB Clock Enable
bits : 5 - 5 (1 bit)


APBCMASK

APBC Mask
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCMASK APBCMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVSYS_ SERCOM0_ SERCOM1_ SERCOM2_ SERCOM3_ TCC0_ TCC1_ TCC2_ TC0_ TC1_ TC2_ TC3_ TC4_ ADC0_ ADC1_ SDADC_ AC_ DAC_ PTC_ CCL_ TAL_

EVSYS_ : EVSYS APB Clock Enable
bits : 0 - 0 (1 bit)

SERCOM0_ : SERCOM0 APB Clock Enable
bits : 1 - 1 (1 bit)

SERCOM1_ : SERCOM1 APB Clock Enable
bits : 2 - 2 (1 bit)

SERCOM2_ : SERCOM2 APB Clock Enable
bits : 3 - 3 (1 bit)

SERCOM3_ : SERCOM3 APB Clock Enable
bits : 4 - 4 (1 bit)

TCC0_ : TCC0 APB Clock Enable
bits : 9 - 9 (1 bit)

TCC1_ : TCC1 APB Clock Enable
bits : 10 - 10 (1 bit)

TCC2_ : TCC2 APB Clock Enable
bits : 11 - 11 (1 bit)

TC0_ : TC0 APB Clock Enable
bits : 12 - 12 (1 bit)

TC1_ : TC1 APB Clock Enable
bits : 13 - 13 (1 bit)

TC2_ : TC2 APB Clock Enable
bits : 14 - 14 (1 bit)

TC3_ : TC3 APB Clock Enable
bits : 15 - 15 (1 bit)

TC4_ : TC4 APB Clock Enable
bits : 16 - 16 (1 bit)

ADC0_ : ADC0 APB Clock Enable
bits : 17 - 17 (1 bit)

ADC1_ : ADC1 APB Clock Enable
bits : 18 - 18 (1 bit)

SDADC_ : SDADC APB Clock Enable
bits : 19 - 19 (1 bit)

AC_ : AC APB Clock Enable
bits : 20 - 20 (1 bit)

DAC_ : DAC APB Clock Enable
bits : 21 - 21 (1 bit)

PTC_ : PTC APB Clock Enable
bits : 22 - 22 (1 bit)

CCL_ : CCL APB Clock Enable
bits : 23 - 23 (1 bit)

TAL_ : TAL APB Clock Enable
bits : 24 - 24 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKRDY

CKRDY : Clock Ready
bits : 0 - 0 (1 bit)


CPUDIV

CPU Clock Division
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUDIV CPUDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CPUDIV

CPUDIV : CPU Clock Division Factor
bits : 0 - 7 (8 bit)

Enumeration: CPUDIVSelect

0x1 : DIV1

Divide by 1

0x2 : DIV2

Divide by 2

0x4 : DIV4

Divide by 4

0x8 : DIV8

Divide by 8

0x10 : DIV16

Divide by 16

0x20 : DIV32

Divide by 32

0x40 : DIV64

Divide by 64

0x80 : DIV128

Divide by 128

End of enumeration elements list.



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