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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EXTICR3

PKGR

EXTICR4

CCCSR

CCVR

CCCR

UR0

UR2

UR3

UR4

UR5

UR6

UR7

UR8

UR9

UR10

UR11

UR12

UR13

UR14

UR15

UR16

UR17

PMCR

EXTICR1

EXTICR2


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI x configuration (x = 8 to 11)
bits : 0 - 3 (4 bit)

EXTI9 : EXTI x configuration (x = 8 to 11)
bits : 4 - 7 (4 bit)

EXTI10 : EXTI10
bits : 8 - 11 (4 bit)

EXTI11 : EXTI x configuration (x = 8 to 11)
bits : 12 - 15 (4 bit)


PKGR

SYSCFG package register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKGR PKGR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKG

PKG : Package
bits : 0 - 3 (4 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI x configuration (x = 12 to 15)
bits : 0 - 3 (4 bit)

EXTI13 : EXTI x configuration (x = 12 to 15)
bits : 4 - 7 (4 bit)

EXTI14 : EXTI x configuration (x = 12 to 15)
bits : 8 - 11 (4 bit)

EXTI15 : EXTI x configuration (x = 12 to 15)
bits : 12 - 15 (4 bit)


CCCSR

compensation cell control/status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCCSR CCCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN CS READY HSLV

EN : enable
bits : 0 - 0 (1 bit)

CS : Code selection
bits : 1 - 1 (1 bit)

READY : Compensation cell ready flag
bits : 8 - 8 (1 bit)

HSLV : High-speed at low-voltage
bits : 16 - 16 (1 bit)


CCVR

SYSCFG compensation cell value register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCVR CCVR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCV PCV

NCV : NMOS compensation value
bits : 0 - 3 (4 bit)

PCV : PMOS compensation value
bits : 4 - 7 (4 bit)


CCCR

SYSCFG compensation cell code register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCCR CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NCC PCC

NCC : NMOS compensation code
bits : 0 - 3 (4 bit)

PCC : PMOS compensation code
bits : 4 - 7 (4 bit)


UR0

SYSCFG user register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR0 UR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKS RDP

BKS : Bank Swap
bits : 0 - 0 (1 bit)

RDP : Readout protection
bits : 16 - 23 (8 bit)


UR2

SYSCFG user register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR2 UR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BORH BOOT_ADD0

BORH : BOR_LVL Brownout Reset Threshold Level
bits : 0 - 1 (2 bit)

BOOT_ADD0 : Boot Address 0
bits : 16 - 31 (16 bit)


UR3

SYSCFG user register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR3 UR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT_ADD1

BOOT_ADD1 : Boot Address 1
bits : 16 - 31 (16 bit)


UR4

SYSCFG user register 4
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR4 UR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEPAD_1

MEPAD_1 : Mass Erase Protected Area Disabled for bank 1
bits : 16 - 16 (1 bit)


UR5

SYSCFG user register 5
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR5 UR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESAD_1 WRPN_1

MESAD_1 : Mass erase secured area disabled for bank 1
bits : 0 - 0 (1 bit)

WRPN_1 : Write protection for flash bank 1
bits : 16 - 23 (8 bit)


UR6

SYSCFG user register 6
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR6 UR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_BEG_1 PA_END_1

PA_BEG_1 : Protected area start address for bank 1
bits : 0 - 11 (12 bit)

PA_END_1 : Protected area end address for bank 1
bits : 16 - 27 (12 bit)


UR7

SYSCFG user register 7
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR7 UR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA_BEG_1 SA_END_1

SA_BEG_1 : Secured area start address for bank 1
bits : 0 - 11 (12 bit)

SA_END_1 : Secured area end address for bank 1
bits : 16 - 27 (12 bit)


UR8

SYSCFG user register 8
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR8 UR8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEPAD_2 MESAD_2

MEPAD_2 : Mass erase protected area disabled for bank 2
bits : 0 - 0 (1 bit)

MESAD_2 : Mass erase secured area disabled for bank 2
bits : 16 - 16 (1 bit)


UR9

SYSCFG user register 9
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR9 UR9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRPN_2 PA_BEG_2

WRPN_2 : Write protection for flash bank 2
bits : 0 - 7 (8 bit)

PA_BEG_2 : Protected area start address for bank 2
bits : 16 - 27 (12 bit)


UR10

SYSCFG user register 10
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR10 UR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_END_2 SA_BEG_2

PA_END_2 : Protected area end address for bank 2
bits : 0 - 11 (12 bit)

SA_BEG_2 : Secured area start address for bank 2
bits : 16 - 27 (12 bit)


UR11

SYSCFG user register 11
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR11 UR11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA_END_2 IWDG1M

SA_END_2 : Secured area end address for bank 2
bits : 0 - 11 (12 bit)

IWDG1M : Independent Watchdog 1 mode
bits : 16 - 16 (1 bit)


UR12

SYSCFG user register 12
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR12 UR12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECURE

SECURE : Secure mode
bits : 16 - 16 (1 bit)


UR13

SYSCFG user register 13
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR13 UR13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDRS D1SBRST

SDRS : Secured DTCM RAM Size
bits : 0 - 1 (2 bit)

D1SBRST : D1 Standby reset
bits : 16 - 16 (1 bit)


UR14

SYSCFG user register 14
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UR14 UR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1STPRST

D1STPRST : D1 Stop Reset
bits : 0 - 0 (1 bit)


UR15

SYSCFG user register 15
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR15 UR15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FZIWDGSTB

FZIWDGSTB : Freeze independent watchdog in Standby mode
bits : 16 - 16 (1 bit)


UR16

SYSCFG user register 16
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR16 UR16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FZIWDGSTP PKP

FZIWDGSTP : Freeze independent watchdog in Stop mode
bits : 0 - 0 (1 bit)

PKP : Private key programmed
bits : 16 - 16 (1 bit)


UR17

SYSCFG user register 17
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

UR17 UR17 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IO_HSLV

IO_HSLV : I/O high speed / low voltage
bits : 0 - 0 (1 bit)


PMCR

peripheral mode configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMCR PMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C1FMP I2C2FMP I2C3FMP I2C4FMP PB6FMP PB7FMP PB8FMP PB9FMP BOOSTE EPIS PA0SO PA1SO PC2SO PC3SO

I2C1FMP : I2C1 Fm+
bits : 0 - 0 (1 bit)

I2C2FMP : I2C2 Fm+
bits : 1 - 1 (1 bit)

I2C3FMP : I2C3 Fm+
bits : 2 - 2 (1 bit)

I2C4FMP : I2C4 Fm+
bits : 3 - 3 (1 bit)

PB6FMP : PB(6) Fm+
bits : 4 - 4 (1 bit)

PB7FMP : PB(7) Fast Mode Plus
bits : 5 - 5 (1 bit)

PB8FMP : PB(8) Fast Mode Plus
bits : 6 - 6 (1 bit)

PB9FMP : PB(9) Fm+
bits : 7 - 7 (1 bit)

BOOSTE : Booster Enable
bits : 8 - 8 (1 bit)

EPIS : Ethernet PHY Interface Selection
bits : 21 - 23 (3 bit)

PA0SO : PA0 Switch Open
bits : 24 - 24 (1 bit)

PA1SO : PA1 Switch Open
bits : 25 - 25 (1 bit)

PC2SO : PC2 Switch Open
bits : 26 - 26 (1 bit)

PC3SO : PC3 Switch Open
bits : 27 - 27 (1 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI x configuration (x = 0 to 3)
bits : 0 - 3 (4 bit)

EXTI1 : EXTI x configuration (x = 0 to 3)
bits : 4 - 7 (4 bit)

EXTI2 : EXTI x configuration (x = 0 to 3)
bits : 8 - 11 (4 bit)

EXTI3 : EXTI x configuration (x = 0 to 3)
bits : 12 - 15 (4 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI x configuration (x = 4 to 7)
bits : 0 - 3 (4 bit)

EXTI5 : EXTI x configuration (x = 4 to 7)
bits : 4 - 7 (4 bit)

EXTI6 : EXTI x configuration (x = 4 to 7)
bits : 8 - 11 (4 bit)

EXTI7 : EXTI x configuration (x = 4 to 7)
bits : 12 - 15 (4 bit)



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