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TCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TCC_CTRLA

CTRLA

TCC_FCTRLB

FCTRLB

TCC_CC2

TCC_CC2_DITH4

TCC_CC2_DITH5

TCC_CC2_DITH6

TCC_WEXCTRL

WEXCTRL

TCC_CCBUF1

TCC_CCBUF1_DITH4

TCC_CCBUF1_DITH5

TCC_CCBUF1_DITH6

TCC_CC3

TCC_CC3_DITH4

TCC_CC3_DITH5

TCC_CC3_DITH6

TCC_DRVCTRL

DRVCTRL

TCC_CCBUF2

TCC_CCBUF2_DITH4

TCC_CCBUF2_DITH5

TCC_CCBUF2_DITH6

TCC_DBGCTRL

DBGCTRL

TCC_EVCTRL

EVCTRL

TCC_INTENCLR

INTENCLR

TCC_CCBUF3

TCC_CCBUF3_DITH4

TCC_CCBUF3_DITH5

TCC_CCBUF3_DITH6

TCC_INTENSET

INTENSET

TCC_INTFLAG

INTFLAG

TCC_STATUS

STATUS

TCC_COUNT

TCC_COUNT_DITH4

TCC_COUNT_DITH5

TCC_COUNT_DITH6

COUNT

COUNT_DITH4

COUNT_DITH5

COUNT_DITH6

COUNT_DITH4_MODE

COUNT_DITH5_MODE

COUNT_DITH6_MODE

TCC_PATT

PATT

TCC_WAVE

WAVE

TCC_CTRLBCLR

CTRLBCLR

TCC_PER

TCC_PER_DITH4

TCC_PER_DITH5

TCC_PER_DITH6

PER

PER_DITH4

PER_DITH5

PER_DITH6

PER_DITH4_MODE

PER_DITH5_MODE

PER_DITH6_MODE

CC0

CC0_DITH4

CC0_DITH5

CC0_DITH6

CC_DITH4_MODE0

CC_DITH5_MODE0

CC_DITH6_MODE0

CC1

CC1_DITH4

CC1_DITH5

CC1_DITH6

CC_DITH4_MODE1

CC_DITH5_MODE1

CC_DITH6_MODE1

CC2

CC2_DITH4

CC2_DITH5

CC2_DITH6

CC_DITH4_MODE2

CC_DITH5_MODE2

CC_DITH6_MODE2

TCC_CTRLBSET

CTRLBSET

CC3

CC3_DITH4

CC3_DITH5

CC3_DITH6

CC_DITH4_MODE3

CC_DITH5_MODE3

CC_DITH6_MODE3

TCC_PATTBUF

PATTBUF

TCC_PERBUF

TCC_PERBUF_DITH4

TCC_PERBUF_DITH5

TCC_PERBUF_DITH6

PERBUF

PERBUF_DITH4

PERBUF_DITH5

PERBUF_DITH6

PERBUF_DITH4_MODE

PERBUF_DITH5_MODE

PERBUF_DITH6_MODE

CCBUF0

CCBUF0_DITH4

CCBUF0_DITH5

CCBUF0_DITH6

CCBUF_DITH4_MODE0

CCBUF_DITH5_MODE0

CCBUF_DITH6_MODE0

CCBUF1

CCBUF1_DITH4

CCBUF1_DITH5

CCBUF1_DITH6

CCBUF_DITH4_MODE1

CCBUF_DITH5_MODE1

CCBUF_DITH6_MODE1

CCBUF2

CCBUF2_DITH4

CCBUF2_DITH5

CCBUF2_DITH6

CCBUF_DITH4_MODE2

CCBUF_DITH5_MODE2

CCBUF_DITH6_MODE2

CCBUF3

CCBUF3_DITH4

CCBUF3_DITH5

CCBUF3_DITH6

CCBUF_DITH4_MODE3

CCBUF_DITH5_MODE3

CCBUF_DITH6_MODE3

TCC_SYNCBUSY

SYNCBUSY

TCC_CC0

TCC_CC0_DITH4

TCC_CC0_DITH5

TCC_CC0_DITH6

TCC_FCTRLA

FCTRLA

TCC_CC1

TCC_CC1_DITH4

TCC_CC1_DITH5

TCC_CC1_DITH6

TCC_CCBUF0

TCC_CCBUF0_DITH4

TCC_CCBUF0_DITH5

TCC_CCBUF0_DITH6


TCC_CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CTRLA TCC_CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RESOLUTION PRESCALER RUNSTDBY PRESCSYNC ALOCK MSYNC DMAOS CPTEN0 CPTEN1 CPTEN2 CPTEN3

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RESOLUTION : Enhanced Resolution
bits : 5 - 6 (2 bit)

Enumeration: RESOLUTIONSelect

0x0 : NONE

Dithering is disabled

0x1 : DITH4

Dithering is done every 16 PWM frames

0x2 : DITH5

Dithering is done every 32 PWM frames

0x3 : DITH6

Dithering is done every 64 PWM frames

End of enumeration elements list.

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

No division

0x1 : DIV2

Divide by 2

0x2 : DIV4

Divide by 4

0x3 : DIV8

Divide by 8

0x4 : DIV16

Divide by 16

0x5 : DIV64

Divide by 64

0x6 : DIV256

Divide by 256

0x7 : DIV1024

Divide by 1024

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)

PRESCSYNC : Prescaler and Counter Synchronization Selection
bits : 12 - 13 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset counter on next GCLK

0x1 : PRESC

Reload or reset counter on next prescaler clock

0x2 : RESYNC

Reload or reset counter on next GCLK and reset prescaler counter

End of enumeration elements list.

ALOCK : Auto Lock
bits : 14 - 14 (1 bit)

MSYNC : Master Synchronization (only for TCC Slave Instance)
bits : 15 - 15 (1 bit)

DMAOS : DMA One-shot Trigger Mode
bits : 23 - 23 (1 bit)

CPTEN0 : Capture Channel 0 Enable
bits : 24 - 24 (1 bit)

CPTEN1 : Capture Channel 1 Enable
bits : 25 - 25 (1 bit)

CPTEN2 : Capture Channel 2 Enable
bits : 26 - 26 (1 bit)

CPTEN3 : Capture Channel 3 Enable
bits : 27 - 27 (1 bit)


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RESOLUTION PRESCALER RUNSTDBY PRESCSYNC ALOCK MSYNC DMAOS CPTEN0 CPTEN1 CPTEN2 CPTEN3

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

RESOLUTION : Enhanced Resolution
bits : 5 - 6 (2 bit)

Enumeration: RESOLUTIONSelect

0 : NONE

Dithering is disabled

1 : DITH4

Dithering is done every 16 PWM frames

2 : DITH5

Dithering is done every 32 PWM frames

3 : DITH6

Dithering is done every 64 PWM frames

End of enumeration elements list.

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0 : DIV1

No division

1 : DIV2

Divide by 2

2 : DIV4

Divide by 4

3 : DIV8

Divide by 8

4 : DIV16

Divide by 16

5 : DIV64

Divide by 64

6 : DIV256

Divide by 256

7 : DIV1024

Divide by 1024

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 11 - 11 (1 bit)

PRESCSYNC : Prescaler and Counter Synchronization Selection
bits : 12 - 13 (2 bit)

Enumeration: PRESCSYNCSelect

0 : GCLK

Reload or reset counter on next GCLK

1 : PRESC

Reload or reset counter on next prescaler clock

2 : RESYNC

Reload or reset counter on next GCLK and reset prescaler counter

End of enumeration elements list.

ALOCK : Auto Lock
bits : 14 - 14 (1 bit)

MSYNC : Master Synchronization (only for TCC Slave Instance)
bits : 15 - 15 (1 bit)

DMAOS : DMA One-shot Trigger Mode
bits : 23 - 23 (1 bit)

CPTEN0 : Capture Channel 0 Enable
bits : 24 - 24 (1 bit)

CPTEN1 : Capture Channel 1 Enable
bits : 25 - 25 (1 bit)

CPTEN2 : Capture Channel 2 Enable
bits : 26 - 26 (1 bit)

CPTEN3 : Capture Channel 3 Enable
bits : 27 - 27 (1 bit)


TCC_FCTRLB

Recoverable Fault B Configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_FCTRLB TCC_FCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC KEEP QUAL BLANK RESTART HALT CHSEL CAPTURE BLANKPRESC BLANKVAL FILTERVAL

SRC : Fault B Source
bits : 0 - 1 (2 bit)

Enumeration: SRCSelect

0x0 : DISABLE

Fault input disabled

0x1 : ENABLE

MCEx (x=0,1) event input

0x2 : INVERT

Inverted MCEx (x=0,1) event input

0x3 : ALTFAULT

Alternate fault (A or B) state at the end of the previous period

End of enumeration elements list.

KEEP : Fault B Keeper
bits : 3 - 3 (1 bit)

QUAL : Fault B Qualification
bits : 4 - 4 (1 bit)

BLANK : Fault B Blanking Mode
bits : 5 - 6 (2 bit)

Enumeration: BLANKSelect

0x0 : START

Blanking applied from start of the ramp

0x1 : RISE

Blanking applied from rising edge of the output waveform

0x2 : FALL

Blanking applied from falling edge of the output waveform

0x3 : BOTH

Blanking applied from each toggle of the output waveform

End of enumeration elements list.

RESTART : Fault B Restart
bits : 7 - 7 (1 bit)

HALT : Fault B Halt Mode
bits : 8 - 9 (2 bit)

Enumeration: HALTSelect

0x0 : DISABLE

Halt action disabled

0x1 : HW

Hardware halt action

0x2 : SW

Software halt action

0x3 : NR

Non-recoverable fault

End of enumeration elements list.

CHSEL : Fault B Capture Channel
bits : 10 - 11 (2 bit)

Enumeration: CHSELSelect

0x0 : CC0

Capture value stored in channel 0

0x1 : CC1

Capture value stored in channel 1

0x2 : CC2

Capture value stored in channel 2

0x3 : CC3

Capture value stored in channel 3

End of enumeration elements list.

CAPTURE : Fault B Capture Action
bits : 12 - 14 (3 bit)

Enumeration: CAPTURESelect

0x0 : DISABLE

No capture

0x1 : CAPT

Capture on fault

0x2 : CAPTMIN

Minimum capture

0x3 : CAPTMAX

Maximum capture

0x4 : LOCMIN

Minimum local detection

0x5 : LOCMAX

Maximum local detection

0x6 : DERIV0

Minimum and maximum local detection

0x7 : CAPTMARK

Capture with ramp index as MSB value

End of enumeration elements list.

BLANKPRESC : Fault B Blanking Prescaler
bits : 15 - 15 (1 bit)

BLANKVAL : Fault B Blanking Time
bits : 16 - 23 (8 bit)

FILTERVAL : Fault B Filter Value
bits : 24 - 27 (4 bit)


FCTRLB

Recoverable Fault B Configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCTRLB FCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC KEEP QUAL BLANK RESTART HALT CHSEL CAPTURE BLANKPRESC BLANKVAL FILTERVAL

SRC : Fault B Source
bits : 0 - 1 (2 bit)

Enumeration: SRCSelect

0 : DISABLE

Fault input disabled

1 : ENABLE

MCEx (x=0,1) event input

2 : INVERT

Inverted MCEx (x=0,1) event input

3 : ALTFAULT

Alternate fault (A or B) state at the end of the previous period

End of enumeration elements list.

KEEP : Fault B Keeper
bits : 3 - 3 (1 bit)

QUAL : Fault B Qualification
bits : 4 - 4 (1 bit)

BLANK : Fault B Blanking Mode
bits : 5 - 6 (2 bit)

Enumeration: BLANKSelect

0 : START

Blanking applied from start of the ramp

1 : RISE

Blanking applied from rising edge of the output waveform

2 : FALL

Blanking applied from falling edge of the output waveform

3 : BOTH

Blanking applied from each toggle of the output waveform

End of enumeration elements list.

RESTART : Fault B Restart
bits : 7 - 7 (1 bit)

HALT : Fault B Halt Mode
bits : 8 - 9 (2 bit)

Enumeration: HALTSelect

0 : DISABLE

Halt action disabled

1 : HW

Hardware halt action

2 : SW

Software halt action

3 : NR

Non-recoverable fault

End of enumeration elements list.

CHSEL : Fault B Capture Channel
bits : 10 - 11 (2 bit)

Enumeration: CHSELSelect

0 : CC0

Capture value stored in channel 0

1 : CC1

Capture value stored in channel 1

2 : CC2

Capture value stored in channel 2

3 : CC3

Capture value stored in channel 3

End of enumeration elements list.

CAPTURE : Fault B Capture Action
bits : 12 - 14 (3 bit)

Enumeration: CAPTURESelect

0 : DISABLE

No capture

1 : CAPT

Capture on fault

2 : CAPTMIN

Minimum capture

3 : CAPTMAX

Maximum capture

4 : LOCMIN

Minimum local detection

5 : LOCMAX

Maximum local detection

6 : DERIV0

Minimum and maximum local detection

7 : CAPTMARK

Capture with ramp index as MSB value

End of enumeration elements list.

BLANKPRESC : Fault B Blanking Prescaler
bits : 15 - 15 (1 bit)

BLANKVAL : Fault B Blanking Time
bits : 16 - 23 (8 bit)

FILTERVAL : Fault B Filter Value
bits : 24 - 27 (4 bit)


TCC_CC2

Compare and Capture
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CC2 TCC_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


TCC_CC2_DITH4

Compare and Capture
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC2_DITH4 TCC_CC2_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


TCC_CC2_DITH5

Compare and Capture
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC2_DITH5 TCC_CC2_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


TCC_CC2_DITH6

Compare and Capture
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC2_DITH6 TCC_CC2_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_WEXCTRL

Waveform Extension Configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_WEXCTRL TCC_WEXCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTMX DTIEN0 DTIEN1 DTIEN2 DTIEN3 DTLS DTHS

OTMX : Output Matrix
bits : 0 - 1 (2 bit)

DTIEN0 : Dead-time Insertion Generator 0 Enable
bits : 8 - 8 (1 bit)

DTIEN1 : Dead-time Insertion Generator 1 Enable
bits : 9 - 9 (1 bit)

DTIEN2 : Dead-time Insertion Generator 2 Enable
bits : 10 - 10 (1 bit)

DTIEN3 : Dead-time Insertion Generator 3 Enable
bits : 11 - 11 (1 bit)

DTLS : Dead-time Low Side Outputs Value
bits : 16 - 23 (8 bit)

DTHS : Dead-time High Side Outputs Value
bits : 24 - 31 (8 bit)


WEXCTRL

Waveform Extension Configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WEXCTRL WEXCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTMX DTIEN0 DTIEN1 DTIEN2 DTIEN3 DTLS DTHS

OTMX : Output Matrix
bits : 0 - 1 (2 bit)

DTIEN0 : Dead-time Insertion Generator 0 Enable
bits : 8 - 8 (1 bit)

DTIEN1 : Dead-time Insertion Generator 1 Enable
bits : 9 - 9 (1 bit)

DTIEN2 : Dead-time Insertion Generator 2 Enable
bits : 10 - 10 (1 bit)

DTIEN3 : Dead-time Insertion Generator 3 Enable
bits : 11 - 11 (1 bit)

DTLS : Dead-time Low Side Outputs Value
bits : 16 - 23 (8 bit)

DTHS : Dead-time High Side Outputs Value
bits : 24 - 31 (8 bit)


TCC_CCBUF1

Compare and Capture Buffer
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CCBUF1 TCC_CCBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


TCC_CCBUF1_DITH4

Compare and Capture Buffer
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF1_DITH4 TCC_CCBUF1_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


TCC_CCBUF1_DITH5

Compare and Capture Buffer
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF1_DITH5 TCC_CCBUF1_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


TCC_CCBUF1_DITH6

Compare and Capture Buffer
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF1_DITH6 TCC_CCBUF1_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


TCC_CC3

Compare and Capture
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CC3 TCC_CC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


TCC_CC3_DITH4

Compare and Capture
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC3_DITH4 TCC_CC3_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


TCC_CC3_DITH5

Compare and Capture
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC3_DITH5 TCC_CC3_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


TCC_CC3_DITH6

Compare and Capture
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC3_DITH6 TCC_CC3_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_DRVCTRL

Driver Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_DRVCTRL TCC_DRVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRE0 NRE1 NRE2 NRE3 NRE4 NRE5 NRE6 NRE7 NRV0 NRV1 NRV2 NRV3 NRV4 NRV5 NRV6 NRV7 INVEN0 INVEN1 INVEN2 INVEN3 INVEN4 INVEN5 INVEN6 INVEN7 FILTERVAL0 FILTERVAL1

NRE0 : Non-Recoverable State 0 Output Enable
bits : 0 - 0 (1 bit)

NRE1 : Non-Recoverable State 1 Output Enable
bits : 1 - 1 (1 bit)

NRE2 : Non-Recoverable State 2 Output Enable
bits : 2 - 2 (1 bit)

NRE3 : Non-Recoverable State 3 Output Enable
bits : 3 - 3 (1 bit)

NRE4 : Non-Recoverable State 4 Output Enable
bits : 4 - 4 (1 bit)

NRE5 : Non-Recoverable State 5 Output Enable
bits : 5 - 5 (1 bit)

NRE6 : Non-Recoverable State 6 Output Enable
bits : 6 - 6 (1 bit)

NRE7 : Non-Recoverable State 7 Output Enable
bits : 7 - 7 (1 bit)

NRV0 : Non-Recoverable State 0 Output Value
bits : 8 - 8 (1 bit)

NRV1 : Non-Recoverable State 1 Output Value
bits : 9 - 9 (1 bit)

NRV2 : Non-Recoverable State 2 Output Value
bits : 10 - 10 (1 bit)

NRV3 : Non-Recoverable State 3 Output Value
bits : 11 - 11 (1 bit)

NRV4 : Non-Recoverable State 4 Output Value
bits : 12 - 12 (1 bit)

NRV5 : Non-Recoverable State 5 Output Value
bits : 13 - 13 (1 bit)

NRV6 : Non-Recoverable State 6 Output Value
bits : 14 - 14 (1 bit)

NRV7 : Non-Recoverable State 7 Output Value
bits : 15 - 15 (1 bit)

INVEN0 : Output Waveform 0 Inversion
bits : 16 - 16 (1 bit)

INVEN1 : Output Waveform 1 Inversion
bits : 17 - 17 (1 bit)

INVEN2 : Output Waveform 2 Inversion
bits : 18 - 18 (1 bit)

INVEN3 : Output Waveform 3 Inversion
bits : 19 - 19 (1 bit)

INVEN4 : Output Waveform 4 Inversion
bits : 20 - 20 (1 bit)

INVEN5 : Output Waveform 5 Inversion
bits : 21 - 21 (1 bit)

INVEN6 : Output Waveform 6 Inversion
bits : 22 - 22 (1 bit)

INVEN7 : Output Waveform 7 Inversion
bits : 23 - 23 (1 bit)

FILTERVAL0 : Non-Recoverable Fault Input 0 Filter Value
bits : 24 - 27 (4 bit)

FILTERVAL1 : Non-Recoverable Fault Input 1 Filter Value
bits : 28 - 31 (4 bit)


DRVCTRL

Driver Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRVCTRL DRVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRE0 NRE1 NRE2 NRE3 NRE4 NRE5 NRE6 NRE7 NRV0 NRV1 NRV2 NRV3 NRV4 NRV5 NRV6 NRV7 INVEN0 INVEN1 INVEN2 INVEN3 INVEN4 INVEN5 INVEN6 INVEN7 FILTERVAL0 FILTERVAL1

NRE0 : Non-Recoverable State 0 Output Enable
bits : 0 - 0 (1 bit)

NRE1 : Non-Recoverable State 1 Output Enable
bits : 1 - 1 (1 bit)

NRE2 : Non-Recoverable State 2 Output Enable
bits : 2 - 2 (1 bit)

NRE3 : Non-Recoverable State 3 Output Enable
bits : 3 - 3 (1 bit)

NRE4 : Non-Recoverable State 4 Output Enable
bits : 4 - 4 (1 bit)

NRE5 : Non-Recoverable State 5 Output Enable
bits : 5 - 5 (1 bit)

NRE6 : Non-Recoverable State 6 Output Enable
bits : 6 - 6 (1 bit)

NRE7 : Non-Recoverable State 7 Output Enable
bits : 7 - 7 (1 bit)

NRV0 : Non-Recoverable State 0 Output Value
bits : 8 - 8 (1 bit)

NRV1 : Non-Recoverable State 1 Output Value
bits : 9 - 9 (1 bit)

NRV2 : Non-Recoverable State 2 Output Value
bits : 10 - 10 (1 bit)

NRV3 : Non-Recoverable State 3 Output Value
bits : 11 - 11 (1 bit)

NRV4 : Non-Recoverable State 4 Output Value
bits : 12 - 12 (1 bit)

NRV5 : Non-Recoverable State 5 Output Value
bits : 13 - 13 (1 bit)

NRV6 : Non-Recoverable State 6 Output Value
bits : 14 - 14 (1 bit)

NRV7 : Non-Recoverable State 7 Output Value
bits : 15 - 15 (1 bit)

INVEN0 : Output Waveform 0 Inversion
bits : 16 - 16 (1 bit)

INVEN1 : Output Waveform 1 Inversion
bits : 17 - 17 (1 bit)

INVEN2 : Output Waveform 2 Inversion
bits : 18 - 18 (1 bit)

INVEN3 : Output Waveform 3 Inversion
bits : 19 - 19 (1 bit)

INVEN4 : Output Waveform 4 Inversion
bits : 20 - 20 (1 bit)

INVEN5 : Output Waveform 5 Inversion
bits : 21 - 21 (1 bit)

INVEN6 : Output Waveform 6 Inversion
bits : 22 - 22 (1 bit)

INVEN7 : Output Waveform 7 Inversion
bits : 23 - 23 (1 bit)

FILTERVAL0 : Non-Recoverable Fault Input 0 Filter Value
bits : 24 - 27 (4 bit)

FILTERVAL1 : Non-Recoverable Fault Input 1 Filter Value
bits : 28 - 31 (4 bit)


TCC_CCBUF2

Compare and Capture Buffer
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CCBUF2 TCC_CCBUF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


TCC_CCBUF2_DITH4

Compare and Capture Buffer
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF2_DITH4 TCC_CCBUF2_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


TCC_CCBUF2_DITH5

Compare and Capture Buffer
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF2_DITH5 TCC_CCBUF2_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


TCC_CCBUF2_DITH6

Compare and Capture Buffer
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF2_DITH6 TCC_CCBUF2_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


TCC_DBGCTRL

Debug Control
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_DBGCTRL TCC_DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN FDDBD

DBGRUN : Debug Running Mode
bits : 0 - 0 (1 bit)

FDDBD : Fault Detection on Debug Break Detection
bits : 2 - 2 (1 bit)


DBGCTRL

Debug Control
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN FDDBD

DBGRUN : Debug Running Mode
bits : 0 - 0 (1 bit)

FDDBD : Fault Detection on Debug Break Detection
bits : 2 - 2 (1 bit)


TCC_EVCTRL

Event Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_EVCTRL TCC_EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT0 EVACT1 CNTSEL OVFEO TRGEO CNTEO TCINV0 TCINV1 TCEI0 TCEI1 MCEI0 MCEI1 MCEI2 MCEI3 MCEO0 MCEO1 MCEO2 MCEO3

EVACT0 : Timer/counter Input Event0 Action
bits : 0 - 2 (3 bit)

Enumeration: EVACT0Select

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or re-trigger counter on event

0x2 : COUNTEV

Count on event

0x3 : START

Start counter on event

0x4 : INC

Increment counter on event

0x5 : COUNT

Count on active state of asynchronous event

0x6 : STAMP

Stamp capture

0x7 : FAULT

Non-recoverable fault

End of enumeration elements list.

EVACT1 : Timer/counter Input Event1 Action
bits : 3 - 5 (3 bit)

Enumeration: EVACT1Select

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Re-trigger counter on event

0x2 : DIR

Direction control

0x3 : STOP

Stop counter on event

0x4 : DEC

Decrement counter on event

0x5 : PPW

Period capture value in CC0 register, pulse width capture value in CC1 register

0x6 : PWP

Period capture value in CC1 register, pulse width capture value in CC0 register

0x7 : FAULT

Non-recoverable fault

End of enumeration elements list.

CNTSEL : Timer/counter Output Event Mode
bits : 6 - 7 (2 bit)

Enumeration: CNTSELSelect

0x0 : START

An interrupt/event is generated when a new counter cycle starts

0x1 : END

An interrupt/event is generated when a counter cycle ends

0x2 : BETWEEN

An interrupt/event is generated when a counter cycle ends, except for the first and last cycles

0x3 : BOUNDARY

An interrupt/event is generated when a new counter cycle starts or a counter cycle ends

End of enumeration elements list.

OVFEO : Overflow/Underflow Output Event Enable
bits : 8 - 8 (1 bit)

TRGEO : Retrigger Output Event Enable
bits : 9 - 9 (1 bit)

CNTEO : Timer/counter Output Event Enable
bits : 10 - 10 (1 bit)

TCINV0 : Inverted Event 0 Input Enable
bits : 12 - 12 (1 bit)

TCINV1 : Inverted Event 1 Input Enable
bits : 13 - 13 (1 bit)

TCEI0 : Timer/counter Event 0 Input Enable
bits : 14 - 14 (1 bit)

TCEI1 : Timer/counter Event 1 Input Enable
bits : 15 - 15 (1 bit)

MCEI0 : Match or Capture Channel 0 Event Input Enable
bits : 16 - 16 (1 bit)

MCEI1 : Match or Capture Channel 1 Event Input Enable
bits : 17 - 17 (1 bit)

MCEI2 : Match or Capture Channel 2 Event Input Enable
bits : 18 - 18 (1 bit)

MCEI3 : Match or Capture Channel 3 Event Input Enable
bits : 19 - 19 (1 bit)

MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 24 - 24 (1 bit)

MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 25 - 25 (1 bit)

MCEO2 : Match or Capture Channel 2 Event Output Enable
bits : 26 - 26 (1 bit)

MCEO3 : Match or Capture Channel 3 Event Output Enable
bits : 27 - 27 (1 bit)


EVCTRL

Event Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT0 EVACT1 CNTSEL OVFEO TRGEO CNTEO TCINV0 TCINV1 TCEI0 TCEI1 MCEI0 MCEI1 MCEI2 MCEI3 MCEO0 MCEO1 MCEO2 MCEO3

EVACT0 : Timer/counter Input Event0 Action
bits : 0 - 2 (3 bit)

Enumeration: EVACT0Select

0 : OFF

Event action disabled

1 : RETRIGGER

Start, restart or re-trigger counter on event

2 : COUNTEV

Count on event

3 : START

Start counter on event

4 : INC

Increment counter on event

5 : COUNT

Count on active state of asynchronous event

6 : STAMP

Stamp capture

7 : FAULT

Non-recoverable fault

End of enumeration elements list.

EVACT1 : Timer/counter Input Event1 Action
bits : 3 - 5 (3 bit)

Enumeration: EVACT1Select

0 : OFF

Event action disabled

1 : RETRIGGER

Re-trigger counter on event

2 : DIR

Direction control

3 : STOP

Stop counter on event

4 : DEC

Decrement counter on event

5 : PPW

Period capture value in CC0 register, pulse width capture value in CC1 register

6 : PWP

Period capture value in CC1 register, pulse width capture value in CC0 register

7 : FAULT

Non-recoverable fault

End of enumeration elements list.

CNTSEL : Timer/counter Output Event Mode
bits : 6 - 7 (2 bit)

Enumeration: CNTSELSelect

0 : START

An interrupt/event is generated when a new counter cycle starts

1 : END

An interrupt/event is generated when a counter cycle ends

2 : BETWEEN

An interrupt/event is generated when a counter cycle ends, except for the first and last cycles

3 : BOUNDARY

An interrupt/event is generated when a new counter cycle starts or a counter cycle ends

End of enumeration elements list.

OVFEO : Overflow/Underflow Output Event Enable
bits : 8 - 8 (1 bit)

TRGEO : Retrigger Output Event Enable
bits : 9 - 9 (1 bit)

CNTEO : Timer/counter Output Event Enable
bits : 10 - 10 (1 bit)

TCINV0 : Inverted Event 0 Input Enable
bits : 12 - 12 (1 bit)

TCINV1 : Inverted Event 1 Input Enable
bits : 13 - 13 (1 bit)

TCEI0 : Timer/counter Event 0 Input Enable
bits : 14 - 14 (1 bit)

TCEI1 : Timer/counter Event 1 Input Enable
bits : 15 - 15 (1 bit)

MCEI0 : Match or Capture Channel 0 Event Input Enable
bits : 16 - 16 (1 bit)

MCEI1 : Match or Capture Channel 1 Event Input Enable
bits : 17 - 17 (1 bit)

MCEI2 : Match or Capture Channel 2 Event Input Enable
bits : 18 - 18 (1 bit)

MCEI3 : Match or Capture Channel 3 Event Input Enable
bits : 19 - 19 (1 bit)

MCEO0 : Match or Capture Channel 0 Event Output Enable
bits : 24 - 24 (1 bit)

MCEO1 : Match or Capture Channel 1 Event Output Enable
bits : 25 - 25 (1 bit)

MCEO2 : Match or Capture Channel 2 Event Output Enable
bits : 26 - 26 (1 bit)

MCEO3 : Match or Capture Channel 3 Event Output Enable
bits : 27 - 27 (1 bit)


TCC_INTENCLR

Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_INTENCLR TCC_INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)

CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)

ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault Interrupt Enable
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)

MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)

MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)

CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)

ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault Interrupt Enable
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)

MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)

MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)


TCC_CCBUF3

Compare and Capture Buffer
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CCBUF3 TCC_CCBUF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


TCC_CCBUF3_DITH4

Compare and Capture Buffer
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF3_DITH4 TCC_CCBUF3_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


TCC_CCBUF3_DITH5

Compare and Capture Buffer
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF3_DITH5 TCC_CCBUF3_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


TCC_CCBUF3_DITH6

Compare and Capture Buffer
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF3_DITH6 TCC_CCBUF3_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


TCC_INTENSET

Interrupt Enable Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_INTENSET TCC_INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)

CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)

ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault Interrupt Enable
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)

MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)

MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow Interrupt Enable
bits : 0 - 0 (1 bit)

TRG : Retrigger Interrupt Enable
bits : 1 - 1 (1 bit)

CNT : Counter Interrupt Enable
bits : 2 - 2 (1 bit)

ERR : Error Interrupt Enable
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault Interrupt Enable
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault Interrupt Enable
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A Interrupt Enable
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B Interrupt Enable
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 Interrupt Enable
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 Interrupt Enable
bits : 15 - 15 (1 bit)

MC0 : Match or Capture Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)

MC1 : Match or Capture Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)

MC2 : Match or Capture Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)

MC3 : Match or Capture Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)


TCC_INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_INTFLAG TCC_INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow
bits : 0 - 0 (1 bit)

TRG : Retrigger
bits : 1 - 1 (1 bit)

CNT : Counter
bits : 2 - 2 (1 bit)

ERR : Error
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1
bits : 15 - 15 (1 bit)

MC0 : Match or Capture 0
bits : 16 - 16 (1 bit)

MC1 : Match or Capture 1
bits : 17 - 17 (1 bit)

MC2 : Match or Capture 2
bits : 18 - 18 (1 bit)

MC3 : Match or Capture 3
bits : 19 - 19 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF TRG CNT ERR UFS DFS FAULTA FAULTB FAULT0 FAULT1 MC0 MC1 MC2 MC3

OVF : Overflow
bits : 0 - 0 (1 bit)

TRG : Retrigger
bits : 1 - 1 (1 bit)

CNT : Counter
bits : 2 - 2 (1 bit)

ERR : Error
bits : 3 - 3 (1 bit)

UFS : Non-Recoverable Update Fault
bits : 10 - 10 (1 bit)

DFS : Non-Recoverable Debug Fault
bits : 11 - 11 (1 bit)

FAULTA : Recoverable Fault A
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1
bits : 15 - 15 (1 bit)

MC0 : Match or Capture 0
bits : 16 - 16 (1 bit)

MC1 : Match or Capture 1
bits : 17 - 17 (1 bit)

MC2 : Match or Capture 2
bits : 18 - 18 (1 bit)

MC3 : Match or Capture 3
bits : 19 - 19 (1 bit)


TCC_STATUS

Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_STATUS TCC_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP IDX UFS DFS SLAVE PATTBUFV PERBUFV FAULTAIN FAULTBIN FAULT0IN FAULT1IN FAULTA FAULTB FAULT0 FAULT1 CCBUFV0 CCBUFV1 CCBUFV2 CCBUFV3 CMP0 CMP1 CMP2 CMP3

STOP : Stop
bits : 0 - 0 (1 bit)
access : read-only

IDX : Ramp
bits : 1 - 1 (1 bit)
access : read-only

UFS : Non-recoverable Update Fault State
bits : 2 - 2 (1 bit)

DFS : Non-Recoverable Debug Fault State
bits : 3 - 3 (1 bit)

SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only

PATTBUFV : Pattern Buffer Valid
bits : 5 - 5 (1 bit)

PERBUFV : Period Buffer Valid
bits : 7 - 7 (1 bit)

FAULTAIN : Recoverable Fault A Input
bits : 8 - 8 (1 bit)
access : read-only

FAULTBIN : Recoverable Fault B Input
bits : 9 - 9 (1 bit)
access : read-only

FAULT0IN : Non-Recoverable Fault0 Input
bits : 10 - 10 (1 bit)
access : read-only

FAULT1IN : Non-Recoverable Fault1 Input
bits : 11 - 11 (1 bit)
access : read-only

FAULTA : Recoverable Fault A State
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B State
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 State
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 State
bits : 15 - 15 (1 bit)

CCBUFV0 : Compare Channel 0 Buffer Valid
bits : 16 - 16 (1 bit)

CCBUFV1 : Compare Channel 1 Buffer Valid
bits : 17 - 17 (1 bit)

CCBUFV2 : Compare Channel 2 Buffer Valid
bits : 18 - 18 (1 bit)

CCBUFV3 : Compare Channel 3 Buffer Valid
bits : 19 - 19 (1 bit)

CMP0 : Compare Channel 0 Value
bits : 24 - 24 (1 bit)
access : read-only

CMP1 : Compare Channel 1 Value
bits : 25 - 25 (1 bit)
access : read-only

CMP2 : Compare Channel 2 Value
bits : 26 - 26 (1 bit)
access : read-only

CMP3 : Compare Channel 3 Value
bits : 27 - 27 (1 bit)
access : read-only


STATUS

Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP IDX UFS DFS SLAVE PATTBUFV PERBUFV FAULTAIN FAULTBIN FAULT0IN FAULT1IN FAULTA FAULTB FAULT0 FAULT1 CCBUFV0 CCBUFV1 CCBUFV2 CCBUFV3 CMP0 CMP1 CMP2 CMP3

STOP : Stop
bits : 0 - 0 (1 bit)
access : read-only

IDX : Ramp
bits : 1 - 1 (1 bit)
access : read-only

UFS : Non-recoverable Update Fault State
bits : 2 - 2 (1 bit)

DFS : Non-Recoverable Debug Fault State
bits : 3 - 3 (1 bit)

SLAVE : Slave
bits : 4 - 4 (1 bit)
access : read-only

PATTBUFV : Pattern Buffer Valid
bits : 5 - 5 (1 bit)

PERBUFV : Period Buffer Valid
bits : 7 - 7 (1 bit)

FAULTAIN : Recoverable Fault A Input
bits : 8 - 8 (1 bit)
access : read-only

FAULTBIN : Recoverable Fault B Input
bits : 9 - 9 (1 bit)
access : read-only

FAULT0IN : Non-Recoverable Fault0 Input
bits : 10 - 10 (1 bit)
access : read-only

FAULT1IN : Non-Recoverable Fault1 Input
bits : 11 - 11 (1 bit)
access : read-only

FAULTA : Recoverable Fault A State
bits : 12 - 12 (1 bit)

FAULTB : Recoverable Fault B State
bits : 13 - 13 (1 bit)

FAULT0 : Non-Recoverable Fault 0 State
bits : 14 - 14 (1 bit)

FAULT1 : Non-Recoverable Fault 1 State
bits : 15 - 15 (1 bit)

CCBUFV0 : Compare Channel 0 Buffer Valid
bits : 16 - 16 (1 bit)

CCBUFV1 : Compare Channel 1 Buffer Valid
bits : 17 - 17 (1 bit)

CCBUFV2 : Compare Channel 2 Buffer Valid
bits : 18 - 18 (1 bit)

CCBUFV3 : Compare Channel 3 Buffer Valid
bits : 19 - 19 (1 bit)

CMP0 : Compare Channel 0 Value
bits : 24 - 24 (1 bit)
access : read-only

CMP1 : Compare Channel 1 Value
bits : 25 - 25 (1 bit)
access : read-only

CMP2 : Compare Channel 2 Value
bits : 26 - 26 (1 bit)
access : read-only

CMP3 : Compare Channel 3 Value
bits : 27 - 27 (1 bit)
access : read-only


TCC_COUNT

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_COUNT TCC_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 23 (24 bit)


TCC_COUNT_DITH4

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

TCC_COUNT_DITH4 TCC_COUNT_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 4 - 23 (20 bit)


TCC_COUNT_DITH5

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

TCC_COUNT_DITH5 TCC_COUNT_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 5 - 23 (19 bit)


TCC_COUNT_DITH6

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

TCC_COUNT_DITH6 TCC_COUNT_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 6 - 23 (18 bit)


COUNT

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 23 (24 bit)


COUNT_DITH4

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT_DITH4 COUNT_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 4 - 23 (20 bit)


COUNT_DITH5

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT_DITH5 COUNT_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 5 - 23 (19 bit)


COUNT_DITH6

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT_DITH6 COUNT_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 6 - 23 (18 bit)


COUNT_DITH4_MODE

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

COUNT_DITH4_MODE COUNT_DITH4_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 4 - 23 (20 bit)


COUNT_DITH5_MODE

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

COUNT_DITH5_MODE COUNT_DITH5_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 5 - 23 (19 bit)


COUNT_DITH6_MODE

Count
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : COUNT
reset_Mask : 0x0

COUNT_DITH6_MODE COUNT_DITH6_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 6 - 23 (18 bit)


TCC_PATT

Pattern
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_PATT TCC_PATT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGE0 PGE1 PGE2 PGE3 PGE4 PGE5 PGE6 PGE7 PGV0 PGV1 PGV2 PGV3 PGV4 PGV5 PGV6 PGV7

PGE0 : Pattern Generator 0 Output Enable
bits : 0 - 0 (1 bit)

PGE1 : Pattern Generator 1 Output Enable
bits : 1 - 1 (1 bit)

PGE2 : Pattern Generator 2 Output Enable
bits : 2 - 2 (1 bit)

PGE3 : Pattern Generator 3 Output Enable
bits : 3 - 3 (1 bit)

PGE4 : Pattern Generator 4 Output Enable
bits : 4 - 4 (1 bit)

PGE5 : Pattern Generator 5 Output Enable
bits : 5 - 5 (1 bit)

PGE6 : Pattern Generator 6 Output Enable
bits : 6 - 6 (1 bit)

PGE7 : Pattern Generator 7 Output Enable
bits : 7 - 7 (1 bit)

PGV0 : Pattern Generator 0 Output Value
bits : 8 - 8 (1 bit)

PGV1 : Pattern Generator 1 Output Value
bits : 9 - 9 (1 bit)

PGV2 : Pattern Generator 2 Output Value
bits : 10 - 10 (1 bit)

PGV3 : Pattern Generator 3 Output Value
bits : 11 - 11 (1 bit)

PGV4 : Pattern Generator 4 Output Value
bits : 12 - 12 (1 bit)

PGV5 : Pattern Generator 5 Output Value
bits : 13 - 13 (1 bit)

PGV6 : Pattern Generator 6 Output Value
bits : 14 - 14 (1 bit)

PGV7 : Pattern Generator 7 Output Value
bits : 15 - 15 (1 bit)


PATT

Pattern
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT PATT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGE0 PGE1 PGE2 PGE3 PGE4 PGE5 PGE6 PGE7 PGV0 PGV1 PGV2 PGV3 PGV4 PGV5 PGV6 PGV7

PGE0 : Pattern Generator 0 Output Enable
bits : 0 - 0 (1 bit)

PGE1 : Pattern Generator 1 Output Enable
bits : 1 - 1 (1 bit)

PGE2 : Pattern Generator 2 Output Enable
bits : 2 - 2 (1 bit)

PGE3 : Pattern Generator 3 Output Enable
bits : 3 - 3 (1 bit)

PGE4 : Pattern Generator 4 Output Enable
bits : 4 - 4 (1 bit)

PGE5 : Pattern Generator 5 Output Enable
bits : 5 - 5 (1 bit)

PGE6 : Pattern Generator 6 Output Enable
bits : 6 - 6 (1 bit)

PGE7 : Pattern Generator 7 Output Enable
bits : 7 - 7 (1 bit)

PGV0 : Pattern Generator 0 Output Value
bits : 8 - 8 (1 bit)

PGV1 : Pattern Generator 1 Output Value
bits : 9 - 9 (1 bit)

PGV2 : Pattern Generator 2 Output Value
bits : 10 - 10 (1 bit)

PGV3 : Pattern Generator 3 Output Value
bits : 11 - 11 (1 bit)

PGV4 : Pattern Generator 4 Output Value
bits : 12 - 12 (1 bit)

PGV5 : Pattern Generator 5 Output Value
bits : 13 - 13 (1 bit)

PGV6 : Pattern Generator 6 Output Value
bits : 14 - 14 (1 bit)

PGV7 : Pattern Generator 7 Output Value
bits : 15 - 15 (1 bit)


TCC_WAVE

Waveform Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_WAVE TCC_WAVE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEGEN RAMP CIPEREN CICCEN0 CICCEN1 CICCEN2 CICCEN3 POL0 POL1 POL2 POL3 SWAP0 SWAP1 SWAP2 SWAP3

WAVEGEN : Waveform Generation
bits : 0 - 2 (3 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ

Normal frequency

0x1 : MFRQ

Match frequency

0x2 : NPWM

Normal PWM

0x4 : DSCRITICAL

Dual-slope critical

0x5 : DSBOTTOM

Dual-slope with interrupt/event condition when COUNT reaches ZERO

0x6 : DSBOTH

Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP

0x7 : DSTOP

Dual-slope with interrupt/event condition when COUNT reaches TOP

End of enumeration elements list.

RAMP : Ramp Mode
bits : 4 - 5 (2 bit)

Enumeration: RAMPSelect

0x0 : RAMP1

RAMP1 operation

0x1 : RAMP2A

Alternative RAMP2 operation

0x2 : RAMP2

RAMP2 operation

0x3 : RAMP2C

Critical RAMP2 operation

End of enumeration elements list.

CIPEREN : Circular period Enable
bits : 7 - 7 (1 bit)

CICCEN0 : Circular Channel 0 Enable
bits : 8 - 8 (1 bit)

CICCEN1 : Circular Channel 1 Enable
bits : 9 - 9 (1 bit)

CICCEN2 : Circular Channel 2 Enable
bits : 10 - 10 (1 bit)

CICCEN3 : Circular Channel 3 Enable
bits : 11 - 11 (1 bit)

POL0 : Channel 0 Polarity
bits : 16 - 16 (1 bit)

POL1 : Channel 1 Polarity
bits : 17 - 17 (1 bit)

POL2 : Channel 2 Polarity
bits : 18 - 18 (1 bit)

POL3 : Channel 3 Polarity
bits : 19 - 19 (1 bit)

SWAP0 : Swap DTI Output Pair 0
bits : 24 - 24 (1 bit)

SWAP1 : Swap DTI Output Pair 1
bits : 25 - 25 (1 bit)

SWAP2 : Swap DTI Output Pair 2
bits : 26 - 26 (1 bit)

SWAP3 : Swap DTI Output Pair 3
bits : 27 - 27 (1 bit)


WAVE

Waveform Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAVE WAVE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVEGEN RAMP CIPEREN CICCEN0 CICCEN1 CICCEN2 CICCEN3 POL0 POL1 POL2 POL3 SWAP0 SWAP1 SWAP2 SWAP3

WAVEGEN : Waveform Generation
bits : 0 - 2 (3 bit)

Enumeration: WAVEGENSelect

0 : NFRQ

Normal frequency

1 : MFRQ

Match frequency

2 : NPWM

Normal PWM

4 : DSCRITICAL

Dual-slope critical

5 : DSBOTTOM

Dual-slope with interrupt/event condition when COUNT reaches ZERO

6 : DSBOTH

Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP

7 : DSTOP

Dual-slope with interrupt/event condition when COUNT reaches TOP

End of enumeration elements list.

RAMP : Ramp Mode
bits : 4 - 5 (2 bit)

Enumeration: RAMPSelect

0 : RAMP1

RAMP1 operation

1 : RAMP2A

Alternative RAMP2 operation

2 : RAMP2

RAMP2 operation

3 : RAMP2C

Critical RAMP2 operation

End of enumeration elements list.

CIPEREN : Circular period Enable
bits : 7 - 7 (1 bit)

CICCEN0 : Circular Channel 0 Enable
bits : 8 - 8 (1 bit)

CICCEN1 : Circular Channel 1 Enable
bits : 9 - 9 (1 bit)

CICCEN2 : Circular Channel 2 Enable
bits : 10 - 10 (1 bit)

CICCEN3 : Circular Channel 3 Enable
bits : 11 - 11 (1 bit)

POL0 : Channel 0 Polarity
bits : 16 - 16 (1 bit)

POL1 : Channel 1 Polarity
bits : 17 - 17 (1 bit)

POL2 : Channel 2 Polarity
bits : 18 - 18 (1 bit)

POL3 : Channel 3 Polarity
bits : 19 - 19 (1 bit)

SWAP0 : Swap DTI Output Pair 0
bits : 24 - 24 (1 bit)

SWAP1 : Swap DTI Output Pair 1
bits : 25 - 25 (1 bit)

SWAP2 : Swap DTI Output Pair 2
bits : 26 - 26 (1 bit)

SWAP3 : Swap DTI Output Pair 3
bits : 27 - 27 (1 bit)


TCC_CTRLBCLR

Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CTRLBCLR TCC_CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT IDXCMD CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot
bits : 2 - 2 (1 bit)

IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)

Enumeration: IDXCMDSelect

0x0 : DISABLE

Command disabled: Index toggles between cycles A and B

0x1 : SET

Set index: cycle B will be forced in the next cycle

0x2 : CLEAR

Clear index: cycle A will be forced in the next cycle

0x3 : HOLD

Hold index: the next cycle will be the same as the current cycle

End of enumeration elements list.

CMD : TCC Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Clear start, restart or retrigger

0x2 : STOP

Force stop

0x3 : UPDATE

Force update or double buffered registers

0x4 : READSYNC

Force COUNT read synchronization

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


CTRLBCLR

Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBCLR CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT IDXCMD CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot
bits : 2 - 2 (1 bit)

IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)

Enumeration: IDXCMDSelect

0 : DISABLE

Command disabled: Index toggles between cycles A and B

1 : SET

Set index: cycle B will be forced in the next cycle

2 : CLEAR

Clear index: cycle A will be forced in the next cycle

3 : HOLD

Hold index: the next cycle will be the same as the current cycle

End of enumeration elements list.

CMD : TCC Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0 : NONE

No action

1 : RETRIGGER

Clear start, restart or retrigger

2 : STOP

Force stop

3 : UPDATE

Force update or double buffered registers

4 : READSYNC

Force COUNT read synchronization

5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TCC_PER

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_PER TCC_PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER

PER : Period Value
bits : 0 - 23 (24 bit)


TCC_PER_DITH4

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

TCC_PER_DITH4 TCC_PER_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

PER : Period Value
bits : 4 - 23 (20 bit)


TCC_PER_DITH5

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

TCC_PER_DITH5 TCC_PER_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

PER : Period Value
bits : 5 - 23 (19 bit)


TCC_PER_DITH6

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

TCC_PER_DITH6 TCC_PER_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

PER : Period Value
bits : 6 - 23 (18 bit)


PER

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER

PER : Period Value
bits : 0 - 23 (24 bit)


PER_DITH4

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER_DITH4 PER_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

PER : Period Value
bits : 4 - 23 (20 bit)


PER_DITH5

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER_DITH5 PER_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

PER : Period Value
bits : 5 - 23 (19 bit)


PER_DITH6

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER_DITH6 PER_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

PER : Period Value
bits : 6 - 23 (18 bit)


PER_DITH4_MODE

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

PER_DITH4_MODE PER_DITH4_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

PER : Period Value
bits : 4 - 23 (20 bit)


PER_DITH5_MODE

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

PER_DITH5_MODE PER_DITH5_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

PER : Period Value
bits : 5 - 23 (19 bit)


PER_DITH6_MODE

Period
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PER
reset_Mask : 0x0

PER_DITH6_MODE PER_DITH6_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER PER

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

PER : Period Value
bits : 6 - 23 (18 bit)


CC0

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0 CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


CC0_DITH4

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_DITH4 CC0_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC0_DITH5

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_DITH5 CC0_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC0_DITH6

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_DITH6 CC0_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC_DITH4_MODE0

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH4_MODE0 CC_DITH4_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC_DITH5_MODE0

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH5_MODE0 CC_DITH5_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC_DITH6_MODE0

Compare and Capture
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH6_MODE0 CC_DITH6_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC1

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1 CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


CC1_DITH4

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_DITH4 CC1_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC1_DITH5

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_DITH5 CC1_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC1_DITH6

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_DITH6 CC1_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC_DITH4_MODE1

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH4_MODE1 CC_DITH4_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC_DITH5_MODE1

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH5_MODE1 CC_DITH5_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC_DITH6_MODE1

Compare and Capture
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH6_MODE1 CC_DITH6_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC2

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2 CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


CC2_DITH4

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_DITH4 CC2_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC2_DITH5

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_DITH5 CC2_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC2_DITH6

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_DITH6 CC2_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC_DITH4_MODE2

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH4_MODE2 CC_DITH4_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC_DITH5_MODE2

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH5_MODE2 CC_DITH5_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC_DITH6_MODE2

Compare and Capture
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH6_MODE2 CC_DITH6_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_CTRLBSET

Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CTRLBSET TCC_CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT IDXCMD CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot
bits : 2 - 2 (1 bit)

IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)

Enumeration: IDXCMDSelect

0x0 : DISABLE

Command disabled: Index toggles between cycles A and B

0x1 : SET

Set index: cycle B will be forced in the next cycle

0x2 : CLEAR

Clear index: cycle A will be forced in the next cycle

0x3 : HOLD

Hold index: the next cycle will be the same as the current cycle

End of enumeration elements list.

CMD : TCC Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Clear start, restart or retrigger

0x2 : STOP

Force stop

0x3 : UPDATE

Force update or double buffered registers

0x4 : READSYNC

Force COUNT read synchronization

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


CTRLBSET

Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBSET CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT IDXCMD CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot
bits : 2 - 2 (1 bit)

IDXCMD : Ramp Index Command
bits : 3 - 4 (2 bit)

Enumeration: IDXCMDSelect

0 : DISABLE

Command disabled: Index toggles between cycles A and B

1 : SET

Set index: cycle B will be forced in the next cycle

2 : CLEAR

Clear index: cycle A will be forced in the next cycle

3 : HOLD

Hold index: the next cycle will be the same as the current cycle

End of enumeration elements list.

CMD : TCC Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0 : NONE

No action

1 : RETRIGGER

Clear start, restart or retrigger

2 : STOP

Force stop

3 : UPDATE

Force update or double buffered registers

4 : READSYNC

Force COUNT read synchronization

5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


CC3

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC3 CC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


CC3_DITH4

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC3_DITH4 CC3_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC3_DITH5

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC3_DITH5 CC3_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC3_DITH6

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC3_DITH6 CC3_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


CC_DITH4_MODE3

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH4_MODE3 CC_DITH4_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


CC_DITH5_MODE3

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH5_MODE3 CC_DITH5_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


CC_DITH6_MODE3

Compare and Capture
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC[%s]
reset_Mask : 0x0

CC_DITH6_MODE3 CC_DITH6_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_PATTBUF

Pattern Buffer
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_PATTBUF TCC_PATTBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGEB0 PGEB1 PGEB2 PGEB3 PGEB4 PGEB5 PGEB6 PGEB7 PGVB0 PGVB1 PGVB2 PGVB3 PGVB4 PGVB5 PGVB6 PGVB7

PGEB0 : Pattern Generator 0 Output Enable Buffer
bits : 0 - 0 (1 bit)

PGEB1 : Pattern Generator 1 Output Enable Buffer
bits : 1 - 1 (1 bit)

PGEB2 : Pattern Generator 2 Output Enable Buffer
bits : 2 - 2 (1 bit)

PGEB3 : Pattern Generator 3 Output Enable Buffer
bits : 3 - 3 (1 bit)

PGEB4 : Pattern Generator 4 Output Enable Buffer
bits : 4 - 4 (1 bit)

PGEB5 : Pattern Generator 5 Output Enable Buffer
bits : 5 - 5 (1 bit)

PGEB6 : Pattern Generator 6 Output Enable Buffer
bits : 6 - 6 (1 bit)

PGEB7 : Pattern Generator 7 Output Enable Buffer
bits : 7 - 7 (1 bit)

PGVB0 : Pattern Generator 0 Output Enable
bits : 8 - 8 (1 bit)

PGVB1 : Pattern Generator 1 Output Enable
bits : 9 - 9 (1 bit)

PGVB2 : Pattern Generator 2 Output Enable
bits : 10 - 10 (1 bit)

PGVB3 : Pattern Generator 3 Output Enable
bits : 11 - 11 (1 bit)

PGVB4 : Pattern Generator 4 Output Enable
bits : 12 - 12 (1 bit)

PGVB5 : Pattern Generator 5 Output Enable
bits : 13 - 13 (1 bit)

PGVB6 : Pattern Generator 6 Output Enable
bits : 14 - 14 (1 bit)

PGVB7 : Pattern Generator 7 Output Enable
bits : 15 - 15 (1 bit)


PATTBUF

Pattern Buffer
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATTBUF PATTBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGEB0 PGEB1 PGEB2 PGEB3 PGEB4 PGEB5 PGEB6 PGEB7 PGVB0 PGVB1 PGVB2 PGVB3 PGVB4 PGVB5 PGVB6 PGVB7

PGEB0 : Pattern Generator 0 Output Enable Buffer
bits : 0 - 0 (1 bit)

PGEB1 : Pattern Generator 1 Output Enable Buffer
bits : 1 - 1 (1 bit)

PGEB2 : Pattern Generator 2 Output Enable Buffer
bits : 2 - 2 (1 bit)

PGEB3 : Pattern Generator 3 Output Enable Buffer
bits : 3 - 3 (1 bit)

PGEB4 : Pattern Generator 4 Output Enable Buffer
bits : 4 - 4 (1 bit)

PGEB5 : Pattern Generator 5 Output Enable Buffer
bits : 5 - 5 (1 bit)

PGEB6 : Pattern Generator 6 Output Enable Buffer
bits : 6 - 6 (1 bit)

PGEB7 : Pattern Generator 7 Output Enable Buffer
bits : 7 - 7 (1 bit)

PGVB0 : Pattern Generator 0 Output Enable
bits : 8 - 8 (1 bit)

PGVB1 : Pattern Generator 1 Output Enable
bits : 9 - 9 (1 bit)

PGVB2 : Pattern Generator 2 Output Enable
bits : 10 - 10 (1 bit)

PGVB3 : Pattern Generator 3 Output Enable
bits : 11 - 11 (1 bit)

PGVB4 : Pattern Generator 4 Output Enable
bits : 12 - 12 (1 bit)

PGVB5 : Pattern Generator 5 Output Enable
bits : 13 - 13 (1 bit)

PGVB6 : Pattern Generator 6 Output Enable
bits : 14 - 14 (1 bit)

PGVB7 : Pattern Generator 7 Output Enable
bits : 15 - 15 (1 bit)


TCC_PERBUF

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_PERBUF TCC_PERBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERBUF

PERBUF : Period Buffer Value
bits : 0 - 23 (24 bit)


TCC_PERBUF_DITH4

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

TCC_PERBUF_DITH4 TCC_PERBUF_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)

PERBUF : Period Buffer Value
bits : 4 - 23 (20 bit)


TCC_PERBUF_DITH5

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

TCC_PERBUF_DITH5 TCC_PERBUF_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

PERBUF : Period Buffer Value
bits : 5 - 23 (19 bit)


TCC_PERBUF_DITH6

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

TCC_PERBUF_DITH6 TCC_PERBUF_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

PERBUF : Period Buffer Value
bits : 6 - 23 (18 bit)


PERBUF

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERBUF PERBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERBUF

PERBUF : Period Buffer Value
bits : 0 - 23 (24 bit)


PERBUF_DITH4

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERBUF_DITH4 PERBUF_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)

PERBUF : Period Buffer Value
bits : 4 - 23 (20 bit)


PERBUF_DITH5

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERBUF_DITH5 PERBUF_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

PERBUF : Period Buffer Value
bits : 5 - 23 (19 bit)


PERBUF_DITH6

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERBUF_DITH6 PERBUF_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

PERBUF : Period Buffer Value
bits : 6 - 23 (18 bit)


PERBUF_DITH4_MODE

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

PERBUF_DITH4_MODE PERBUF_DITH4_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 3 (4 bit)

PERBUF : Period Buffer Value
bits : 4 - 23 (20 bit)


PERBUF_DITH5_MODE

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

PERBUF_DITH5_MODE PERBUF_DITH5_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

PERBUF : Period Buffer Value
bits : 5 - 23 (19 bit)


PERBUF_DITH6_MODE

Period Buffer
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PERBUF
reset_Mask : 0x0

PERBUF_DITH6_MODE PERBUF_DITH6_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF PERBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

PERBUF : Period Buffer Value
bits : 6 - 23 (18 bit)


CCBUF0

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF0 CCBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


CCBUF0_DITH4

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF0_DITH4 CCBUF0_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF0_DITH5

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF0_DITH5 CCBUF0_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF0_DITH6

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF0_DITH6 CCBUF0_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF_DITH4_MODE0

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH4_MODE0 CCBUF_DITH4_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF_DITH5_MODE0

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH5_MODE0 CCBUF_DITH5_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF_DITH6_MODE0

Compare and Capture Buffer
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH6_MODE0 CCBUF_DITH6_MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF1

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF1 CCBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


CCBUF1_DITH4

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF1_DITH4 CCBUF1_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF1_DITH5

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF1_DITH5 CCBUF1_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF1_DITH6

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF1_DITH6 CCBUF1_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF_DITH4_MODE1

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH4_MODE1 CCBUF_DITH4_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF_DITH5_MODE1

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH5_MODE1 CCBUF_DITH5_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF_DITH6_MODE1

Compare and Capture Buffer
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH6_MODE1 CCBUF_DITH6_MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF2

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF2 CCBUF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


CCBUF2_DITH4

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF2_DITH4 CCBUF2_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF2_DITH5

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF2_DITH5 CCBUF2_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF2_DITH6

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF2_DITH6 CCBUF2_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF_DITH4_MODE2

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH4_MODE2 CCBUF_DITH4_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF_DITH5_MODE2

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH5_MODE2 CCBUF_DITH5_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF_DITH6_MODE2

Compare and Capture Buffer
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH6_MODE2 CCBUF_DITH6_MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF3

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF3 CCBUF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


CCBUF3_DITH4

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF3_DITH4 CCBUF3_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF3_DITH5

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF3_DITH5 CCBUF3_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF3_DITH6

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF3_DITH6 CCBUF3_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


CCBUF_DITH4_MODE3

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH4_MODE3 CCBUF_DITH4_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


CCBUF_DITH5_MODE3

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH5_MODE3 CCBUF_DITH5_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


CCBUF_DITH6_MODE3

Compare and Capture Buffer
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF[%s]
reset_Mask : 0x0

CCBUF_DITH6_MODE3 CCBUF_DITH6_MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)


TCC_SYNCBUSY

Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCC_SYNCBUSY TCC_SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PATT WAVE PER CC0 CC1 CC2 CC3

SWRST : Swrst Busy
bits : 0 - 0 (1 bit)

ENABLE : Enable Busy
bits : 1 - 1 (1 bit)

CTRLB : Ctrlb Busy
bits : 2 - 2 (1 bit)

STATUS : Status Busy
bits : 3 - 3 (1 bit)

COUNT : Count Busy
bits : 4 - 4 (1 bit)

PATT : Pattern Busy
bits : 5 - 5 (1 bit)

WAVE : Wave Busy
bits : 6 - 6 (1 bit)

PER : Period Busy
bits : 7 - 7 (1 bit)

CC0 : Compare Channel 0 Busy
bits : 8 - 8 (1 bit)

CC1 : Compare Channel 1 Busy
bits : 9 - 9 (1 bit)

CC2 : Compare Channel 2 Busy
bits : 10 - 10 (1 bit)

CC3 : Compare Channel 3 Busy
bits : 11 - 11 (1 bit)


SYNCBUSY

Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PATT WAVE PER CC0 CC1 CC2 CC3

SWRST : Swrst Busy
bits : 0 - 0 (1 bit)

ENABLE : Enable Busy
bits : 1 - 1 (1 bit)

CTRLB : Ctrlb Busy
bits : 2 - 2 (1 bit)

STATUS : Status Busy
bits : 3 - 3 (1 bit)

COUNT : Count Busy
bits : 4 - 4 (1 bit)

PATT : Pattern Busy
bits : 5 - 5 (1 bit)

WAVE : Wave Busy
bits : 6 - 6 (1 bit)

PER : Period Busy
bits : 7 - 7 (1 bit)

CC0 : Compare Channel 0 Busy
bits : 8 - 8 (1 bit)

CC1 : Compare Channel 1 Busy
bits : 9 - 9 (1 bit)

CC2 : Compare Channel 2 Busy
bits : 10 - 10 (1 bit)

CC3 : Compare Channel 3 Busy
bits : 11 - 11 (1 bit)


TCC_CC0

Compare and Capture
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CC0 TCC_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


TCC_CC0_DITH4

Compare and Capture
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC0_DITH4 TCC_CC0_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


TCC_CC0_DITH5

Compare and Capture
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC0_DITH5 TCC_CC0_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


TCC_CC0_DITH6

Compare and Capture
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC0_DITH6 TCC_CC0_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_FCTRLA

Recoverable Fault A Configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_FCTRLA TCC_FCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC KEEP QUAL BLANK RESTART HALT CHSEL CAPTURE BLANKPRESC BLANKVAL FILTERVAL

SRC : Fault A Source
bits : 0 - 1 (2 bit)

Enumeration: SRCSelect

0x0 : DISABLE

Fault input disabled

0x1 : ENABLE

MCEx (x=0,1) event input

0x2 : INVERT

Inverted MCEx (x=0,1) event input

0x3 : ALTFAULT

Alternate fault (A or B) state at the end of the previous period

End of enumeration elements list.

KEEP : Fault A Keeper
bits : 3 - 3 (1 bit)

QUAL : Fault A Qualification
bits : 4 - 4 (1 bit)

BLANK : Fault A Blanking Mode
bits : 5 - 6 (2 bit)

Enumeration: BLANKSelect

0x0 : START

Blanking applied from start of the ramp

0x1 : RISE

Blanking applied from rising edge of the output waveform

0x2 : FALL

Blanking applied from falling edge of the output waveform

0x3 : BOTH

Blanking applied from each toggle of the output waveform

End of enumeration elements list.

RESTART : Fault A Restart
bits : 7 - 7 (1 bit)

HALT : Fault A Halt Mode
bits : 8 - 9 (2 bit)

Enumeration: HALTSelect

0x0 : DISABLE

Halt action disabled

0x1 : HW

Hardware halt action

0x2 : SW

Software halt action

0x3 : NR

Non-recoverable fault

End of enumeration elements list.

CHSEL : Fault A Capture Channel
bits : 10 - 11 (2 bit)

Enumeration: CHSELSelect

0x0 : CC0

Capture value stored in channel 0

0x1 : CC1

Capture value stored in channel 1

0x2 : CC2

Capture value stored in channel 2

0x3 : CC3

Capture value stored in channel 3

End of enumeration elements list.

CAPTURE : Fault A Capture Action
bits : 12 - 14 (3 bit)

Enumeration: CAPTURESelect

0x0 : DISABLE

No capture

0x1 : CAPT

Capture on fault

0x2 : CAPTMIN

Minimum capture

0x3 : CAPTMAX

Maximum capture

0x4 : LOCMIN

Minimum local detection

0x5 : LOCMAX

Maximum local detection

0x6 : DERIV0

Minimum and maximum local detection

0x7 : CAPTMARK

Capture with ramp index as MSB value

End of enumeration elements list.

BLANKPRESC : Fault A Blanking Prescaler
bits : 15 - 15 (1 bit)

BLANKVAL : Fault A Blanking Time
bits : 16 - 23 (8 bit)

FILTERVAL : Fault A Filter Value
bits : 24 - 27 (4 bit)


FCTRLA

Recoverable Fault A Configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCTRLA FCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC KEEP QUAL BLANK RESTART HALT CHSEL CAPTURE BLANKPRESC BLANKVAL FILTERVAL

SRC : Fault A Source
bits : 0 - 1 (2 bit)

Enumeration: SRCSelect

0 : DISABLE

Fault input disabled

1 : ENABLE

MCEx (x=0,1) event input

2 : INVERT

Inverted MCEx (x=0,1) event input

3 : ALTFAULT

Alternate fault (A or B) state at the end of the previous period

End of enumeration elements list.

KEEP : Fault A Keeper
bits : 3 - 3 (1 bit)

QUAL : Fault A Qualification
bits : 4 - 4 (1 bit)

BLANK : Fault A Blanking Mode
bits : 5 - 6 (2 bit)

Enumeration: BLANKSelect

0 : START

Blanking applied from start of the ramp

1 : RISE

Blanking applied from rising edge of the output waveform

2 : FALL

Blanking applied from falling edge of the output waveform

3 : BOTH

Blanking applied from each toggle of the output waveform

End of enumeration elements list.

RESTART : Fault A Restart
bits : 7 - 7 (1 bit)

HALT : Fault A Halt Mode
bits : 8 - 9 (2 bit)

Enumeration: HALTSelect

0 : DISABLE

Halt action disabled

1 : HW

Hardware halt action

2 : SW

Software halt action

3 : NR

Non-recoverable fault

End of enumeration elements list.

CHSEL : Fault A Capture Channel
bits : 10 - 11 (2 bit)

Enumeration: CHSELSelect

0 : CC0

Capture value stored in channel 0

1 : CC1

Capture value stored in channel 1

2 : CC2

Capture value stored in channel 2

3 : CC3

Capture value stored in channel 3

End of enumeration elements list.

CAPTURE : Fault A Capture Action
bits : 12 - 14 (3 bit)

Enumeration: CAPTURESelect

0 : DISABLE

No capture

1 : CAPT

Capture on fault

2 : CAPTMIN

Minimum capture

3 : CAPTMAX

Maximum capture

4 : LOCMIN

Minimum local detection

5 : LOCMAX

Maximum local detection

6 : DERIV0

Minimum and maximum local detection

7 : CAPTMARK

Capture with ramp index as MSB value

End of enumeration elements list.

BLANKPRESC : Fault A Blanking Prescaler
bits : 15 - 15 (1 bit)

BLANKVAL : Fault A Blanking Time
bits : 16 - 23 (8 bit)

FILTERVAL : Fault A Filter Value
bits : 24 - 27 (4 bit)


TCC_CC1

Compare and Capture
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CC1 TCC_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Channel Compare/Capture Value
bits : 0 - 23 (24 bit)


TCC_CC1_DITH4

Compare and Capture
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC1_DITH4 TCC_CC1_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 3 (4 bit)

CC : Channel Compare/Capture Value
bits : 4 - 23 (20 bit)


TCC_CC1_DITH5

Compare and Capture
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC1_DITH5 TCC_CC1_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 4 (5 bit)

CC : Channel Compare/Capture Value
bits : 5 - 23 (19 bit)


TCC_CC1_DITH6

Compare and Capture
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CC%s
reset_Mask : 0x0

TCC_CC1_DITH6 TCC_CC1_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHER CC

DITHER : Dithering Cycle Number
bits : 0 - 5 (6 bit)

CC : Channel Compare/Capture Value
bits : 6 - 23 (18 bit)


TCC_CCBUF0

Compare and Capture Buffer
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCC_CCBUF0 TCC_CCBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 23 (24 bit)


TCC_CCBUF0_DITH4

Compare and Capture Buffer
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF0_DITH4 TCC_CCBUF0_DITH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF DITHERBUF

CCBUF : Channel Compare/Capture Buffer Value
bits : 0 - 3 (4 bit)

DITHERBUF : Dithering Buffer Cycle Number
bits : 4 - 23 (20 bit)


TCC_CCBUF0_DITH5

Compare and Capture Buffer
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF0_DITH5 TCC_CCBUF0_DITH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 4 (5 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 5 - 23 (19 bit)


TCC_CCBUF0_DITH6

Compare and Capture Buffer
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CCBUF%s
reset_Mask : 0x0

TCC_CCBUF0_DITH6 TCC_CCBUF0_DITH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DITHERBUF CCBUF

DITHERBUF : Dithering Buffer Cycle Number
bits : 0 - 5 (6 bit)

CCBUF : Channel Compare/Capture Buffer Value
bits : 6 - 23 (18 bit)



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