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SUPC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

INTENCLR

BODVDD

BODCORE

VREG

VREF

INTENSET

INTFLAG

STATUS


INTENCLR

Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODVDDRDY BODVDDDET BVDDSRDY BODCORERDY BODCOREDET BCORESRDY

BODVDDRDY : BODVDD Ready
bits : 0 - 0 (1 bit)

BODVDDDET : BODVDD Detection
bits : 1 - 1 (1 bit)

BVDDSRDY : BODVDD Synchronization Ready
bits : 2 - 2 (1 bit)

BODCORERDY : BODCORE Ready
bits : 3 - 3 (1 bit)

BODCOREDET : BODCORE Detection
bits : 4 - 4 (1 bit)

BCORESRDY : BODCORE Synchronization Ready
bits : 5 - 5 (1 bit)


BODVDD

BODVDD Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODVDD BODVDD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HYST ACTION STDBYCFG RUNSTDBY ACTCFG PSEL LEVEL

ENABLE : Enable
bits : 1 - 1 (1 bit)

HYST : Hysteresis Enable
bits : 2 - 2 (1 bit)

ACTION : Action when Threshold Crossed
bits : 3 - 4 (2 bit)

Enumeration: ACTIONSelect

0x0 : NONE

No action

0x1 : RESET

The BOD33 generates a reset

0x2 : INT

The BOD33 generates an interrupt

End of enumeration elements list.

STDBYCFG : Configuration in Standby mode
bits : 5 - 5 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ACTCFG : Configuration in Active mode
bits : 8 - 8 (1 bit)

PSEL : Prescaler Select
bits : 12 - 15 (4 bit)

Enumeration: PSELSelect

0x0 : DIV2

Divide clock by 2

0x1 : DIV4

Divide clock by 4

0x2 : DIV8

Divide clock by 8

0x3 : DIV16

Divide clock by 16

0x4 : DIV32

Divide clock by 32

0x5 : DIV64

Divide clock by 64

0x6 : DIV128

Divide clock by 128

0x7 : DIV256

Divide clock by 256

0x8 : DIV512

Divide clock by 512

0x9 : DIV1024

Divide clock by 1024

0xa : DIV2048

Divide clock by 2048

0xb : DIV4096

Divide clock by 4096

0xc : DIV8192

Divide clock by 8192

0xd : DIV16384

Divide clock by 16384

0xe : DIV32768

Divide clock by 32768

0xf : DIV65536

Divide clock by 65536

End of enumeration elements list.

LEVEL : Threshold Level for VDD
bits : 16 - 21 (6 bit)


BODCORE

BODCORE Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODCORE BODCORE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HYST ACTION STDBYCFG RUNSTDBY ACTCFG PSEL LEVEL

ENABLE : Enable
bits : 1 - 1 (1 bit)

HYST : Hysteresis Enable
bits : 2 - 2 (1 bit)

ACTION : Action when Threshold Crossed
bits : 3 - 4 (2 bit)

Enumeration: ACTIONSelect

0x0 : NONE

No action

0x1 : RESET

The BOD12 generates a reset

0x2 : INT

The BOD12 generates an interrupt

End of enumeration elements list.

STDBYCFG : Configuration in Standby mode
bits : 5 - 5 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ACTCFG : Configuration in Active mode
bits : 8 - 8 (1 bit)

PSEL : Prescaler Select
bits : 12 - 15 (4 bit)

Enumeration: PSELSelect

0x0 : DIV2

Divide clock by 2

0x1 : DIV4

Divide clock by 4

0x2 : DIV8

Divide clock by 8

0x3 : DIV16

Divide clock by 16

0x4 : DIV32

Divide clock by 32

0x5 : DIV64

Divide clock by 64

0x6 : DIV128

Divide clock by 128

0x7 : DIV256

Divide clock by 256

0x8 : DIV512

Divide clock by 512

0x9 : DIV1024

Divide clock by 1024

0xa : DIV2048

Divide clock by 2048

0xb : DIV4096

Divide clock by 4096

0xc : DIV8192

Divide clock by 8192

0xd : DIV16384

Divide clock by 16384

0xe : DIV32768

Divide clock by 32768

0xf : DIV65536

Divide clock by 65536

End of enumeration elements list.

LEVEL : Threshold Level
bits : 16 - 21 (6 bit)


VREG

VREG Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG VREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY

ENABLE : Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)


VREF

VREF Control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEN VREFOE RUNSTDBY ONDEMAND SEL

TSEN : Temperature Sensor Output Enable
bits : 1 - 1 (1 bit)

VREFOE : Voltage Reference Output Enable
bits : 2 - 2 (1 bit)

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Contrl
bits : 7 - 7 (1 bit)

SEL : Voltage Reference Selection
bits : 16 - 19 (4 bit)

Enumeration: SELSelect

0x0 : 1V024

1.024V voltage reference typical value

0x2 : 2V048

2.048V voltage reference typical value

0x3 : 4V096

4.096V voltage reference typical value

End of enumeration elements list.


INTENSET

Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODVDDRDY BODVDDDET BVDDSRDY BODCORERDY BODCOREDET BCORESRDY

BODVDDRDY : BODVDD Ready
bits : 0 - 0 (1 bit)

BODVDDDET : BODVDD Detection
bits : 1 - 1 (1 bit)

BVDDSRDY : BODVDD Synchronization Ready
bits : 2 - 2 (1 bit)

BODCORERDY : BODCORE Ready
bits : 3 - 3 (1 bit)

BODCOREDET : BODCORE Detection
bits : 4 - 4 (1 bit)

BCORESRDY : BODCORE Synchronization Ready
bits : 5 - 5 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODVDDRDY BODVDDDET BVDDSRDY BODCORERDY BODCOREDET BCORESRDY

BODVDDRDY : BODVDD Ready
bits : 0 - 0 (1 bit)

BODVDDDET : BODVDD Detection
bits : 1 - 1 (1 bit)

BVDDSRDY : BODVDD Synchronization Ready
bits : 2 - 2 (1 bit)

BODCORERDY : BODCORE Ready
bits : 3 - 3 (1 bit)

BODCOREDET : BODCORE Detection
bits : 4 - 4 (1 bit)

BCORESRDY : BODCORE Synchronization Ready
bits : 5 - 5 (1 bit)


STATUS

Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODVDDRDY BODVDDDET BVDDSRDY BODCORERDY BODCOREDET BCORESRDY

BODVDDRDY : BODVDD Ready
bits : 0 - 0 (1 bit)
access : read-only

BODVDDDET : BODVDD Detection
bits : 1 - 1 (1 bit)
access : read-only

BVDDSRDY : BODVDD Synchronization Ready
bits : 2 - 2 (1 bit)
access : read-only

BODCORERDY : BODCORE Ready
bits : 3 - 3 (1 bit)
access : read-only

BODCOREDET : BODCORE Detection
bits : 4 - 4 (1 bit)
access : read-only

BCORESRDY : BODCORE Synchronization Ready
bits : 5 - 5 (1 bit)
access : read-only



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