GCLK

Registers

CTRLA

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWRST : Software Reset
bits : 0 - 0 (1 bit)

PCHCTRL0

Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL23

Peripheral Clock Control
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL24

Peripheral Clock Control
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL5

Generic Clock Generator Control
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL25

Peripheral Clock Control
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL26

Peripheral Clock Control
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL27

Peripheral Clock Control
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL6

Generic Clock Generator Control
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL28

Peripheral Clock Control
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL29

Peripheral Clock Control
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL30

Peripheral Clock Control
address_offset : 0x1744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL1

Peripheral Clock Control
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL31

Peripheral Clock Control
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL7

Generic Clock Generator Control
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL32

Peripheral Clock Control
address_offset : 0x1940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL33

Peripheral Clock Control
address_offset : 0x1A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL34

Peripheral Clock Control
address_offset : 0x1B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL35

Peripheral Clock Control
address_offset : 0x1C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL8

Generic Clock Generator Control
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL36

Peripheral Clock Control
address_offset : 0x1D68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL37

Peripheral Clock Control
address_offset : 0x1E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL38

Peripheral Clock Control
address_offset : 0x1F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL39

Peripheral Clock Control
address_offset : 0x20B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL2

Peripheral Clock Control
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL40

Peripheral Clock Control
address_offset : 0x21D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL3

Peripheral Clock Control
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL4

Peripheral Clock Control
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL5

Peripheral Clock Control
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

SYNCBUSY

Synchronization Busy
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SWRST : Software Reset Synchroniation Busy bit
bits : 0 - 0 (1 bit)
access : read-only

GENCTRL0 : Generic Clock Generator Control 0 Synchronization Busy bits
bits : 2 - 2 (1 bit)
access : read-only

Enumeration: GENCTRL0Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL1 : Generic Clock Generator Control 1 Synchronization Busy bits
bits : 3 - 3 (1 bit)
access : read-only

Enumeration: GENCTRL1Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL2 : Generic Clock Generator Control 2 Synchronization Busy bits
bits : 4 - 4 (1 bit)
access : read-only

Enumeration: GENCTRL2Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL3 : Generic Clock Generator Control 3 Synchronization Busy bits
bits : 5 - 5 (1 bit)
access : read-only

Enumeration: GENCTRL3Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL4 : Generic Clock Generator Control 4 Synchronization Busy bits
bits : 6 - 6 (1 bit)
access : read-only

Enumeration: GENCTRL4Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL5 : Generic Clock Generator Control 5 Synchronization Busy bits
bits : 7 - 7 (1 bit)
access : read-only

Enumeration: GENCTRL5Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL6 : Generic Clock Generator Control 6 Synchronization Busy bits
bits : 8 - 8 (1 bit)
access : read-only

Enumeration: GENCTRL6Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL7 : Generic Clock Generator Control 7 Synchronization Busy bits
bits : 9 - 9 (1 bit)
access : read-only

Enumeration: GENCTRL7Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL8 : Generic Clock Generator Control 8 Synchronization Busy bits
bits : 10 - 10 (1 bit)
access : read-only

Enumeration: GENCTRL8Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL0

Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL6

Peripheral Clock Control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL7

Peripheral Clock Control
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL8

Peripheral Clock Control
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL9

Peripheral Clock Control
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL1

Generic Clock Generator Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL10

Peripheral Clock Control
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL11

Peripheral Clock Control
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL12

Peripheral Clock Control
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL2

Generic Clock Generator Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL13

Peripheral Clock Control
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL14

Peripheral Clock Control
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL15

Peripheral Clock Control
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL16

Peripheral Clock Control
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL3

Generic Clock Generator Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL17

Peripheral Clock Control
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL18

Peripheral Clock Control
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL19

Peripheral Clock Control
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL20

Peripheral Clock Control
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL4

Generic Clock Generator Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 2 (3 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC48M

OSC48M oscillator output

0x7 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL21

Peripheral Clock Control
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL22

Peripheral Clock Control
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

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ChipSelect

GCLK

Peripheral Memory Blocks

Registers

CTRLA

PCHCTRL0

PCHCTRL23

PCHCTRL24

GENCTRL5

PCHCTRL25

PCHCTRL26

PCHCTRL27

GENCTRL6

PCHCTRL28

PCHCTRL29

PCHCTRL30

PCHCTRL1

PCHCTRL31

GENCTRL7

PCHCTRL32

PCHCTRL33

PCHCTRL34

PCHCTRL35

GENCTRL8

PCHCTRL36

PCHCTRL37

PCHCTRL38

PCHCTRL39

PCHCTRL2

PCHCTRL40

PCHCTRL3

PCHCTRL4

PCHCTRL5

SYNCBUSY

GENCTRL0

PCHCTRL6

PCHCTRL7

PCHCTRL8

PCHCTRL9

GENCTRL1

PCHCTRL10

PCHCTRL11

PCHCTRL12

GENCTRL2

PCHCTRL13

PCHCTRL14

PCHCTRL15

PCHCTRL16

GENCTRL3

PCHCTRL17

PCHCTRL18

PCHCTRL19

PCHCTRL20

GENCTRL4

PCHCTRL21

PCHCTRL22