\n

TAL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLA

INTSTATUS6

INTSTATUS7

INTSTATUS8

INTSTATUS9

INTSTATUS10

INTSTATUS11

CTICTRLA0

INTSTATUS12

CTIMASK0

INTSTATUS13

INTSTATUS14

INTSTATUS15

INTSTATUS16

INTSTATUS17

CTICTRLA1

INTSTATUS18

CTIMASK1

INTSTATUS19

INTSTATUS20

INTSTATUS21

INTSTATUS22

RSTCTRL

INTSTATUS0

DMACPUSEL0

INTSTATUS23

CTICTRLA2

INTSTATUS24

EVCPUSEL0

CTIMASK2

INTSTATUS25

INTSTATUS26

EXTCTRL

EICCPUSEL0

INTSTATUS27

INTSTATUS28

INTCPUSEL0

INTSTATUS29

INTCPUSEL1

INTSTATUS30

EVCTRL

IRQTRIG

INTSTATUS1

INTENCLR

INTSTATUS2

INTENSET

INTFLAG

INTSTATUS3

GLOBMASK

HALT

INTSTATUS4

RESTART

BRKSTATUS

INTSTATUS5


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)


INTSTATUS6

Interrupt n Status
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS6 INTSTATUS6 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS7

Interrupt n Status
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS7 INTSTATUS7 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS8

Interrupt n Status
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS8 INTSTATUS8 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS9

Interrupt n Status
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS9 INTSTATUS9 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS10

Interrupt n Status
address_offset : 0x1B7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS10 INTSTATUS10 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS11

Interrupt n Status
address_offset : 0x1E2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS11 INTSTATUS11 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


CTICTRLA0

Cross-Trigger Interface n Control A
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTICTRLA0 CTICTRLA0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACTION RESTART

ACTION : Action when global break issued
bits : 0 - 1 (2 bit)

Enumeration: ACTIONSelect

0x0 : BREAK

Break when requested

0x1 : INTERRUPT

Trigger DBG interrupt instead of break

0x2 : IGNORE

Ignore break request

End of enumeration elements list.

RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)


INTSTATUS12

Interrupt n Status
address_offset : 0x20E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS12 INTSTATUS12 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


CTIMASK0

Cross-Trigger Interface n Mask
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTIMASK0 CTIMASK0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EVBRK : Event Break Master
bits : 6 - 6 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


INTSTATUS13

Interrupt n Status
address_offset : 0x23B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS13 INTSTATUS13 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS14

Interrupt n Status
address_offset : 0x269 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS14 INTSTATUS14 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS15

Interrupt n Status
address_offset : 0x298 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS15 INTSTATUS15 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS16

Interrupt n Status
address_offset : 0x2C8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS16 INTSTATUS16 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS17

Interrupt n Status
address_offset : 0x2F9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS17 INTSTATUS17 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


CTICTRLA1

Cross-Trigger Interface n Control A
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTICTRLA1 CTICTRLA1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACTION RESTART

ACTION : Action when global break issued
bits : 0 - 1 (2 bit)

Enumeration: ACTIONSelect

0x0 : BREAK

Break when requested

0x1 : INTERRUPT

Trigger DBG interrupt instead of break

0x2 : IGNORE

Ignore break request

End of enumeration elements list.

RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)


INTSTATUS18

Interrupt n Status
address_offset : 0x32B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS18 INTSTATUS18 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


CTIMASK1

Cross-Trigger Interface n Mask
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTIMASK1 CTIMASK1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EVBRK : Event Break Master
bits : 6 - 6 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


INTSTATUS19

Interrupt n Status
address_offset : 0x35E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS19 INTSTATUS19 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS20

Interrupt n Status
address_offset : 0x392 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS20 INTSTATUS20 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS21

Interrupt n Status
address_offset : 0x3C7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS21 INTSTATUS21 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS22

Interrupt n Status
address_offset : 0x3FD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS22 INTSTATUS22 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


RSTCTRL

Reset Control
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCTRL RSTCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

INTSTATUS0

Interrupt n Status
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS0 INTSTATUS0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


DMACPUSEL0

DMA Channel Interrupts CPU Select 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACPUSEL0 DMACPUSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 : DMA Channel 0 Interrupt CPU Select
bits : 0 - 0 (1 bit)

CH1 : DMA Channel 1 Interrupt CPU Select
bits : 2 - 2 (1 bit)

CH2 : DMA Channel 2 Interrupt CPU Select
bits : 4 - 4 (1 bit)

CH3 : DMA Channel 3 Interrupt CPU Select
bits : 6 - 6 (1 bit)

CH4 : DMA Channel 4 Interrupt CPU Select
bits : 8 - 8 (1 bit)

CH5 : DMA Channel 5 Interrupt CPU Select
bits : 10 - 10 (1 bit)

CH6 : DMA Channel 6 Interrupt CPU Select
bits : 12 - 12 (1 bit)

CH7 : DMA Channel 7 Interrupt CPU Select
bits : 14 - 14 (1 bit)

CH8 : DMA Channel 8 Interrupt CPU Select
bits : 16 - 16 (1 bit)

CH9 : DMA Channel 9 Interrupt CPU Select
bits : 18 - 18 (1 bit)

CH10 : DMA Channel 10 Interrupt CPU Select
bits : 20 - 20 (1 bit)

CH11 : DMA Channel 11 Interrupt CPU Select
bits : 22 - 22 (1 bit)


INTSTATUS23

Interrupt n Status
address_offset : 0x434 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS23 INTSTATUS23 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


CTICTRLA2

Cross-Trigger Interface n Control A
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTICTRLA2 CTICTRLA2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACTION RESTART

ACTION : Action when global break issued
bits : 0 - 1 (2 bit)

Enumeration: ACTIONSelect

0x0 : BREAK

Break when requested

0x1 : INTERRUPT

Trigger DBG interrupt instead of break

0x2 : IGNORE

Ignore break request

End of enumeration elements list.

RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)


INTSTATUS24

Interrupt n Status
address_offset : 0x46C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS24 INTSTATUS24 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


EVCPUSEL0

EVSYS Channel Interrupts CPU Select 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCPUSEL0 EVCPUSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 : Event Channel 0 Interrupt CPU Select
bits : 0 - 0 (1 bit)

CH1 : Event Channel 1 Interrupt CPU Select
bits : 2 - 2 (1 bit)

CH2 : Event Channel 2 Interrupt CPU Select
bits : 4 - 4 (1 bit)

CH3 : Event Channel 3 Interrupt CPU Select
bits : 6 - 6 (1 bit)

CH4 : Event Channel 4 Interrupt CPU Select
bits : 8 - 8 (1 bit)

CH5 : Event Channel 5 Interrupt CPU Select
bits : 10 - 10 (1 bit)

CH6 : Event Channel 6 Interrupt CPU Select
bits : 12 - 12 (1 bit)

CH7 : Event Channel 7 Interrupt CPU Select
bits : 14 - 14 (1 bit)

CH8 : Event Channel 8 Interrupt CPU Select
bits : 16 - 16 (1 bit)

CH9 : Event Channel 9 Interrupt CPU Select
bits : 18 - 18 (1 bit)

CH10 : Event Channel 10 Interrupt CPU Select
bits : 20 - 20 (1 bit)

CH11 : Event Channel 11 Interrupt CPU Select
bits : 22 - 22 (1 bit)


CTIMASK2

Cross-Trigger Interface n Mask
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTIMASK2 CTIMASK2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EVBRK : Event Break Master
bits : 6 - 6 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


INTSTATUS25

Interrupt n Status
address_offset : 0x4A5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS25 INTSTATUS25 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS26

Interrupt n Status
address_offset : 0x4DF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS26 INTSTATUS26 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


EXTCTRL

External Break Control
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTCTRL EXTCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE INV

ENABLE : Enable BRK Pin
bits : 0 - 0 (1 bit)

INV : Invert BRK Pin
bits : 1 - 1 (1 bit)


EICCPUSEL0

EIC External Interrupts CPU Select 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EICCPUSEL0 EICCPUSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6 EXTINT7 EXTINT8 EXTINT9 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15

EXTINT0 : External Interrupt 0 CPU Select
bits : 0 - 0 (1 bit)

EXTINT1 : External Interrupt 1 CPU Select
bits : 2 - 2 (1 bit)

EXTINT2 : External Interrupt 2 CPU Select
bits : 4 - 4 (1 bit)

EXTINT3 : External Interrupt 3 CPU Select
bits : 6 - 6 (1 bit)

EXTINT4 : External Interrupt 4 CPU Select
bits : 8 - 8 (1 bit)

EXTINT5 : External Interrupt 5 CPU Select
bits : 10 - 10 (1 bit)

EXTINT6 : External Interrupt 6 CPU Select
bits : 12 - 12 (1 bit)

EXTINT7 : External Interrupt 7 CPU Select
bits : 14 - 14 (1 bit)

EXTINT8 : External Interrupt 8 CPU Select
bits : 16 - 16 (1 bit)

EXTINT9 : External Interrupt 9 CPU Select
bits : 18 - 18 (1 bit)

EXTINT10 : External Interrupt 10 CPU Select
bits : 20 - 20 (1 bit)

EXTINT11 : External Interrupt 11 CPU Select
bits : 22 - 22 (1 bit)

EXTINT12 : External Interrupt 12 CPU Select
bits : 24 - 24 (1 bit)

EXTINT13 : External Interrupt 13 CPU Select
bits : 26 - 26 (1 bit)

EXTINT14 : External Interrupt 14 CPU Select
bits : 28 - 28 (1 bit)

EXTINT15 : External Interrupt 15 CPU Select
bits : 30 - 30 (1 bit)


INTSTATUS27

Interrupt n Status
address_offset : 0x51A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS27 INTSTATUS27 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTSTATUS28

Interrupt n Status
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS28 INTSTATUS28 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTCPUSEL0

Interrupts CPU Select 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCPUSEL0 INTCPUSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTSTATUS29

Interrupt n Status
address_offset : 0x593 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS29 INTSTATUS29 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTCPUSEL1

Interrupts CPU Select 1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCPUSEL1 INTCPUSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTSTATUS30

Interrupt n Status
address_offset : 0x5D1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS30 INTSTATUS30 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


EVCTRL

Event Control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRKEI BRKEO

BRKEI : Break Input Event Enable
bits : 0 - 0 (1 bit)

BRKEO : Break Output Event Enable
bits : 1 - 1 (1 bit)


IRQTRIG

Interrupt Trigger
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQTRIG IRQTRIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE IRQNUM OVERRIDE

ENABLE : Trigger Enable
bits : 0 - 0 (1 bit)

IRQNUM : Interrupt Request Number
bits : 1 - 5 (5 bit)

OVERRIDE : Interrupt Request Override Value
bits : 8 - 15 (8 bit)


INTSTATUS1

Interrupt n Status
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS1 INTSTATUS1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRK

BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)


INTSTATUS2

Interrupt n Status
address_offset : 0x83 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS2 INTSTATUS2 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRK

BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BRK

BRK : Break
bits : 0 - 0 (1 bit)


INTSTATUS3

Interrupt n Status
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS3 INTSTATUS3 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


GLOBMASK

Global Break Requests Mask
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLOBMASK GLOBMASK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EVBRK : Event Break Master
bits : 6 - 6 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


HALT

Debug Halt Request
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HALT HALT write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EVBRK : Event Break Master
bits : 6 - 6 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


INTSTATUS4

Interrupt n Status
address_offset : 0xCA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS4 INTSTATUS4 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)


RESTART

Debug Restart Request
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RESTART RESTART write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CM0P PPP EXTBRK

CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)

PPP : PPP Break Master
bits : 1 - 1 (1 bit)

EXTBRK : External Break Master
bits : 7 - 7 (1 bit)


BRKSTATUS

Break Request Status
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRKSTATUS BRKSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM0P PPP EVBRK EXTBRK

CM0P : CM0P Break Request
bits : 0 - 1 (2 bit)

Enumeration: CM0PSelect

0x0 : INT_RUN

CM0P running, by internal request

0x1 : INT_HALT

CM0P halted, by internal request

0x2 : EXT_RUN

CM0P running, by external request

0x3 : EXT_HALT

CM0P halted, by external request

End of enumeration elements list.

PPP : PPP Break Request
bits : 2 - 3 (2 bit)

Enumeration: PPPSelect

0x0 : INT_RUN

PPP running, by internal request

0x1 : INT_HALT

PPP halted, by internal request

0x2 : EXT_RUN

PPP running, by external request

0x3 : EXT_HALT

PPP halted, by external request

End of enumeration elements list.

EVBRK : Event Break Request
bits : 12 - 13 (2 bit)

Enumeration: EVBRKSelect

0x0 : INT_RUN

EVBRK running

End of enumeration elements list.

EXTBRK : External Break Request
bits : 14 - 15 (2 bit)

Enumeration: EXTBRKSelect

0x0 : INT_RUN

External CPU running, by internal request

0x1 : INT_HALT

External CPU halted, by internal request

0x2 : EXT_RUN

External CPU running, by external request

0x3 : EXT_HALT

External CPU halted, by external request

End of enumeration elements list.


INTSTATUS5

Interrupt n Status
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS5 INTSTATUS5 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)

IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)

IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)

IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)

IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)

IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)

IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)

IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)



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