\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
Interrupt n Status
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x1B7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x1E2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x20E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x23B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x269 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x298 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x2C8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x2F9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x32 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x32B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x35E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x392 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x3C7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x3FD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Reset Control
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt n Status
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
DMA Channel Interrupts CPU Select 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : DMA Channel 0 Interrupt CPU Select
bits : 0 - 0 (1 bit)
CH1 : DMA Channel 1 Interrupt CPU Select
bits : 2 - 2 (1 bit)
CH2 : DMA Channel 2 Interrupt CPU Select
bits : 4 - 4 (1 bit)
CH3 : DMA Channel 3 Interrupt CPU Select
bits : 6 - 6 (1 bit)
CH4 : DMA Channel 4 Interrupt CPU Select
bits : 8 - 8 (1 bit)
CH5 : DMA Channel 5 Interrupt CPU Select
bits : 10 - 10 (1 bit)
CH6 : DMA Channel 6 Interrupt CPU Select
bits : 12 - 12 (1 bit)
CH7 : DMA Channel 7 Interrupt CPU Select
bits : 14 - 14 (1 bit)
CH8 : DMA Channel 8 Interrupt CPU Select
bits : 16 - 16 (1 bit)
CH9 : DMA Channel 9 Interrupt CPU Select
bits : 18 - 18 (1 bit)
CH10 : DMA Channel 10 Interrupt CPU Select
bits : 20 - 20 (1 bit)
CH11 : DMA Channel 11 Interrupt CPU Select
bits : 22 - 22 (1 bit)
Interrupt n Status
address_offset : 0x434 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Cross-Trigger Interface n Control A
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTION : Action when global break issued
bits : 0 - 1 (2 bit)
Enumeration: ACTIONSelect
0x0 : BREAK
Break when requested
0x1 : INTERRUPT
Trigger DBG interrupt instead of break
0x2 : IGNORE
Ignore break request
End of enumeration elements list.
RESTART : Action when global restart issued
bits : 2 - 2 (1 bit)
Interrupt n Status
address_offset : 0x46C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
EVSYS Channel Interrupts CPU Select 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Event Channel 0 Interrupt CPU Select
bits : 0 - 0 (1 bit)
CH1 : Event Channel 1 Interrupt CPU Select
bits : 2 - 2 (1 bit)
CH2 : Event Channel 2 Interrupt CPU Select
bits : 4 - 4 (1 bit)
CH3 : Event Channel 3 Interrupt CPU Select
bits : 6 - 6 (1 bit)
CH4 : Event Channel 4 Interrupt CPU Select
bits : 8 - 8 (1 bit)
CH5 : Event Channel 5 Interrupt CPU Select
bits : 10 - 10 (1 bit)
CH6 : Event Channel 6 Interrupt CPU Select
bits : 12 - 12 (1 bit)
CH7 : Event Channel 7 Interrupt CPU Select
bits : 14 - 14 (1 bit)
CH8 : Event Channel 8 Interrupt CPU Select
bits : 16 - 16 (1 bit)
CH9 : Event Channel 9 Interrupt CPU Select
bits : 18 - 18 (1 bit)
CH10 : Event Channel 10 Interrupt CPU Select
bits : 20 - 20 (1 bit)
CH11 : Event Channel 11 Interrupt CPU Select
bits : 22 - 22 (1 bit)
Cross-Trigger Interface n Mask
address_offset : 0x4A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x4A5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x4DF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
External Break Control
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable BRK Pin
bits : 0 - 0 (1 bit)
INV : Invert BRK Pin
bits : 1 - 1 (1 bit)
EIC External Interrupts CPU Select 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTINT0 : External Interrupt 0 CPU Select
bits : 0 - 0 (1 bit)
EXTINT1 : External Interrupt 1 CPU Select
bits : 2 - 2 (1 bit)
EXTINT2 : External Interrupt 2 CPU Select
bits : 4 - 4 (1 bit)
EXTINT3 : External Interrupt 3 CPU Select
bits : 6 - 6 (1 bit)
EXTINT4 : External Interrupt 4 CPU Select
bits : 8 - 8 (1 bit)
EXTINT5 : External Interrupt 5 CPU Select
bits : 10 - 10 (1 bit)
EXTINT6 : External Interrupt 6 CPU Select
bits : 12 - 12 (1 bit)
EXTINT7 : External Interrupt 7 CPU Select
bits : 14 - 14 (1 bit)
EXTINT8 : External Interrupt 8 CPU Select
bits : 16 - 16 (1 bit)
EXTINT9 : External Interrupt 9 CPU Select
bits : 18 - 18 (1 bit)
EXTINT10 : External Interrupt 10 CPU Select
bits : 20 - 20 (1 bit)
EXTINT11 : External Interrupt 11 CPU Select
bits : 22 - 22 (1 bit)
EXTINT12 : External Interrupt 12 CPU Select
bits : 24 - 24 (1 bit)
EXTINT13 : External Interrupt 13 CPU Select
bits : 26 - 26 (1 bit)
EXTINT14 : External Interrupt 14 CPU Select
bits : 28 - 28 (1 bit)
EXTINT15 : External Interrupt 15 CPU Select
bits : 30 - 30 (1 bit)
Interrupt n Status
address_offset : 0x51A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupts CPU Select 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt n Status
address_offset : 0x593 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupts CPU Select 1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt n Status
address_offset : 0x5D1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Event Control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEI : Break Input Event Enable
bits : 0 - 0 (1 bit)
BRKEO : Break Output Event Enable
bits : 1 - 1 (1 bit)
Interrupt Trigger
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Trigger Enable
bits : 0 - 0 (1 bit)
IRQNUM : Interrupt Request Number
bits : 1 - 5 (5 bit)
OVERRIDE : Interrupt Request Override Value
bits : 8 - 15 (8 bit)
Interrupt n Status
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt n Status
address_offset : 0x83 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK : Break
bits : 0 - 0 (1 bit)
Interrupt n Status
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Global Break Requests Mask
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Debug Halt Request
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EVBRK : Event Break Master
bits : 6 - 6 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Interrupt n Status
address_offset : 0xCA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Debug Restart Request
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Master
bits : 0 - 0 (1 bit)
PPP : PPP Break Master
bits : 1 - 1 (1 bit)
EXTBRK : External Break Master
bits : 7 - 7 (1 bit)
Break Request Status
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CM0P : CM0P Break Request
bits : 0 - 1 (2 bit)
Enumeration: CM0PSelect
0x0 : INT_RUN
CM0P running, by internal request
0x1 : INT_HALT
CM0P halted, by internal request
0x2 : EXT_RUN
CM0P running, by external request
0x3 : EXT_HALT
CM0P halted, by external request
End of enumeration elements list.
PPP : PPP Break Request
bits : 2 - 3 (2 bit)
Enumeration: PPPSelect
0x0 : INT_RUN
PPP running, by internal request
0x1 : INT_HALT
PPP halted, by internal request
0x2 : EXT_RUN
PPP running, by external request
0x3 : EXT_HALT
PPP halted, by external request
End of enumeration elements list.
EVBRK : Event Break Request
bits : 12 - 13 (2 bit)
Enumeration: EVBRKSelect
0x0 : INT_RUN
EVBRK running
End of enumeration elements list.
EXTBRK : External Break Request
bits : 14 - 15 (2 bit)
Enumeration: EXTBRKSelect
0x0 : INT_RUN
External CPU running, by internal request
0x1 : INT_HALT
External CPU halted, by internal request
0x2 : EXT_RUN
External CPU running, by external request
0x3 : EXT_HALT
External CPU halted, by external request
End of enumeration elements list.
Interrupt n Status
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ0 : Interrupt Status for Interrupt Request 0 within Interrupt n
bits : 0 - 0 (1 bit)
IRQ1 : Interrupt Status for Interrupt Request 1 within Interrupt n
bits : 1 - 1 (1 bit)
IRQ2 : Interrupt Status for Interrupt Request 2 within Interrupt n
bits : 2 - 2 (1 bit)
IRQ3 : Interrupt Status for Interrupt Request 3 within Interrupt n
bits : 3 - 3 (1 bit)
IRQ4 : Interrupt Status for Interrupt Request 4 within Interrupt n
bits : 4 - 4 (1 bit)
IRQ5 : Interrupt Status for Interrupt Request 5 within Interrupt n
bits : 5 - 5 (1 bit)
IRQ6 : Interrupt Status for Interrupt Request 6 within Interrupt n
bits : 6 - 6 (1 bit)
IRQ7 : Interrupt Status for Interrupt Request 7 within Interrupt n
bits : 7 - 7 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.